1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18
19 #include <video/mipi_display.h>
20
21 #include <drm/bridge/dw_mipi_dsi.h>
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_print.h>
24
25 #define HWVER_130 0x31333000 /* IP version 1.30 */
26 #define HWVER_131 0x31333100 /* IP version 1.31 */
27
28 /* DSI digital registers & bit definitions */
29 #define DSI_VERSION 0x00
30 #define VERSION GENMASK(31, 8)
31
32 /* DSI wrapper registers & bit definitions */
33 /* Note: registers are named as in the Reference Manual */
34 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
35 #define WCFGR_DSIM BIT(0) /* DSI Mode */
36 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */
37
38 #define DSI_WCR 0x0404 /* Wrapper Control Reg */
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
40
41 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */
42 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
43 #define WISR_RRS BIT(12) /* Regulator Ready Status */
44
45 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */
46 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */
47 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
48
49 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
50 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
51 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
52 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
53 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
54 #define WRPCR_REGEN BIT(24) /* REGulator ENable */
55 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */
56 #define IDF_MIN 1
57 #define IDF_MAX 7
58 #define NDIV_MIN 10
59 #define NDIV_MAX 125
60 #define ODF_MIN 1
61 #define ODF_MAX 8
62
63 /* dsi color format coding according to the datasheet */
64 enum dsi_color {
65 DSI_RGB565_CONF1,
66 DSI_RGB565_CONF2,
67 DSI_RGB565_CONF3,
68 DSI_RGB666_CONF1,
69 DSI_RGB666_CONF2,
70 DSI_RGB888,
71 };
72
73 #define LANE_MIN_KBPS 31250
74 #define LANE_MAX_KBPS 500000
75
76 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
77 #define SLEEP_US 1000
78 #define TIMEOUT_US 200000
79
80 struct dw_mipi_dsi_stm {
81 void __iomem *base;
82 struct device *dev;
83 struct clk *pllref_clk;
84 struct clk *pclk;
85 struct clk_hw txbyte_clk;
86 struct dw_mipi_dsi *dsi;
87 struct dw_mipi_dsi_plat_data pdata;
88 u32 hw_version;
89 int lane_min_kbps;
90 int lane_max_kbps;
91 struct regulator *vdd_supply;
92 };
93
dsi_write(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 val)94 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
95 {
96 writel(val, dsi->base + reg);
97 }
98
dsi_read(struct dw_mipi_dsi_stm * dsi,u32 reg)99 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
100 {
101 return readl(dsi->base + reg);
102 }
103
dsi_set(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 mask)104 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
105 {
106 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
107 }
108
dsi_clear(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 mask)109 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
110 {
111 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
112 }
113
dsi_update_bits(struct dw_mipi_dsi_stm * dsi,u32 reg,u32 mask,u32 val)114 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
115 u32 mask, u32 val)
116 {
117 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
118 }
119
dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)120 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
121 {
122 switch (fmt) {
123 case MIPI_DSI_FMT_RGB888:
124 return DSI_RGB888;
125 case MIPI_DSI_FMT_RGB666:
126 return DSI_RGB666_CONF2;
127 case MIPI_DSI_FMT_RGB666_PACKED:
128 return DSI_RGB666_CONF1;
129 case MIPI_DSI_FMT_RGB565:
130 return DSI_RGB565_CONF1;
131 default:
132 DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
133 }
134 return DSI_RGB888;
135 }
136
dsi_pll_get_clkout_khz(int clkin_khz,int idf,int ndiv,int odf)137 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
138 {
139 int divisor = idf * odf;
140
141 /* prevent from division by 0 */
142 if (!divisor)
143 return 0;
144
145 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
146 }
147
dsi_pll_get_params(struct dw_mipi_dsi_stm * dsi,int clkin_khz,int clkout_khz,int * idf,int * ndiv,int * odf)148 static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi,
149 int clkin_khz, int clkout_khz,
150 int *idf, int *ndiv, int *odf)
151 {
152 int i, o, n, n_min, n_max;
153 int fvco_min, fvco_max, delta, best_delta; /* all in khz */
154
155 /* Early checks preventing division by 0 & odd results */
156 if (clkin_khz <= 0 || clkout_khz <= 0)
157 return -EINVAL;
158
159 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
160 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
161
162 best_delta = 1000000; /* big started value (1000000khz) */
163
164 for (i = IDF_MIN; i <= IDF_MAX; i++) {
165 /* Compute ndiv range according to Fvco */
166 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
167 n_max = (fvco_max * i) / (2 * clkin_khz);
168
169 /* No need to continue idf loop if we reach ndiv max */
170 if (n_min >= NDIV_MAX)
171 break;
172
173 /* Clamp ndiv to valid values */
174 if (n_min < NDIV_MIN)
175 n_min = NDIV_MIN;
176 if (n_max > NDIV_MAX)
177 n_max = NDIV_MAX;
178
179 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
180 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
181 /* Check ndiv according to vco range */
182 if (n < n_min || n > n_max)
183 continue;
184 /* Check if new delta is better & saves parameters */
185 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
186 clkout_khz;
187 if (delta < 0)
188 delta = -delta;
189 if (delta < best_delta) {
190 *idf = i;
191 *ndiv = n;
192 *odf = o;
193 best_delta = delta;
194 }
195 /* fast return in case of "perfect result" */
196 if (!delta)
197 return 0;
198 }
199 }
200
201 return 0;
202 }
203
204 #define clk_to_dw_mipi_dsi_stm(clk) \
205 container_of(clk, struct dw_mipi_dsi_stm, txbyte_clk)
206
dw_mipi_dsi_clk_disable(struct clk_hw * clk)207 static void dw_mipi_dsi_clk_disable(struct clk_hw *clk)
208 {
209 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
210
211 DRM_DEBUG_DRIVER("\n");
212
213 /* Disable the DSI PLL */
214 dsi_clear(dsi, DSI_WRPCR, WRPCR_PLLEN);
215
216 /* Disable the regulator */
217 dsi_clear(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
218 }
219
dw_mipi_dsi_clk_enable(struct clk_hw * clk)220 static int dw_mipi_dsi_clk_enable(struct clk_hw *clk)
221 {
222 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
223 u32 val;
224 int ret;
225
226 DRM_DEBUG_DRIVER("\n");
227
228 /* Enable the regulator */
229 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
230 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_RRS,
231 SLEEP_US, TIMEOUT_US);
232 if (ret)
233 DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
234
235 /* Enable the DSI PLL & wait for its lock */
236 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
237 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
238 SLEEP_US, TIMEOUT_US);
239 if (ret)
240 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
241
242 return 0;
243 }
244
dw_mipi_dsi_clk_is_enabled(struct clk_hw * hw)245 static int dw_mipi_dsi_clk_is_enabled(struct clk_hw *hw)
246 {
247 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
248
249 return dsi_read(dsi, DSI_WRPCR) & WRPCR_PLLEN;
250 }
251
dw_mipi_dsi_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)252 static unsigned long dw_mipi_dsi_clk_recalc_rate(struct clk_hw *hw,
253 unsigned long parent_rate)
254 {
255 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
256 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
257 u32 val;
258
259 DRM_DEBUG_DRIVER("\n");
260
261 pll_in_khz = (unsigned int)(parent_rate / 1000);
262
263 val = dsi_read(dsi, DSI_WRPCR);
264
265 idf = (val & WRPCR_IDF) >> 11;
266 if (!idf)
267 idf = 1;
268 ndiv = (val & WRPCR_NDIV) >> 2;
269 odf = int_pow(2, (val & WRPCR_ODF) >> 16);
270
271 /* Get the adjusted pll out value */
272 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
273
274 return (unsigned long)pll_out_khz * 1000;
275 }
276
dw_mipi_dsi_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)277 static int dw_mipi_dsi_clk_determine_rate(struct clk_hw *hw,
278 struct clk_rate_request *req)
279 {
280 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
281 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
282 int ret;
283
284 DRM_DEBUG_DRIVER("\n");
285
286 pll_in_khz = (unsigned int)(req->best_parent_rate / 1000);
287
288 /* Compute best pll parameters */
289 idf = 0;
290 ndiv = 0;
291 odf = 0;
292
293 ret = dsi_pll_get_params(dsi, pll_in_khz, req->rate / 1000,
294 &idf, &ndiv, &odf);
295 if (ret)
296 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
297
298 /* Get the adjusted pll out value */
299 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
300
301 req->rate = pll_out_khz * 1000;
302
303 return 0;
304 }
305
dw_mipi_dsi_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)306 static int dw_mipi_dsi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
307 unsigned long parent_rate)
308 {
309 struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
310 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
311 int ret;
312 u32 val;
313
314 DRM_DEBUG_DRIVER("\n");
315
316 pll_in_khz = (unsigned int)(parent_rate / 1000);
317
318 /* Compute best pll parameters */
319 idf = 0;
320 ndiv = 0;
321 odf = 0;
322
323 ret = dsi_pll_get_params(dsi, pll_in_khz, rate / 1000, &idf, &ndiv, &odf);
324 if (ret)
325 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
326
327 /* Get the adjusted pll out value */
328 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
329
330 /* Set the PLL division factors */
331 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
332 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
333
334 /* Compute uix4 & set the bit period in high-speed mode */
335 val = 4000000 / pll_out_khz;
336 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
337
338 return 0;
339 }
340
dw_mipi_dsi_clk_unregister(void * data)341 static void dw_mipi_dsi_clk_unregister(void *data)
342 {
343 struct dw_mipi_dsi_stm *dsi = data;
344
345 DRM_DEBUG_DRIVER("\n");
346
347 of_clk_del_provider(dsi->dev->of_node);
348 clk_hw_unregister(&dsi->txbyte_clk);
349 }
350
351 static const struct clk_ops dw_mipi_dsi_stm_clk_ops = {
352 .enable = dw_mipi_dsi_clk_enable,
353 .disable = dw_mipi_dsi_clk_disable,
354 .is_enabled = dw_mipi_dsi_clk_is_enabled,
355 .recalc_rate = dw_mipi_dsi_clk_recalc_rate,
356 .determine_rate = dw_mipi_dsi_clk_determine_rate,
357 .set_rate = dw_mipi_dsi_clk_set_rate,
358 };
359
360 static struct clk_init_data cdata_init = {
361 .name = "ck_dsi_phy",
362 .ops = &dw_mipi_dsi_stm_clk_ops,
363 .parent_names = (const char * []) {"ck_hse"},
364 .num_parents = 1,
365 };
366
dw_mipi_dsi_clk_register(struct dw_mipi_dsi_stm * dsi,struct device * dev)367 static int dw_mipi_dsi_clk_register(struct dw_mipi_dsi_stm *dsi,
368 struct device *dev)
369 {
370 struct device_node *node = dev->of_node;
371 int ret;
372
373 DRM_DEBUG_DRIVER("Registering clk\n");
374
375 dsi->txbyte_clk.init = &cdata_init;
376
377 ret = clk_hw_register(dev, &dsi->txbyte_clk);
378 if (ret)
379 return ret;
380
381 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get,
382 &dsi->txbyte_clk);
383 if (ret)
384 clk_hw_unregister(&dsi->txbyte_clk);
385
386 return ret;
387 }
388
dw_mipi_dsi_phy_init(void * priv_data)389 static int dw_mipi_dsi_phy_init(void *priv_data)
390 {
391 struct dw_mipi_dsi_stm *dsi = priv_data;
392 int ret;
393
394 ret = clk_prepare_enable(dsi->txbyte_clk.clk);
395 return ret;
396 }
397
dw_mipi_dsi_phy_power_on(void * priv_data)398 static void dw_mipi_dsi_phy_power_on(void *priv_data)
399 {
400 struct dw_mipi_dsi_stm *dsi = priv_data;
401
402 DRM_DEBUG_DRIVER("\n");
403
404 /* Enable the DSI wrapper */
405 dsi_set(dsi, DSI_WCR, WCR_DSIEN);
406 }
407
dw_mipi_dsi_phy_power_off(void * priv_data)408 static void dw_mipi_dsi_phy_power_off(void *priv_data)
409 {
410 struct dw_mipi_dsi_stm *dsi = priv_data;
411
412 DRM_DEBUG_DRIVER("\n");
413
414 clk_disable_unprepare(dsi->txbyte_clk.clk);
415
416 /* Disable the DSI wrapper */
417 dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
418 }
419
420 static int
dw_mipi_dsi_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)421 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
422 unsigned long mode_flags, u32 lanes, u32 format,
423 unsigned int *lane_mbps)
424 {
425 struct dw_mipi_dsi_stm *dsi = priv_data;
426 unsigned int pll_in_khz, pll_out_khz;
427 int ret, bpp;
428
429 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
430
431 /* Compute requested pll out */
432 bpp = mipi_dsi_pixel_format_to_bpp(format);
433 pll_out_khz = mode->clock * bpp / lanes;
434
435 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
436 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
437 pll_out_khz = (pll_out_khz * 12) / 10;
438
439 if (pll_out_khz > dsi->lane_max_kbps) {
440 pll_out_khz = dsi->lane_max_kbps;
441 DRM_WARN("Warning max phy mbps is used\n");
442 }
443 if (pll_out_khz < dsi->lane_min_kbps) {
444 pll_out_khz = dsi->lane_min_kbps;
445 DRM_WARN("Warning min phy mbps is used\n");
446 }
447
448 ret = clk_set_rate((dsi->txbyte_clk.clk), pll_out_khz * 1000);
449 if (ret)
450 DRM_DEBUG_DRIVER("ERROR Could not set rate of %d to %s clk->name",
451 pll_out_khz, clk_hw_get_name(&dsi->txbyte_clk));
452
453 /* Select video mode by resetting DSIM bit */
454 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
455
456 /* Select the color coding */
457 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
458 dsi_color_from_mipi(format) << 1);
459
460 *lane_mbps = pll_out_khz / 1000;
461
462 DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
463 pll_in_khz, pll_out_khz, *lane_mbps);
464
465 return 0;
466 }
467
468 #define DSI_PHY_DELAY(fp, vp, mbps) DIV_ROUND_UP((fp) * (mbps) + 1000 * (vp), 8000)
469
470 static int
dw_mipi_dsi_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi_dphy_timing * timing)471 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
472 struct dw_mipi_dsi_dphy_timing *timing)
473 {
474 /*
475 * From STM32MP157 datasheet, valid for STM32F469, STM32F7x9, STM32H747
476 * phy_clkhs2lp_time = (272+136*UI)/(8*UI)
477 * phy_clklp2hs_time = (512+40*UI)/(8*UI)
478 * phy_hs2lp_time = (192+64*UI)/(8*UI)
479 * phy_lp2hs_time = (256+32*UI)/(8*UI)
480 */
481 timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);
482 timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
483 timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);
484 timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
485
486 return 0;
487 }
488
489 #define CLK_TOLERANCE_HZ 50
490
491 static enum drm_mode_status
dw_mipi_dsi_stm_mode_valid(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format)492 dw_mipi_dsi_stm_mode_valid(void *priv_data,
493 const struct drm_display_mode *mode,
494 unsigned long mode_flags, u32 lanes, u32 format)
495 {
496 struct dw_mipi_dsi_stm *dsi = priv_data;
497 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
498 int ret, bpp;
499
500 bpp = mipi_dsi_pixel_format_to_bpp(format);
501 if (bpp < 0)
502 return MODE_BAD;
503
504 /* Compute requested pll out */
505 pll_out_khz = mode->clock * bpp / lanes;
506
507 if (pll_out_khz > dsi->lane_max_kbps)
508 return MODE_CLOCK_HIGH;
509
510 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
511 /* Add 20% to pll out to be higher than pixel bw */
512 pll_out_khz = (pll_out_khz * 12) / 10;
513 } else {
514 if (pll_out_khz < dsi->lane_min_kbps)
515 return MODE_CLOCK_LOW;
516 }
517
518 /* Compute best pll parameters */
519 idf = 0;
520 ndiv = 0;
521 odf = 0;
522 pll_in_khz = clk_get_rate(dsi->pllref_clk) / 1000;
523 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
524 if (ret) {
525 DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
526 return MODE_ERROR;
527 }
528
529 if (!(mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
530 unsigned int px_clock_hz, target_px_clock_hz, lane_mbps;
531 int dsi_short_packet_size_px, hfp, hsync, hbp, delay_to_lp;
532 struct dw_mipi_dsi_dphy_timing dphy_timing;
533
534 /* Get the adjusted pll out value */
535 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
536
537 px_clock_hz = DIV_ROUND_CLOSEST_ULL(1000ULL * pll_out_khz * lanes, bpp);
538 target_px_clock_hz = mode->clock * 1000;
539 /*
540 * Filter modes according to the clock value, particularly useful for
541 * hdmi modes that require precise pixel clocks.
542 */
543 if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
544 px_clock_hz > target_px_clock_hz + CLK_TOLERANCE_HZ)
545 return MODE_CLOCK_RANGE;
546
547 /* sync packets are codes as DSI short packets (4 bytes) */
548 dsi_short_packet_size_px = DIV_ROUND_UP(4 * BITS_PER_BYTE, bpp);
549
550 hfp = mode->hsync_start - mode->hdisplay;
551 hsync = mode->hsync_end - mode->hsync_start;
552 hbp = mode->htotal - mode->hsync_end;
553
554 /* hsync must be longer than 4 bytes HSS packets */
555 if (hsync < dsi_short_packet_size_px)
556 return MODE_HSYNC_NARROW;
557
558 if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
559 /* HBP must be longer than 4 bytes HSE packets */
560 if (hbp < dsi_short_packet_size_px)
561 return MODE_HSYNC_NARROW;
562 hbp -= dsi_short_packet_size_px;
563 } else {
564 /* With sync events HBP extends in the hsync */
565 hbp += hsync - dsi_short_packet_size_px;
566 }
567
568 lane_mbps = pll_out_khz / 1000;
569 ret = dw_mipi_dsi_phy_get_timing(priv_data, lane_mbps, &dphy_timing);
570 if (ret)
571 return MODE_ERROR;
572 /*
573 * In non-burst mode DSI has to enter in LP during HFP
574 * (horizontal front porch) or HBP (horizontal back porch) to
575 * resync with LTDC pixel clock.
576 */
577 delay_to_lp = DIV_ROUND_UP((dphy_timing.data_hs2lp + dphy_timing.data_lp2hs) *
578 lanes * BITS_PER_BYTE, bpp);
579 if (hfp < delay_to_lp && hbp < delay_to_lp)
580 return MODE_HSYNC;
581 }
582
583 return MODE_OK;
584 }
585
586 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = {
587 .init = dw_mipi_dsi_phy_init,
588 .power_on = dw_mipi_dsi_phy_power_on,
589 .power_off = dw_mipi_dsi_phy_power_off,
590 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
591 .get_timing = dw_mipi_dsi_phy_get_timing,
592 };
593
594 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = {
595 .max_data_lanes = 2,
596 .mode_valid = dw_mipi_dsi_stm_mode_valid,
597 .phy_ops = &dw_mipi_dsi_stm_phy_ops,
598 };
599
600 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = {
601 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
602 { },
603 };
604 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
605
dw_mipi_dsi_stm_probe(struct platform_device * pdev)606 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
607 {
608 struct device *dev = &pdev->dev;
609 struct dw_mipi_dsi_stm *dsi;
610 const struct dw_mipi_dsi_plat_data *pdata = of_device_get_match_data(dev);
611 int ret;
612
613 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
614 if (!dsi)
615 return -ENOMEM;
616
617 dsi->base = devm_platform_ioremap_resource(pdev, 0);
618 if (IS_ERR(dsi->base)) {
619 ret = PTR_ERR(dsi->base);
620 DRM_ERROR("Unable to get dsi registers %d\n", ret);
621 return ret;
622 }
623
624 dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");
625 if (IS_ERR(dsi->vdd_supply)) {
626 ret = PTR_ERR(dsi->vdd_supply);
627 dev_err_probe(dev, ret, "Failed to request regulator\n");
628 return ret;
629 }
630
631 ret = regulator_enable(dsi->vdd_supply);
632 if (ret) {
633 DRM_ERROR("Failed to enable regulator: %d\n", ret);
634 return ret;
635 }
636
637 dsi->pllref_clk = devm_clk_get(dev, "ref");
638 if (IS_ERR(dsi->pllref_clk)) {
639 ret = PTR_ERR(dsi->pllref_clk);
640 dev_err_probe(dev, ret, "Unable to get pll reference clock\n");
641 goto err_clk_get;
642 }
643
644 ret = clk_prepare_enable(dsi->pllref_clk);
645 if (ret) {
646 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
647 goto err_clk_get;
648 }
649
650 dsi->pclk = devm_clk_get(dev, "pclk");
651 if (IS_ERR(dsi->pclk)) {
652 ret = PTR_ERR(dsi->pclk);
653 DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
654 goto err_dsi_probe;
655 }
656
657 ret = clk_prepare_enable(dsi->pclk);
658 if (ret) {
659 DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
660 goto err_dsi_probe;
661 }
662
663 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
664 clk_disable_unprepare(dsi->pclk);
665
666 if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
667 ret = -ENODEV;
668 DRM_ERROR("bad dsi hardware version\n");
669 goto err_dsi_probe;
670 }
671
672 /* set lane capabilities according to hw version */
673 dsi->lane_min_kbps = LANE_MIN_KBPS;
674 dsi->lane_max_kbps = LANE_MAX_KBPS;
675 if (dsi->hw_version == HWVER_131) {
676 dsi->lane_min_kbps *= 2;
677 dsi->lane_max_kbps *= 2;
678 }
679
680 dsi->pdata = *pdata;
681 dsi->pdata.base = dsi->base;
682 dsi->pdata.priv_data = dsi;
683
684 dsi->pdata.max_data_lanes = 2;
685 dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops;
686
687 platform_set_drvdata(pdev, dsi);
688
689 dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata);
690 if (IS_ERR(dsi->dsi)) {
691 ret = PTR_ERR(dsi->dsi);
692 dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n");
693 goto err_dsi_probe;
694 }
695
696 /*
697 * We need to wait for the generic bridge to probe before enabling and
698 * register the internal pixel clock.
699 */
700 ret = clk_prepare_enable(dsi->pclk);
701 if (ret) {
702 DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
703 goto err_dsi_probe;
704 }
705
706 ret = dw_mipi_dsi_clk_register(dsi, dev);
707 if (ret) {
708 DRM_ERROR("Failed to register DSI pixel clock: %d\n", ret);
709 clk_disable_unprepare(dsi->pclk);
710 goto err_dsi_probe;
711 }
712
713 clk_disable_unprepare(dsi->pclk);
714
715 return 0;
716
717 err_dsi_probe:
718 clk_disable_unprepare(dsi->pllref_clk);
719 err_clk_get:
720 regulator_disable(dsi->vdd_supply);
721
722 return ret;
723 }
724
dw_mipi_dsi_stm_remove(struct platform_device * pdev)725 static void dw_mipi_dsi_stm_remove(struct platform_device *pdev)
726 {
727 struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
728
729 dw_mipi_dsi_remove(dsi->dsi);
730 clk_disable_unprepare(dsi->pllref_clk);
731 dw_mipi_dsi_clk_unregister(dsi);
732 regulator_disable(dsi->vdd_supply);
733 }
734
dw_mipi_dsi_stm_suspend(struct device * dev)735 static int dw_mipi_dsi_stm_suspend(struct device *dev)
736 {
737 struct dw_mipi_dsi_stm *dsi = dev_get_drvdata(dev);
738
739 DRM_DEBUG_DRIVER("\n");
740
741 clk_disable_unprepare(dsi->pllref_clk);
742 clk_disable_unprepare(dsi->pclk);
743 regulator_disable(dsi->vdd_supply);
744
745 return 0;
746 }
747
dw_mipi_dsi_stm_resume(struct device * dev)748 static int dw_mipi_dsi_stm_resume(struct device *dev)
749 {
750 struct dw_mipi_dsi_stm *dsi = dev_get_drvdata(dev);
751 int ret;
752
753 DRM_DEBUG_DRIVER("\n");
754
755 ret = regulator_enable(dsi->vdd_supply);
756 if (ret) {
757 DRM_ERROR("Failed to enable regulator: %d\n", ret);
758 return ret;
759 }
760
761 ret = clk_prepare_enable(dsi->pclk);
762 if (ret) {
763 regulator_disable(dsi->vdd_supply);
764 DRM_ERROR("Failed to enable pclk: %d\n", ret);
765 return ret;
766 }
767
768 ret = clk_prepare_enable(dsi->pllref_clk);
769 if (ret) {
770 clk_disable_unprepare(dsi->pclk);
771 regulator_disable(dsi->vdd_supply);
772 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
773 return ret;
774 }
775
776 return 0;
777 }
778
779 static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
780 SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
781 dw_mipi_dsi_stm_resume)
782 RUNTIME_PM_OPS(dw_mipi_dsi_stm_suspend,
783 dw_mipi_dsi_stm_resume, NULL)
784 };
785
786 static struct platform_driver dw_mipi_dsi_stm_driver = {
787 .probe = dw_mipi_dsi_stm_probe,
788 .remove = dw_mipi_dsi_stm_remove,
789 .driver = {
790 .of_match_table = dw_mipi_dsi_stm_dt_ids,
791 .name = "stm32-display-dsi",
792 .pm = &dw_mipi_dsi_stm_pm_ops,
793 },
794 };
795
796 module_platform_driver(dw_mipi_dsi_stm_driver);
797
798 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
799 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
800 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver");
801 MODULE_LICENSE("GPL v2");
802