1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _UAPI_XE_DRM_H_ 7 #define _UAPI_XE_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 /* 16 * Please note that modifications to all structs defined here are 17 * subject to backwards-compatibility constraints. 18 * Sections in this file are organized as follows: 19 * 1. IOCTL definition 20 * 2. Extension definition and helper structs 21 * 3. IOCTL's Query structs in the order of the Query's entries. 22 * 4. The rest of IOCTL structs in the order of IOCTL declaration. 23 */ 24 25 /** 26 * DOC: Xe Device Block Diagram 27 * 28 * The diagram below represents a high-level simplification of a discrete 29 * GPU supported by the Xe driver. It shows some device components which 30 * are necessary to understand this API, as well as how their relations 31 * to each other. This diagram does not represent real hardware:: 32 * 33 * ┌──────────────────────────────────────────────────────────────────┐ 34 * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ 35 * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ 36 * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ 37 * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ 38 * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ 39 * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ 40 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 41 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ 42 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 43 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 44 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ 45 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 46 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 47 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ 48 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 49 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 50 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ 51 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 52 * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 53 * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ 54 * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 55 * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ 56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ 57 * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ 58 * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ 59 * └─────────────────────────────Device0───────┬──────────────────────┘ 60 * │ 61 * ───────────────────────┴────────── PCI bus 62 */ 63 64 /** 65 * DOC: Xe uAPI Overview 66 * 67 * This section aims to describe the Xe's IOCTL entries, its structs, and other 68 * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related 69 * entries and usage. 70 * 71 * List of supported IOCTLs: 72 * - &DRM_IOCTL_XE_DEVICE_QUERY 73 * - &DRM_IOCTL_XE_GEM_CREATE 74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET 75 * - &DRM_IOCTL_XE_VM_CREATE 76 * - &DRM_IOCTL_XE_VM_DESTROY 77 * - &DRM_IOCTL_XE_VM_BIND 78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 81 * - &DRM_IOCTL_XE_EXEC 82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE 83 * - &DRM_IOCTL_XE_OBSERVATION 84 * - &DRM_IOCTL_XE_MADVISE 85 * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS 86 * - &DRM_IOCTL_XE_VM_GET_PROPERTY 87 */ 88 89 /* 90 * xe specific ioctls. 91 * 92 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 93 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 94 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 95 */ 96 #define DRM_XE_DEVICE_QUERY 0x00 97 #define DRM_XE_GEM_CREATE 0x01 98 #define DRM_XE_GEM_MMAP_OFFSET 0x02 99 #define DRM_XE_VM_CREATE 0x03 100 #define DRM_XE_VM_DESTROY 0x04 101 #define DRM_XE_VM_BIND 0x05 102 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 103 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 104 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 105 #define DRM_XE_EXEC 0x09 106 #define DRM_XE_WAIT_USER_FENCE 0x0a 107 #define DRM_XE_OBSERVATION 0x0b 108 #define DRM_XE_MADVISE 0x0c 109 #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d 110 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e 111 #define DRM_XE_VM_GET_PROPERTY 0x0f 112 113 /* Must be kept compact -- no holes */ 114 115 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 116 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 117 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 118 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 119 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 120 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 121 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 122 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 123 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 124 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 125 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 126 #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) 127 #define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise) 128 #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr) 129 #define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) 130 #define DRM_IOCTL_XE_VM_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_GET_PROPERTY, struct drm_xe_vm_get_property) 131 132 /** 133 * DOC: Xe IOCTL Extensions 134 * 135 * Before detailing the IOCTLs and its structs, it is important to highlight 136 * that every IOCTL in Xe is extensible. 137 * 138 * Many interfaces need to grow over time. In most cases we can simply 139 * extend the struct and have userspace pass in more data. Another option, 140 * as demonstrated by Vulkan's approach to providing extensions for forward 141 * and backward compatibility, is to use a list of optional structs to 142 * provide those extra details. 143 * 144 * The key advantage to using an extension chain is that it allows us to 145 * redefine the interface more easily than an ever growing struct of 146 * increasing complexity, and for large parts of that interface to be 147 * entirely optional. The downside is more pointer chasing; chasing across 148 * the __user boundary with pointers encapsulated inside u64. 149 * 150 * Example chaining: 151 * 152 * .. code-block:: C 153 * 154 * struct drm_xe_user_extension ext3 { 155 * .next_extension = 0, // end 156 * .name = ..., 157 * }; 158 * struct drm_xe_user_extension ext2 { 159 * .next_extension = (uintptr_t)&ext3, 160 * .name = ..., 161 * }; 162 * struct drm_xe_user_extension ext1 { 163 * .next_extension = (uintptr_t)&ext2, 164 * .name = ..., 165 * }; 166 * 167 * Typically the struct drm_xe_user_extension would be embedded in some uAPI 168 * struct, and in this case we would feed it the head of the chain(i.e ext1), 169 * which would then apply all of the above extensions. 170 */ 171 172 /** 173 * struct drm_xe_user_extension - Base class for defining a chain of extensions 174 */ 175 struct drm_xe_user_extension { 176 /** 177 * @next_extension: 178 * 179 * Pointer to the next struct drm_xe_user_extension, or zero if the end. 180 */ 181 __u64 next_extension; 182 183 /** 184 * @name: Name of the extension. 185 * 186 * Note that the name here is just some integer. 187 * 188 * Also note that the name space for this is not global for the whole 189 * driver, but rather its scope/meaning is limited to the specific piece 190 * of uAPI which has embedded the struct drm_xe_user_extension. 191 */ 192 __u32 name; 193 194 /** 195 * @pad: MBZ 196 * 197 * All undefined bits must be zero. 198 */ 199 __u32 pad; 200 }; 201 202 /** 203 * struct drm_xe_ext_set_property - Generic set property extension 204 * 205 * A generic struct that allows any of the Xe's IOCTL to be extended 206 * with a set_property operation. 207 */ 208 struct drm_xe_ext_set_property { 209 /** @base: base user extension */ 210 struct drm_xe_user_extension base; 211 212 /** @property: property to set */ 213 __u32 property; 214 215 /** @pad: MBZ */ 216 __u32 pad; 217 218 union { 219 /** @value: property value */ 220 __u64 value; 221 /** @ptr: pointer to user value */ 222 __u64 ptr; 223 }; 224 225 /** @reserved: Reserved */ 226 __u64 reserved[2]; 227 }; 228 229 /** 230 * struct drm_xe_engine_class_instance - instance of an engine class 231 * 232 * It is returned as part of the @drm_xe_engine, but it also is used as 233 * the input of engine selection for both @drm_xe_exec_queue_create and 234 * @drm_xe_query_engine_cycles 235 * 236 * The @engine_class can be: 237 * - %DRM_XE_ENGINE_CLASS_RENDER 238 * - %DRM_XE_ENGINE_CLASS_COPY 239 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE 240 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 241 * - %DRM_XE_ENGINE_CLASS_COMPUTE 242 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual 243 * hardware engine class). Used for creating ordered queues of VM 244 * bind operations. 245 */ 246 struct drm_xe_engine_class_instance { 247 #define DRM_XE_ENGINE_CLASS_RENDER 0 248 #define DRM_XE_ENGINE_CLASS_COPY 1 249 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 250 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 251 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 252 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 253 /** @engine_class: engine class id */ 254 __u16 engine_class; 255 /** @engine_instance: engine instance id */ 256 __u16 engine_instance; 257 /** @gt_id: Unique ID of this GT within the PCI Device */ 258 __u16 gt_id; 259 /** @pad: MBZ */ 260 __u16 pad; 261 }; 262 263 /** 264 * struct drm_xe_engine - describe hardware engine 265 */ 266 struct drm_xe_engine { 267 /** @instance: The @drm_xe_engine_class_instance */ 268 struct drm_xe_engine_class_instance instance; 269 270 /** @reserved: Reserved */ 271 __u64 reserved[3]; 272 }; 273 274 /** 275 * struct drm_xe_query_engines - describe engines 276 * 277 * If a query is made with a struct @drm_xe_device_query where .query 278 * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of 279 * struct @drm_xe_query_engines in .data. 280 */ 281 struct drm_xe_query_engines { 282 /** @num_engines: number of engines returned in @engines */ 283 __u32 num_engines; 284 /** @pad: MBZ */ 285 __u32 pad; 286 /** @engines: The returned engines for this device */ 287 struct drm_xe_engine engines[]; 288 }; 289 290 /** 291 * enum drm_xe_memory_class - Supported memory classes. 292 */ 293 enum drm_xe_memory_class { 294 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ 295 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 296 /** 297 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this 298 * represents the memory that is local to the device, which we 299 * call VRAM. Not valid on integrated platforms. 300 */ 301 DRM_XE_MEM_REGION_CLASS_VRAM 302 }; 303 304 /** 305 * struct drm_xe_mem_region - Describes some region as known to 306 * the driver. 307 */ 308 struct drm_xe_mem_region { 309 /** 310 * @mem_class: The memory class describing this region. 311 * 312 * See enum drm_xe_memory_class for supported values. 313 */ 314 __u16 mem_class; 315 /** 316 * @instance: The unique ID for this region, which serves as the 317 * index in the placement bitmask used as argument for 318 * &DRM_IOCTL_XE_GEM_CREATE 319 */ 320 __u16 instance; 321 /** 322 * @min_page_size: Min page-size in bytes for this region. 323 * 324 * When the kernel allocates memory for this region, the 325 * underlying pages will be at least @min_page_size in size. 326 * Buffer objects with an allowable placement in this region must be 327 * created with a size aligned to this value. 328 * GPU virtual address mappings of (parts of) buffer objects that 329 * may be placed in this region must also have their GPU virtual 330 * address and range aligned to this value. 331 * Affected IOCTLS will return %-EINVAL if alignment restrictions are 332 * not met. 333 */ 334 __u32 min_page_size; 335 /** 336 * @total_size: The usable size in bytes for this region. 337 */ 338 __u64 total_size; 339 /** 340 * @used: Estimate of the memory used in bytes for this region. 341 */ 342 __u64 used; 343 /** 344 * @cpu_visible_size: How much of this region can be CPU 345 * accessed, in bytes. 346 * 347 * This will always be <= @total_size, and the remainder (if 348 * any) will not be CPU accessible. If the CPU accessible part 349 * is smaller than @total_size then this is referred to as a 350 * small BAR system. 351 * 352 * On systems without small BAR (full BAR), the probed_size will 353 * always equal the @total_size, since all of it will be CPU 354 * accessible. 355 * 356 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM 357 * regions (for other types the value here will always equal 358 * zero). 359 */ 360 __u64 cpu_visible_size; 361 /** 362 * @cpu_visible_used: Estimate of CPU visible memory used, in 363 * bytes. 364 * 365 * Note this is only currently tracked for 366 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value 367 * here will always be zero). 368 */ 369 __u64 cpu_visible_used; 370 /** @reserved: Reserved */ 371 __u64 reserved[6]; 372 }; 373 374 /** 375 * struct drm_xe_query_mem_regions - describe memory regions 376 * 377 * If a query is made with a struct drm_xe_device_query where .query 378 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses 379 * struct drm_xe_query_mem_regions in .data. 380 */ 381 struct drm_xe_query_mem_regions { 382 /** @num_mem_regions: number of memory regions returned in @mem_regions */ 383 __u32 num_mem_regions; 384 /** @pad: MBZ */ 385 __u32 pad; 386 /** @mem_regions: The returned memory regions for this device */ 387 struct drm_xe_mem_region mem_regions[]; 388 }; 389 390 /** 391 * struct drm_xe_query_config - describe the device configuration 392 * 393 * If a query is made with a struct drm_xe_device_query where .query 394 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses 395 * struct drm_xe_query_config in .data. 396 * 397 * The index in @info can be: 398 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) 399 * and the device revision (next 8 bits) 400 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device 401 * configuration, see list below 402 * 403 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device 404 * has usable VRAM 405 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device 406 * has low latency hint support 407 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the 408 * device has CPU address mirroring support 409 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the 410 * device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION. 411 * This is exposed only on Xe2+. 412 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set 413 * if a queue can be creaed with 414 * %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 415 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment 416 * required by this device, typically SZ_4K or SZ_64K 417 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address 418 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest 419 * available exec queue priority 420 */ 421 struct drm_xe_query_config { 422 /** @num_params: number of parameters returned in info */ 423 __u32 num_params; 424 425 /** @pad: MBZ */ 426 __u32 pad; 427 428 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 429 #define DRM_XE_QUERY_CONFIG_FLAGS 1 430 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 431 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1) 432 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2) 433 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3) 434 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4) 435 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_PURGING_SUPPORT (1 << 5) 436 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 437 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 438 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 439 /** @info: array of elements containing the config info */ 440 __u64 info[]; 441 }; 442 443 /** 444 * struct drm_xe_gt - describe an individual GT. 445 * 446 * To be used with drm_xe_query_gt_list, which will return a list with all the 447 * existing GT individual descriptions. 448 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for 449 * implementing graphics and/or media operations. 450 * 451 * The index in @type can be: 452 * - %DRM_XE_QUERY_GT_TYPE_MAIN 453 * - %DRM_XE_QUERY_GT_TYPE_MEDIA 454 */ 455 struct drm_xe_gt { 456 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 457 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 458 /** @type: GT type: Main or Media */ 459 __u16 type; 460 /** @tile_id: Tile ID where this GT lives (Information only) */ 461 __u16 tile_id; 462 /** @gt_id: Unique ID of this GT within the PCI Device */ 463 __u16 gt_id; 464 /** @pad: MBZ */ 465 __u16 pad[3]; 466 /** @reference_clock: A clock frequency for timestamp */ 467 __u32 reference_clock; 468 /** 469 * @near_mem_regions: Bit mask of instances from 470 * drm_xe_query_mem_regions that are nearest to the current engines 471 * of this GT. 472 * Each index in this mask refers directly to the struct 473 * drm_xe_query_mem_regions' instance, no assumptions should 474 * be made about order. The type of each region is described 475 * by struct drm_xe_query_mem_regions' mem_class. 476 */ 477 __u64 near_mem_regions; 478 /** 479 * @far_mem_regions: Bit mask of instances from 480 * drm_xe_query_mem_regions that are far from the engines of this GT. 481 * In general, they have extra indirections when compared to the 482 * @near_mem_regions. For a discrete device this could mean system 483 * memory and memory living in a different tile. 484 * Each index in this mask refers directly to the struct 485 * drm_xe_query_mem_regions' instance, no assumptions should 486 * be made about order. The type of each region is described 487 * by struct drm_xe_query_mem_regions' mem_class. 488 */ 489 __u64 far_mem_regions; 490 /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ 491 __u16 ip_ver_major; 492 /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ 493 __u16 ip_ver_minor; 494 /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ 495 __u16 ip_ver_rev; 496 /** @pad2: MBZ */ 497 __u16 pad2; 498 /** @reserved: Reserved */ 499 __u64 reserved[7]; 500 }; 501 502 /** 503 * struct drm_xe_query_gt_list - A list with GT description items. 504 * 505 * If a query is made with a struct drm_xe_device_query where .query 506 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct 507 * drm_xe_query_gt_list in .data. 508 */ 509 struct drm_xe_query_gt_list { 510 /** @num_gt: number of GT items returned in gt_list */ 511 __u32 num_gt; 512 /** @pad: MBZ */ 513 __u32 pad; 514 /** @gt_list: The GT list returned for this device */ 515 struct drm_xe_gt gt_list[]; 516 }; 517 518 /** 519 * struct drm_xe_query_topology_mask - describe the topology mask of a GT 520 * 521 * This is the hardware topology which reflects the internal physical 522 * structure of the GPU. 523 * 524 * If a query is made with a struct drm_xe_device_query where .query 525 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses 526 * struct drm_xe_query_topology_mask in .data. 527 * 528 * The @type can be: 529 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices 530 * (DSS) available for geometry operations. For example a query response 531 * containing the following in mask: 532 * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` 533 * means 32 DSS are available for geometry. 534 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices 535 * (DSS) available for compute operations. For example a query response 536 * containing the following in mask: 537 * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` 538 * means 32 DSS are available for compute. 539 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type 540 * may be omitted if the driver is unable to query the mask from the 541 * hardware. 542 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) 543 * available per Dual Sub Slices (DSS). For example a query response 544 * containing the following in mask: 545 * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` 546 * means each DSS has 16 SIMD8 EUs. This type may be omitted if device 547 * doesn't have SIMD8 EUs. 548 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution 549 * Units (EU) available per Dual Sub Slices (DSS). For example a query 550 * response containing the following in mask: 551 * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` 552 * means each DSS has 16 SIMD16 EUs. This type may be omitted if device 553 * doesn't have SIMD16 EUs. 554 */ 555 struct drm_xe_query_topology_mask { 556 /** @gt_id: GT ID the mask is associated with */ 557 __u16 gt_id; 558 559 #define DRM_XE_TOPO_DSS_GEOMETRY 1 560 #define DRM_XE_TOPO_DSS_COMPUTE 2 561 #define DRM_XE_TOPO_L3_BANK 3 562 #define DRM_XE_TOPO_EU_PER_DSS 4 563 #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5 564 /** @type: type of mask */ 565 __u16 type; 566 567 /** @num_bytes: number of bytes in requested mask */ 568 __u32 num_bytes; 569 570 /** @mask: little-endian mask of @num_bytes */ 571 __u8 mask[]; 572 }; 573 574 /** 575 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps 576 * 577 * If a query is made with a struct drm_xe_device_query where .query is equal to 578 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles 579 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and 580 * .data points to this allocated structure. 581 * 582 * The query returns the engine cycles, which along with GT's @reference_clock, 583 * can be used to calculate the engine timestamp. In addition the 584 * query returns a set of cpu timestamps that indicate when the command 585 * streamer cycle count was captured. 586 */ 587 struct drm_xe_query_engine_cycles { 588 /** 589 * @eci: This is input by the user and is the engine for which command 590 * streamer cycles is queried. 591 */ 592 struct drm_xe_engine_class_instance eci; 593 594 /** 595 * @clockid: This is input by the user and is the reference clock id for 596 * CPU timestamp. For definition, see clock_gettime(2) and 597 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, 598 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. 599 */ 600 __s32 clockid; 601 602 /** @width: Width of the engine cycle counter in bits. */ 603 __u32 width; 604 605 /** 606 * @engine_cycles: Engine cycles as read from its register 607 * at 0x358 offset. 608 */ 609 __u64 engine_cycles; 610 611 /** 612 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before 613 * reading the engine_cycles register using the reference clockid set by the 614 * user. 615 */ 616 __u64 cpu_timestamp; 617 618 /** 619 * @cpu_delta: Time delta in ns captured around reading the lower dword 620 * of the engine_cycles register. 621 */ 622 __u64 cpu_delta; 623 }; 624 625 /** 626 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version 627 * 628 * Given a uc_type this will return the branch, major, minor and patch version 629 * of the micro-controller firmware. 630 */ 631 struct drm_xe_query_uc_fw_version { 632 /** @uc_type: The micro-controller type to query firmware version */ 633 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 634 #define XE_QUERY_UC_TYPE_HUC 1 635 __u16 uc_type; 636 637 /** @pad: MBZ */ 638 __u16 pad; 639 640 /** @branch_ver: branch uc fw version */ 641 __u32 branch_ver; 642 /** @major_ver: major uc fw version */ 643 __u32 major_ver; 644 /** @minor_ver: minor uc fw version */ 645 __u32 minor_ver; 646 /** @patch_ver: patch uc fw version */ 647 __u32 patch_ver; 648 649 /** @pad2: MBZ */ 650 __u32 pad2; 651 652 /** @reserved: Reserved */ 653 __u64 reserved; 654 }; 655 656 /** 657 * struct drm_xe_query_pxp_status - query if PXP is ready 658 * 659 * If PXP is enabled and no fatal error has occurred, the status will be set to 660 * one of the following values: 661 * 0: PXP init still in progress 662 * 1: PXP init complete 663 * 664 * If PXP is not enabled or something has gone wrong, the query will be failed 665 * with one of the following error codes: 666 * -ENODEV: PXP not supported or disabled; 667 * -EIO: fatal error occurred during init, so PXP will never be enabled; 668 * -EINVAL: incorrect value provided as part of the query; 669 * -EFAULT: error copying the memory between kernel and userspace. 670 * 671 * The status can only be 0 in the first few seconds after driver load. If 672 * everything works as expected, the status will transition to init complete in 673 * less than 1 second, while in case of errors the driver might take longer to 674 * start returning an error code, but it should still take less than 10 seconds. 675 * 676 * The supported session type bitmask is based on the values in 677 * enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore 678 * is not reported in the bitmask. 679 * 680 */ 681 struct drm_xe_query_pxp_status { 682 /** @status: current PXP status */ 683 __u32 status; 684 685 /** @supported_session_types: bitmask of supported PXP session types */ 686 __u32 supported_session_types; 687 }; 688 689 /** 690 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main 691 * structure to query device information 692 * 693 * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* 694 * and sets the value in the query member. This determines the type of 695 * the structure provided by the driver in data, among struct drm_xe_query_*. 696 * 697 * The @query can be: 698 * - %DRM_XE_DEVICE_QUERY_ENGINES 699 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS 700 * - %DRM_XE_DEVICE_QUERY_CONFIG 701 * - %DRM_XE_DEVICE_QUERY_GT_LIST 702 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware 703 * configuration of the device such as information on slices, memory, 704 * caches, and so on. It is provided as a table of key / value 705 * attributes. 706 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 707 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 708 * - %DRM_XE_DEVICE_QUERY_PXP_STATUS 709 * 710 * If size is set to 0, the driver fills it with the required size for 711 * the requested type of data to query. If size is equal to the required 712 * size, the queried information is copied into data. If size is set to 713 * a value different from 0 and different from the required size, the 714 * IOCTL call returns -EINVAL. 715 * 716 * For example the following code snippet allows retrieving and printing 717 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: 718 * 719 * .. code-block:: C 720 * 721 * struct drm_xe_query_engines *engines; 722 * struct drm_xe_device_query query = { 723 * .extensions = 0, 724 * .query = DRM_XE_DEVICE_QUERY_ENGINES, 725 * .size = 0, 726 * .data = 0, 727 * }; 728 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 729 * engines = malloc(query.size); 730 * query.data = (uintptr_t)engines; 731 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 732 * for (int i = 0; i < engines->num_engines; i++) { 733 * printf("Engine %d: %s\n", i, 734 * engines->engines[i].instance.engine_class == 735 * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": 736 * engines->engines[i].instance.engine_class == 737 * DRM_XE_ENGINE_CLASS_COPY ? "COPY": 738 * engines->engines[i].instance.engine_class == 739 * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": 740 * engines->engines[i].instance.engine_class == 741 * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": 742 * engines->engines[i].instance.engine_class == 743 * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": 744 * "UNKNOWN"); 745 * } 746 * free(engines); 747 */ 748 struct drm_xe_device_query { 749 /** @extensions: Pointer to the first extension struct, if any */ 750 __u64 extensions; 751 752 #define DRM_XE_DEVICE_QUERY_ENGINES 0 753 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 754 #define DRM_XE_DEVICE_QUERY_CONFIG 2 755 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 756 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 757 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 758 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 759 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 760 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 761 #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9 762 #define DRM_XE_DEVICE_QUERY_EU_STALL 10 763 /** @query: The type of data to query */ 764 __u32 query; 765 766 /** @size: Size of the queried data */ 767 __u32 size; 768 769 /** @data: Queried data is placed here */ 770 __u64 data; 771 772 /** @reserved: Reserved */ 773 __u64 reserved[2]; 774 }; 775 776 /** 777 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for 778 * gem creation 779 * 780 * The @flags can be: 781 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING - Modify the GEM object 782 * allocation strategy by deferring physical memory allocation 783 * until the object is either bound to a virtual memory region via 784 * VM_BIND or accessed by the CPU. As a result, no backing memory is 785 * reserved at the time of GEM object creation. 786 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is 787 * intended for scanout via the display engine. When set, kernel ensures 788 * that the allocation is placed in a memory region compatible with the 789 * display engine requirements. This may impose restrictions on tiling, 790 * alignment, and memory placement to guarantee proper display functionality. 791 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a 792 * possible placement, ensure that the corresponding VRAM allocation 793 * will always use the CPU accessible part of VRAM. This is important 794 * for small-bar systems (on full-bar systems this gets turned into a 795 * noop). 796 * Note1: System memory can be used as an extra placement if the kernel 797 * should spill the allocation to system memory, if space can't be made 798 * available in the CPU accessible part of VRAM (giving the same 799 * behaviour as the i915 interface, see 800 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). 801 * Note2: For clear-color CCS surfaces the kernel needs to read the 802 * clear-color value stored in the buffer, and on discrete platforms we 803 * need to use VRAM for display surfaces, therefore the kernel requires 804 * setting this flag for such objects, otherwise an error is thrown on 805 * small-bar systems. 806 * - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to 807 * hint that compression (CCS) should be disabled for the buffer being 808 * created. This can avoid unnecessary memory operations and CCS state 809 * management. 810 * On pre-Xe2 platforms, this flag is currently rejected as compression 811 * control is not supported via PAT index. On Xe2+ platforms, compression 812 * is controlled via PAT entries. If this flag is set, the driver will reject 813 * any VM bind that requests a PAT index enabling compression for this BO. 814 * Note: On dGPU platforms, there is currently no change in behavior with 815 * this flag, but future improvements may leverage it. The current benefit is 816 * primarily applicable to iGPU platforms. 817 * 818 * @cpu_caching supports the following values: 819 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back 820 * caching. On iGPU this can't be used for scanout surfaces. Currently 821 * not allowed for objects placed in VRAM. 822 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This 823 * is uncached. Scanout surfaces should likely use this. All objects 824 * that can be placed in VRAM must use this. 825 * 826 * This ioctl supports setting the following properties via the 827 * %DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY extension, which uses the 828 * generic @drm_xe_ext_set_property struct: 829 * 830 * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session 831 * this object will be used with. Valid values are listed in enum 832 * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so 833 * there is no need to explicitly set that. Objects used with session of type 834 * %DRM_XE_PXP_TYPE_HWDRM will be marked as invalid if a PXP invalidation 835 * event occurs after their creation. Attempting to flip an invalid object 836 * will cause a black frame to be displayed instead. Submissions with invalid 837 * objects mapped in the VM will be rejected. 838 */ 839 struct drm_xe_gem_create { 840 #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0 841 #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0 842 /** @extensions: Pointer to the first extension struct, if any */ 843 __u64 extensions; 844 845 /** 846 * @size: Size of the object to be created, must match region 847 * (system or vram) minimum alignment (&min_page_size). 848 */ 849 __u64 size; 850 851 /** 852 * @placement: A mask of memory instances of where BO can be placed. 853 * Each index in this mask refers directly to the struct 854 * drm_xe_query_mem_regions' instance, no assumptions should 855 * be made about order. The type of each region is described 856 * by struct drm_xe_query_mem_regions' mem_class. 857 */ 858 __u32 placement; 859 860 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) 861 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) 862 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) 863 #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3) 864 /** 865 * @flags: Flags, currently a mask of memory instances of where BO can 866 * be placed 867 */ 868 __u32 flags; 869 870 /** 871 * @vm_id: Attached VM, if any 872 * 873 * If a VM is specified, this BO must: 874 * 875 * 1. Only ever be bound to that VM. 876 * 2. Cannot be exported as a PRIME fd. 877 */ 878 __u32 vm_id; 879 880 /** 881 * @handle: Returned handle for the object. 882 * 883 * Object handles are nonzero. 884 */ 885 __u32 handle; 886 887 #define DRM_XE_GEM_CPU_CACHING_WB 1 888 #define DRM_XE_GEM_CPU_CACHING_WC 2 889 /** 890 * @cpu_caching: The CPU caching mode to select for this object. If 891 * mmaping the object the mode selected here will also be used. The 892 * exception is when mapping system memory (including data evicted 893 * to system) on discrete GPUs. The caching mode selected will 894 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency 895 * between GPU- and CPU is guaranteed. The caching mode of 896 * existing CPU-mappings will be updated transparently to 897 * user-space clients. 898 */ 899 __u16 cpu_caching; 900 /** @pad: MBZ */ 901 __u16 pad[3]; 902 903 /** @reserved: Reserved */ 904 __u64 reserved[2]; 905 }; 906 907 /** 908 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET 909 * 910 * The @flags can be: 911 * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset 912 * for use in mmap ioctl. Writing to the returned mmap address will generate a 913 * PCI memory barrier with low overhead (avoiding IOCTL call as well as writing 914 * to VRAM which would also add overhead), acting like an MI_MEM_FENCE 915 * instruction. 916 * 917 * Note: The mmap size can be at most 4K, due to HW limitations. As a result 918 * this interface is only supported on CPU architectures that support 4K page 919 * size. The mmap_offset ioctl will detect this and gracefully return an 920 * error, where userspace is expected to have a different fallback method for 921 * triggering a barrier. 922 * 923 * Roughly the usage would be as follows: 924 * 925 * .. code-block:: C 926 * 927 * struct drm_xe_gem_mmap_offset mmo = { 928 * .handle = 0, // must be set to 0 929 * .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, 930 * }; 931 * 932 * err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); 933 * map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); 934 * map[i] = 0xdeadbeaf; // issue barrier 935 */ 936 struct drm_xe_gem_mmap_offset { 937 /** @extensions: Pointer to the first extension struct, if any */ 938 __u64 extensions; 939 940 /** @handle: Handle for the object being mapped. */ 941 __u32 handle; 942 943 #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0) 944 /** @flags: Flags */ 945 __u32 flags; 946 947 /** @offset: The fake offset to use for subsequent mmap call */ 948 __u64 offset; 949 950 /** @reserved: Reserved */ 951 __u64 reserved[2]; 952 }; 953 954 /** 955 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE 956 * 957 * The @flags can be: 958 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address 959 * space of the VM to scratch page. A vm_bind would overwrite the scratch 960 * page mapping. This flag is mutually exclusive with the 961 * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and 962 * xe3 platform. 963 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts 964 * exec submissions to its exec_queues that don't have an upper time 965 * limit on the job execution time. But exec submissions to these 966 * don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, 967 * DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, 968 * together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. 969 * LR VMs can be created in recoverable page-fault mode using 970 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. 971 * If that flag is omitted, the UMD can not rely on the slightly 972 * different per-VM overcommit semantics that are enabled by 973 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may 974 * still enable recoverable pagefaults if supported by the device. 975 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also 976 * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on 977 * demand when accessed, and also allows per-VM overcommit of memory. 978 * The xe driver internally uses recoverable pagefaults to implement 979 * this. 980 * - %DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT - Requires also 981 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit 982 * but only during a &DRM_IOCTL_XE_VM_BIND operation with the 983 * %DRM_XE_VM_BIND_FLAG_IMMEDIATE flag set. This may be useful for 984 * user-space naively probing the amount of available memory. 985 */ 986 struct drm_xe_vm_create { 987 /** @extensions: Pointer to the first extension struct, if any */ 988 __u64 extensions; 989 990 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 991 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) 992 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) 993 #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3) 994 /** @flags: Flags */ 995 __u32 flags; 996 997 /** @vm_id: Returned VM ID */ 998 __u32 vm_id; 999 1000 /** @reserved: Reserved */ 1001 __u64 reserved[2]; 1002 }; 1003 1004 /** 1005 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY 1006 */ 1007 struct drm_xe_vm_destroy { 1008 /** @vm_id: VM ID */ 1009 __u32 vm_id; 1010 1011 /** @pad: MBZ */ 1012 __u32 pad; 1013 1014 /** @reserved: Reserved */ 1015 __u64 reserved[2]; 1016 }; 1017 1018 /** 1019 * struct drm_xe_vm_bind_op - run bind operations 1020 * 1021 * The @op can be: 1022 * - %DRM_XE_VM_BIND_OP_MAP 1023 * - %DRM_XE_VM_BIND_OP_UNMAP 1024 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR 1025 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL 1026 * - %DRM_XE_VM_BIND_OP_PREFETCH 1027 * 1028 * and the @flags can be: 1029 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only 1030 * to ensure write protection 1031 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the 1032 * MAP operation immediately rather than deferring the MAP to the page 1033 * fault handler. This is implied on a non-faulting VM as there is no 1034 * fault handler to defer to. 1035 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page 1036 * tables are setup with a special bit which indicates writes are 1037 * dropped and all reads return zero. In the future, the NULL flags 1038 * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 1039 * handle MBZ, and the BO offset MBZ. This flag is intended to 1040 * implement VK sparse bindings. 1041 * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP, 1042 * reject the binding if the encryption key is no longer valid. This 1043 * flag has no effect on BOs that are not marked as using PXP. 1044 * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is 1045 * set, no mappings are created rather the range is reserved for CPU address 1046 * mirroring which will be populated on GPU page faults or prefetches. Only 1047 * valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address 1048 * mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 1049 * handle MBZ, and the BO offset MBZ. 1050 * - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with 1051 * %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying 1052 * CPU address space range is unmapped (typically with munmap(2) or brk(2)). 1053 * The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values 1054 * that were present immediately after the &DRM_IOCTL_XE_VM_BIND. 1055 * The reset GPU virtual address range is the intersection of the range bound 1056 * using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range 1057 * unmapped. 1058 * This functionality is present to mimic the behaviour of CPU address space 1059 * madvises set using madvise(2), which are typically reset on unmap. 1060 * Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus 1061 * not invoke autoreset. Neither will stack variables going out of scope. 1062 * Therefore it's recommended to always explicitly reset the madvises when 1063 * freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call. 1064 * - %DRM_XE_VM_BIND_FLAG_DECOMPRESS - Request on-device decompression for a MAP. 1065 * When set on a MAP bind operation, request the driver schedule an on-device 1066 * in-place decompression (via the migrate/resolve path) for the GPU mapping 1067 * created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on 1068 * other ops is rejected. The bind's pat_index must select the device's 1069 * "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that 1070 * support Flat CCS and the required HW generation XE2+. 1071 * 1072 * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be: 1073 * - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in 1074 * the memory region advised by madvise. 1075 */ 1076 struct drm_xe_vm_bind_op { 1077 /** @extensions: Pointer to the first extension struct, if any */ 1078 __u64 extensions; 1079 1080 /** 1081 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP 1082 */ 1083 __u32 obj; 1084 1085 /** 1086 * @pat_index: The platform defined @pat_index to use for this mapping. 1087 * The index basically maps to some predefined memory attributes, 1088 * including things like caching, coherency, compression etc. The exact 1089 * meaning of the pat_index is platform specific and defined in the 1090 * Bspec and PRMs. When the KMD sets up the binding the index here is 1091 * encoded into the ppGTT PTE. 1092 * 1093 * For coherency the @pat_index needs to be at least 1way coherent when 1094 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD 1095 * will extract the coherency mode from the @pat_index and reject if 1096 * there is a mismatch (see note below for pre-MTL platforms). 1097 * 1098 * Note: On pre-MTL platforms there is only a caching mode and no 1099 * explicit coherency mode, but on such hardware there is always a 1100 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with 1101 * CPU caches even with the caching mode set as uncached. It's only the 1102 * display engine that is incoherent (on dgpu it must be in VRAM which 1103 * is always mapped as WC on the CPU). However to keep the uapi somewhat 1104 * consistent with newer platforms the KMD groups the different cache 1105 * levels into the following coherency buckets on all pre-MTL platforms: 1106 * 1107 * ppGTT UC -> COH_NONE 1108 * ppGTT WC -> COH_NONE 1109 * ppGTT WT -> COH_NONE 1110 * ppGTT WB -> COH_AT_LEAST_1WAY 1111 * 1112 * In practice UC/WC/WT should only ever used for scanout surfaces on 1113 * such platforms (or perhaps in general for dma-buf if shared with 1114 * another device) since it is only the display engine that is actually 1115 * incoherent. Everything else should typically use WB given that we 1116 * have a shared-LLC. On MTL+ this completely changes and the HW 1117 * defines the coherency mode as part of the @pat_index, where 1118 * incoherent GT access is possible. 1119 * 1120 * Note: For userptr and externally imported dma-buf the kernel expects 1121 * either 1WAY or 2WAY for the @pat_index. Starting from NVL-P, for 1122 * userptr, svm, madvise and externally imported dma-buf the kernel expects 1123 * either 2WAY or 1WAY and XA @pat_index. 1124 * 1125 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 1126 * on the @pat_index. For such mappings there is no actual memory being 1127 * mapped (the address in the PTE is invalid), so the various PAT memory 1128 * attributes likely do not apply. Simply leaving as zero is one 1129 * option (still a valid pat_index). Same applies to 1130 * DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping 1131 * there is no actual memory being mapped. 1132 */ 1133 __u16 pat_index; 1134 1135 /** @pad: MBZ */ 1136 __u16 pad; 1137 1138 union { 1139 /** 1140 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, 1141 * ignored for unbind 1142 */ 1143 __u64 obj_offset; 1144 1145 /** @userptr: user pointer to bind on */ 1146 __u64 userptr; 1147 1148 /** 1149 * @cpu_addr_mirror_offset: Offset from GPU @addr to create 1150 * CPU address mirror mappings. MBZ with current level of 1151 * support (e.g. 1 to 1 mapping between GPU and CPU mappings 1152 * only supported). 1153 */ 1154 __s64 cpu_addr_mirror_offset; 1155 }; 1156 1157 /** 1158 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL 1159 */ 1160 __u64 range; 1161 1162 /** @addr: Address to operate on, MBZ for UNMAP_ALL */ 1163 __u64 addr; 1164 1165 #define DRM_XE_VM_BIND_OP_MAP 0x0 1166 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 1167 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 1168 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 1169 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 1170 /** @op: Bind operation to perform */ 1171 __u32 op; 1172 1173 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) 1174 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) 1175 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) 1176 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) 1177 #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4) 1178 #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5) 1179 #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6) 1180 #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7) 1181 /** @flags: Bind flags */ 1182 __u32 flags; 1183 1184 #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1 1185 /** 1186 * @prefetch_mem_region_instance: Memory region to prefetch VMA to. 1187 * It is a region instance, not a mask. 1188 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. 1189 */ 1190 __u32 prefetch_mem_region_instance; 1191 1192 /** @pad2: MBZ */ 1193 __u32 pad2; 1194 1195 /** @reserved: Reserved */ 1196 __u64 reserved[3]; 1197 }; 1198 1199 /** 1200 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND 1201 * 1202 * Below is an example of a minimal use of @drm_xe_vm_bind to 1203 * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to 1204 * illustrate `userptr`. It can be synchronized by using the example 1205 * provided for @drm_xe_sync. 1206 * 1207 * .. code-block:: C 1208 * 1209 * data = aligned_alloc(ALIGNMENT, BO_SIZE); 1210 * struct drm_xe_vm_bind bind = { 1211 * .vm_id = vm, 1212 * .num_binds = 1, 1213 * .bind.obj = 0, 1214 * .bind.obj_offset = to_user_pointer(data), 1215 * .bind.range = BO_SIZE, 1216 * .bind.addr = BIND_ADDRESS, 1217 * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, 1218 * .bind.flags = 0, 1219 * .num_syncs = 1, 1220 * .syncs = &sync, 1221 * .exec_queue_id = 0, 1222 * }; 1223 * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); 1224 * 1225 */ 1226 struct drm_xe_vm_bind { 1227 /** @extensions: Pointer to the first extension struct, if any */ 1228 __u64 extensions; 1229 1230 /** @vm_id: The ID of the VM to bind to */ 1231 __u32 vm_id; 1232 1233 /** 1234 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND 1235 * and exec queue must have same vm_id. If zero, the default VM bind engine 1236 * is used. 1237 */ 1238 __u32 exec_queue_id; 1239 1240 /** @pad: MBZ */ 1241 __u32 pad; 1242 1243 /** @num_binds: number of binds in this IOCTL */ 1244 __u32 num_binds; 1245 1246 union { 1247 /** @bind: used if num_binds == 1 */ 1248 struct drm_xe_vm_bind_op bind; 1249 1250 /** 1251 * @vector_of_binds: userptr to array of struct 1252 * drm_xe_vm_bind_op if num_binds > 1 1253 */ 1254 __u64 vector_of_binds; 1255 }; 1256 1257 /** @pad2: MBZ */ 1258 __u32 pad2; 1259 1260 /** @num_syncs: amount of syncs to wait on */ 1261 __u32 num_syncs; 1262 1263 /** @syncs: pointer to struct drm_xe_sync array */ 1264 __u64 syncs; 1265 1266 /** @reserved: Reserved */ 1267 __u64 reserved[2]; 1268 }; 1269 1270 /** struct xe_vm_fault - Describes faults for %DRM_XE_VM_GET_PROPERTY_FAULTS */ 1271 struct xe_vm_fault { 1272 /** @address: Canonical address of the fault */ 1273 __u64 address; 1274 /** @address_precision: Precision of faulted address */ 1275 __u32 address_precision; 1276 /** @access_type: Type of address access that resulted in fault */ 1277 #define FAULT_ACCESS_TYPE_READ 0 1278 #define FAULT_ACCESS_TYPE_WRITE 1 1279 #define FAULT_ACCESS_TYPE_ATOMIC 2 1280 __u8 access_type; 1281 /** @fault_type: Type of fault reported */ 1282 #define FAULT_TYPE_NOT_PRESENT 0 1283 #define FAULT_TYPE_WRITE_ACCESS 1 1284 #define FAULT_TYPE_ATOMIC_ACCESS 2 1285 __u8 fault_type; 1286 /** @fault_level: fault level of the fault */ 1287 #define FAULT_LEVEL_PTE 0 1288 #define FAULT_LEVEL_PDE 1 1289 #define FAULT_LEVEL_PDP 2 1290 #define FAULT_LEVEL_PML4 3 1291 #define FAULT_LEVEL_PML5 4 1292 __u8 fault_level; 1293 /** @pad: MBZ */ 1294 __u8 pad; 1295 /** @reserved: MBZ */ 1296 __u64 reserved[4]; 1297 }; 1298 1299 /** 1300 * struct drm_xe_vm_get_property - Input of &DRM_IOCTL_XE_VM_GET_PROPERTY 1301 * 1302 * The user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*, 1303 * and sets the values in the vm_id and property members, respectively. This 1304 * determines both the VM to get the property of, as well as the property to 1305 * report. 1306 * 1307 * If size is set to 0, the driver fills it with the required size for the 1308 * requested property. The user is expected here to allocate memory for the 1309 * property structure and to provide a pointer to the allocated memory using the 1310 * data member. For some properties, this may be zero, in which case, the 1311 * value of the property will be saved to the value member and size will remain 1312 * zero on return. 1313 * 1314 * If size is not zero, then the IOCTL will attempt to copy the requested 1315 * property into the data member. 1316 * 1317 * The IOCTL will return -ENOENT if the VM could not be identified from the 1318 * provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as 1319 * providing an invalid size for the given property or if the property data 1320 * could not be copied to the memory allocated to the data member. 1321 * 1322 * The property member can be: 1323 * - %DRM_XE_VM_GET_PROPERTY_FAULTS 1324 */ 1325 struct drm_xe_vm_get_property { 1326 /** @extensions: Pointer to the first extension struct, if any */ 1327 __u64 extensions; 1328 1329 /** @vm_id: The ID of the VM to query the properties of */ 1330 __u32 vm_id; 1331 1332 #define DRM_XE_VM_GET_PROPERTY_FAULTS 0 1333 /** @property: property to get */ 1334 __u32 property; 1335 1336 /** @size: Size to allocate for @data */ 1337 __u32 size; 1338 1339 /** @pad: MBZ */ 1340 __u32 pad; 1341 1342 union { 1343 /** @data: Pointer to user-defined array of flexible size and type */ 1344 __u64 data; 1345 /** @value: Return value for scalar queries */ 1346 __u64 value; 1347 }; 1348 1349 /** @reserved: MBZ */ 1350 __u64 reserved[3]; 1351 }; 1352 1353 /** 1354 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 1355 * 1356 * This ioctl supports setting the following properties via the 1357 * %DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY extension, which uses the 1358 * generic @drm_xe_ext_set_property struct: 1359 * 1360 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority. 1361 * CAP_SYS_NICE is required to set a value above normal. 1362 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice 1363 * duration in microseconds. 1364 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session 1365 * this queue will be used with. Valid values are listed in enum 1366 * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so 1367 * there is no need to explicitly set that. When a queue of type 1368 * %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session 1369 * (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running. 1370 * The user is expected to query the PXP status via the query ioctl (see 1371 * %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before 1372 * attempting to create a queue with this property. When a queue is created 1373 * before PXP is ready, the ioctl will return -EBUSY if init is still in 1374 * progress or -EIO if init failed. 1375 * Given that going into a power-saving state kills PXP HWDRM sessions, 1376 * runtime PM will be blocked while queues of this type are alive. 1377 * All PXP queues will be killed if a PXP invalidation event occurs. 1378 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-queue group 1379 * or add secondary queues to a multi-queue group. 1380 * If the extension's 'value' field has %DRM_XE_MULTI_GROUP_CREATE flag set, 1381 * then a new multi-queue group is created with this queue as the primary queue 1382 * (Q0). Otherwise, the queue gets added to the multi-queue group whose primary 1383 * queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. 1384 * All the other non-relevant bits of extension's 'value' field while adding the 1385 * primary or the secondary queues of the group must be set to 0. 1386 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue 1387 * priority within the multi-queue group. Current valid priority values are 0–2 1388 * (default is 1), with higher values indicating higher priority. 1389 * - %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX - Set the queue to 1390 * enable render color cache keying on BTP+BTI instead of just BTI 1391 * (only valid for render queues). 1392 * 1393 * The example below shows how to use @drm_xe_exec_queue_create to create 1394 * a simple exec_queue (no parallel submission) of class 1395 * &DRM_XE_ENGINE_CLASS_RENDER. 1396 * 1397 * .. code-block:: C 1398 * 1399 * struct drm_xe_engine_class_instance instance = { 1400 * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, 1401 * }; 1402 * struct drm_xe_exec_queue_create exec_queue_create = { 1403 * .extensions = 0, 1404 * .vm_id = vm, 1405 * .num_bb_per_exec = 1, 1406 * .num_eng_per_bb = 1, 1407 * .instances = to_user_pointer(&instance), 1408 * }; 1409 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1410 * 1411 * Allow users to provide a hint to kernel for cases demanding low latency 1412 * profile. Please note it will have impact on power consumption. User can 1413 * indicate low latency hint with flag while creating exec queue as 1414 * mentioned below, 1415 * 1416 * struct drm_xe_exec_queue_create exec_queue_create = { 1417 * .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, 1418 * .extensions = 0, 1419 * .vm_id = vm, 1420 * .num_bb_per_exec = 1, 1421 * .num_eng_per_bb = 1, 1422 * .instances = to_user_pointer(&instance), 1423 * }; 1424 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1425 * 1426 */ 1427 struct drm_xe_exec_queue_create { 1428 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 1429 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 1430 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 1431 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2 1432 #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3 1433 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4 1434 #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63) 1435 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5 1436 #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6 1437 /** @extensions: Pointer to the first extension struct, if any */ 1438 __u64 extensions; 1439 1440 /** @width: submission width (number BB per exec) for this exec queue */ 1441 __u16 width; 1442 1443 /** @num_placements: number of valid placements for this exec queue */ 1444 __u16 num_placements; 1445 1446 /** @vm_id: VM to use for this exec queue */ 1447 __u32 vm_id; 1448 1449 #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0) 1450 /** @flags: flags to use for this exec queue */ 1451 __u32 flags; 1452 1453 /** @exec_queue_id: Returned exec queue ID */ 1454 __u32 exec_queue_id; 1455 1456 /** 1457 * @instances: user pointer to a 2-d array of struct 1458 * drm_xe_engine_class_instance 1459 * 1460 * length = width (i) * num_placements (j) 1461 * index = j + i * width 1462 */ 1463 __u64 instances; 1464 1465 /** @reserved: Reserved */ 1466 __u64 reserved[2]; 1467 }; 1468 1469 /** 1470 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 1471 */ 1472 struct drm_xe_exec_queue_destroy { 1473 /** @exec_queue_id: Exec queue ID */ 1474 __u32 exec_queue_id; 1475 1476 /** @pad: MBZ */ 1477 __u32 pad; 1478 1479 /** @reserved: Reserved */ 1480 __u64 reserved[2]; 1481 }; 1482 1483 /** 1484 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 1485 * 1486 * The @property can be: 1487 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 1488 */ 1489 struct drm_xe_exec_queue_get_property { 1490 /** @extensions: Pointer to the first extension struct, if any */ 1491 __u64 extensions; 1492 1493 /** @exec_queue_id: Exec queue ID */ 1494 __u32 exec_queue_id; 1495 1496 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 1497 /** @property: property to get */ 1498 __u32 property; 1499 1500 /** @value: property value */ 1501 __u64 value; 1502 1503 /** @reserved: Reserved */ 1504 __u64 reserved[2]; 1505 }; 1506 1507 /** 1508 * struct drm_xe_sync - sync object 1509 * 1510 * The @type can be: 1511 * - %DRM_XE_SYNC_TYPE_SYNCOBJ 1512 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 1513 * - %DRM_XE_SYNC_TYPE_USER_FENCE 1514 * 1515 * and the @flags can be: 1516 * - %DRM_XE_SYNC_FLAG_SIGNAL 1517 * 1518 * A minimal use of @drm_xe_sync looks like this: 1519 * 1520 * .. code-block:: C 1521 * 1522 * struct drm_xe_sync sync = { 1523 * .flags = DRM_XE_SYNC_FLAG_SIGNAL, 1524 * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, 1525 * }; 1526 * struct drm_syncobj_create syncobj_create = { 0 }; 1527 * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); 1528 * sync.handle = syncobj_create.handle; 1529 * ... 1530 * use of &sync in drm_xe_exec or drm_xe_vm_bind 1531 * ... 1532 * struct drm_syncobj_wait wait = { 1533 * .handles = &sync.handle, 1534 * .timeout_nsec = INT64_MAX, 1535 * .count_handles = 1, 1536 * .flags = 0, 1537 * .first_signaled = 0, 1538 * .pad = 0, 1539 * }; 1540 * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); 1541 */ 1542 struct drm_xe_sync { 1543 /** @extensions: Pointer to the first extension struct, if any */ 1544 __u64 extensions; 1545 1546 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 1547 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 1548 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 1549 /** @type: Type of the this sync object */ 1550 __u32 type; 1551 1552 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) 1553 /** @flags: Sync Flags */ 1554 __u32 flags; 1555 1556 union { 1557 /** @handle: Handle for the object */ 1558 __u32 handle; 1559 1560 /** 1561 * @addr: Address of user fence. When sync is passed in via exec 1562 * IOCTL this is a GPU address in the VM. When sync passed in via 1563 * VM bind IOCTL this is a user pointer. In either case, it is 1564 * the users responsibility that this address is present and 1565 * mapped when the user fence is signalled. Must be qword 1566 * aligned. 1567 */ 1568 __u64 addr; 1569 }; 1570 1571 /** 1572 * @timeline_value: Input for the timeline sync object. Needs to be 1573 * different than 0 when used with %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ. 1574 */ 1575 __u64 timeline_value; 1576 1577 /** @reserved: Reserved */ 1578 __u64 reserved[2]; 1579 }; 1580 1581 /** 1582 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC 1583 * 1584 * This is an example to use @drm_xe_exec for execution of the object 1585 * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue 1586 * (see example in @drm_xe_exec_queue_create). It can be synchronized 1587 * by using the example provided for @drm_xe_sync. 1588 * 1589 * .. code-block:: C 1590 * 1591 * struct drm_xe_exec exec = { 1592 * .exec_queue_id = exec_queue, 1593 * .syncs = &sync, 1594 * .num_syncs = 1, 1595 * .address = BIND_ADDRESS, 1596 * .num_batch_buffer = 1, 1597 * }; 1598 * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); 1599 * 1600 */ 1601 struct drm_xe_exec { 1602 /** @extensions: Pointer to the first extension struct, if any */ 1603 __u64 extensions; 1604 1605 /** @exec_queue_id: Exec queue ID for the batch buffer */ 1606 __u32 exec_queue_id; 1607 1608 #define DRM_XE_MAX_SYNCS 1024 1609 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 1610 __u32 num_syncs; 1611 1612 /** @syncs: Pointer to struct drm_xe_sync array. */ 1613 __u64 syncs; 1614 1615 /** 1616 * @address: address of batch buffer if num_batch_buffer == 1 or an 1617 * array of batch buffer addresses 1618 */ 1619 __u64 address; 1620 1621 /** 1622 * @num_batch_buffer: number of batch buffer in this exec, must match 1623 * the width of the engine 1624 */ 1625 __u16 num_batch_buffer; 1626 1627 /** @pad: MBZ */ 1628 __u16 pad[3]; 1629 1630 /** @reserved: Reserved */ 1631 __u64 reserved[2]; 1632 }; 1633 1634 /** 1635 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE 1636 * 1637 * Wait on user fence, XE will wake-up on every HW engine interrupt in the 1638 * instances list and check if user fence is complete:: 1639 * 1640 * (*addr & MASK) OP (VALUE & MASK) 1641 * 1642 * Returns to user on user fence completion or timeout. 1643 * 1644 * The @op can be: 1645 * - %DRM_XE_UFENCE_WAIT_OP_EQ 1646 * - %DRM_XE_UFENCE_WAIT_OP_NEQ 1647 * - %DRM_XE_UFENCE_WAIT_OP_GT 1648 * - %DRM_XE_UFENCE_WAIT_OP_GTE 1649 * - %DRM_XE_UFENCE_WAIT_OP_LT 1650 * - %DRM_XE_UFENCE_WAIT_OP_LTE 1651 * 1652 * and the @flags can be: 1653 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME 1654 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP 1655 * 1656 * The @mask values can be for example: 1657 * - 0xffu for u8 1658 * - 0xffffu for u16 1659 * - 0xffffffffu for u32 1660 * - 0xffffffffffffffffu for u64 1661 */ 1662 struct drm_xe_wait_user_fence { 1663 /** @extensions: Pointer to the first extension struct, if any */ 1664 __u64 extensions; 1665 1666 /** 1667 * @addr: user pointer address to wait on, must qword aligned 1668 */ 1669 __u64 addr; 1670 1671 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 1672 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 1673 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 1674 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 1675 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 1676 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 1677 /** @op: wait operation (type of comparison) */ 1678 __u16 op; 1679 1680 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) 1681 /** @flags: wait flags */ 1682 __u16 flags; 1683 1684 /** @pad: MBZ */ 1685 __u32 pad; 1686 1687 /** @value: compare value */ 1688 __u64 value; 1689 1690 /** @mask: comparison mask */ 1691 __u64 mask; 1692 1693 /** 1694 * @timeout: how long to wait before bailing, value in nanoseconds. 1695 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) 1696 * it contains timeout expressed in nanoseconds to wait (fence will 1697 * expire at now() + timeout). 1698 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait 1699 * will end at timeout (uses system MONOTONIC_CLOCK). 1700 * Passing negative timeout leads to neverending wait. 1701 * 1702 * On relative timeout this value is updated with timeout left 1703 * (for restarting the call in case of signal delivery). 1704 * On absolute timeout this value stays intact (restarted call still 1705 * expire at the same point of time). 1706 */ 1707 __s64 timeout; 1708 1709 /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ 1710 __u32 exec_queue_id; 1711 1712 /** @pad2: MBZ */ 1713 __u32 pad2; 1714 1715 /** @reserved: Reserved */ 1716 __u64 reserved[2]; 1717 }; 1718 1719 /** 1720 * enum drm_xe_observation_type - Observation stream types 1721 */ 1722 enum drm_xe_observation_type { 1723 /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */ 1724 DRM_XE_OBSERVATION_TYPE_OA, 1725 /** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */ 1726 DRM_XE_OBSERVATION_TYPE_EU_STALL, 1727 }; 1728 1729 /** 1730 * enum drm_xe_observation_op - Observation stream ops 1731 */ 1732 enum drm_xe_observation_op { 1733 /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */ 1734 DRM_XE_OBSERVATION_OP_STREAM_OPEN, 1735 1736 /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */ 1737 DRM_XE_OBSERVATION_OP_ADD_CONFIG, 1738 1739 /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */ 1740 DRM_XE_OBSERVATION_OP_REMOVE_CONFIG, 1741 }; 1742 1743 /** 1744 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION 1745 * 1746 * The observation layer enables multiplexing observation streams of 1747 * multiple types. The actual params for a particular stream operation are 1748 * supplied via the @param pointer (use __copy_from_user to get these 1749 * params). 1750 */ 1751 struct drm_xe_observation_param { 1752 /** @extensions: Pointer to the first extension struct, if any */ 1753 __u64 extensions; 1754 /** @observation_type: observation stream type, of enum @drm_xe_observation_type */ 1755 __u64 observation_type; 1756 /** @observation_op: observation stream op, of enum @drm_xe_observation_op */ 1757 __u64 observation_op; 1758 /** @param: Pointer to actual stream params */ 1759 __u64 param; 1760 }; 1761 1762 /** 1763 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's 1764 * 1765 * Information exchanged between userspace and kernel for observation fd 1766 * ioctl's is stream type specific 1767 */ 1768 enum drm_xe_observation_ioctls { 1769 /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */ 1770 DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0), 1771 1772 /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */ 1773 DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1), 1774 1775 /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */ 1776 DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2), 1777 1778 /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */ 1779 DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3), 1780 1781 /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */ 1782 DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4), 1783 }; 1784 1785 /** 1786 * enum drm_xe_oa_unit_type - OA unit types 1787 */ 1788 enum drm_xe_oa_unit_type { 1789 /** 1790 * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered 1791 * sub-types of OAG. For OAR/OAC, use OAG. 1792 */ 1793 DRM_XE_OA_UNIT_TYPE_OAG, 1794 1795 /** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */ 1796 DRM_XE_OA_UNIT_TYPE_OAM, 1797 1798 /** @DRM_XE_OA_UNIT_TYPE_OAM_SAG: OAM_SAG OA unit */ 1799 DRM_XE_OA_UNIT_TYPE_OAM_SAG, 1800 1801 /** @DRM_XE_OA_UNIT_TYPE_MERT: MERT OA unit */ 1802 DRM_XE_OA_UNIT_TYPE_MERT, 1803 }; 1804 1805 /** 1806 * struct drm_xe_oa_unit - describe OA unit 1807 */ 1808 struct drm_xe_oa_unit { 1809 /** @extensions: Pointer to the first extension struct, if any */ 1810 __u64 extensions; 1811 1812 /** @oa_unit_id: OA unit ID */ 1813 __u32 oa_unit_id; 1814 1815 /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */ 1816 __u32 oa_unit_type; 1817 1818 /** @capabilities: OA capabilities bit-mask */ 1819 __u64 capabilities; 1820 #define DRM_XE_OA_CAPS_BASE (1 << 0) 1821 #define DRM_XE_OA_CAPS_SYNCS (1 << 1) 1822 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2) 1823 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3) 1824 #define DRM_XE_OA_CAPS_OAM (1 << 4) 1825 #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5) 1826 1827 /** @oa_timestamp_freq: OA timestamp freq */ 1828 __u64 oa_timestamp_freq; 1829 1830 /** @gt_id: gt id for this OA unit */ 1831 __u16 gt_id; 1832 1833 /** @reserved1: MBZ */ 1834 __u16 reserved1[3]; 1835 1836 /** @reserved: MBZ */ 1837 __u64 reserved[3]; 1838 1839 /** @num_engines: number of engines in @eci array */ 1840 __u64 num_engines; 1841 1842 /** @eci: engines attached to this OA unit */ 1843 struct drm_xe_engine_class_instance eci[]; 1844 }; 1845 1846 /** 1847 * struct drm_xe_query_oa_units - describe OA units 1848 * 1849 * If a query is made with a struct drm_xe_device_query where .query 1850 * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct 1851 * drm_xe_query_oa_units in .data. 1852 * 1853 * OA unit properties for all OA units can be accessed using a code block 1854 * such as the one below: 1855 * 1856 * .. code-block:: C 1857 * 1858 * struct drm_xe_query_oa_units *qoa; 1859 * struct drm_xe_oa_unit *oau; 1860 * u8 *poau; 1861 * 1862 * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: 1863 * poau = (u8 *)&qoa->oa_units[0]; 1864 * for (int i = 0; i < qoa->num_oa_units; i++) { 1865 * oau = (struct drm_xe_oa_unit *)poau; 1866 * // Access 'struct drm_xe_oa_unit' fields here 1867 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); 1868 * } 1869 */ 1870 struct drm_xe_query_oa_units { 1871 /** @extensions: Pointer to the first extension struct, if any */ 1872 __u64 extensions; 1873 /** @num_oa_units: number of OA units returned in oau[] */ 1874 __u32 num_oa_units; 1875 /** @pad: MBZ */ 1876 __u32 pad; 1877 /** 1878 * @oa_units: struct @drm_xe_oa_unit array returned for this device. 1879 * Written below as a u64 array to avoid problems with nested flexible 1880 * arrays with some compilers 1881 */ 1882 __u64 oa_units[]; 1883 }; 1884 1885 /** 1886 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec 1887 * 52198/60942 1888 */ 1889 enum drm_xe_oa_format_type { 1890 /** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */ 1891 DRM_XE_OA_FMT_TYPE_OAG, 1892 /** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */ 1893 DRM_XE_OA_FMT_TYPE_OAR, 1894 /** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */ 1895 DRM_XE_OA_FMT_TYPE_OAM, 1896 /** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */ 1897 DRM_XE_OA_FMT_TYPE_OAC, 1898 /** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */ 1899 DRM_XE_OA_FMT_TYPE_OAM_MPEC, 1900 /** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */ 1901 DRM_XE_OA_FMT_TYPE_PEC, 1902 }; 1903 1904 /** 1905 * enum drm_xe_oa_property_id - OA stream property id's 1906 * 1907 * Stream params are specified as a chain of @drm_xe_ext_set_property 1908 * struct's, with @property values from enum @drm_xe_oa_property_id and 1909 * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY. 1910 * @param field in struct @drm_xe_observation_param points to the first 1911 * @drm_xe_ext_set_property struct. 1912 * 1913 * Exactly the same mechanism is also used for stream reconfiguration using the 1914 * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a 1915 * subset of properties below can be specified for stream reconfiguration. 1916 */ 1917 enum drm_xe_oa_property_id { 1918 #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 1919 /** 1920 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open 1921 * the OA stream, see @oa_unit_id in 'struct 1922 * drm_xe_query_oa_units'. Defaults to 0 if not provided. 1923 */ 1924 DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1, 1925 1926 /** 1927 * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw 1928 * OA unit reports or stream samples in a global buffer attached to an 1929 * OA unit. 1930 */ 1931 DRM_XE_OA_PROPERTY_SAMPLE_OA, 1932 1933 /** 1934 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA 1935 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG. 1936 */ 1937 DRM_XE_OA_PROPERTY_OA_METRIC_SET, 1938 1939 /** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */ 1940 DRM_XE_OA_PROPERTY_OA_FORMAT, 1941 /* 1942 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942, 1943 * in terms of the following quantities: a. enum @drm_xe_oa_format_type 1944 * b. Counter select c. Counter size and d. BC report. Also refer to the 1945 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. 1946 */ 1947 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0) 1948 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8) 1949 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16) 1950 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24) 1951 1952 /** 1953 * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit 1954 * sampling with sampling frequency proportional to 2^(period_exponent + 1) 1955 */ 1956 DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 1957 1958 /** 1959 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA 1960 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE). 1961 */ 1962 DRM_XE_OA_PROPERTY_OA_DISABLED, 1963 1964 /** 1965 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific 1966 * @exec_queue_id. OA queries can be executed on this exec queue. 1967 */ 1968 DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, 1969 1970 /** 1971 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to 1972 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0. 1973 */ 1974 DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 1975 1976 /** 1977 * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing 1978 * to be disabled for the stream exec queue. 1979 */ 1980 DRM_XE_OA_PROPERTY_NO_PREEMPT, 1981 1982 /** 1983 * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array 1984 * specified in @DRM_XE_OA_PROPERTY_SYNCS 1985 */ 1986 DRM_XE_OA_PROPERTY_NUM_SYNCS, 1987 1988 /** 1989 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array 1990 * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA 1991 * configuration will wait till input fences signal. Output fences 1992 * will signal after the new OA configuration takes effect. For 1993 * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar 1994 * to the VM bind case. 1995 */ 1996 DRM_XE_OA_PROPERTY_SYNCS, 1997 1998 /** 1999 * @DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE: Size of OA buffer to be 2000 * allocated by the driver in bytes. Supported sizes are powers of 2001 * 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA 2002 * buffer is allocated by default. 2003 */ 2004 DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, 2005 2006 /** 2007 * @DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS: Number of reports to wait 2008 * for before unblocking poll or read 2009 */ 2010 DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS, 2011 }; 2012 2013 /** 2014 * struct drm_xe_oa_config - OA metric configuration 2015 * 2016 * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A 2017 * particular config can be specified when opening an OA stream using 2018 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property. 2019 */ 2020 struct drm_xe_oa_config { 2021 /** @extensions: Pointer to the first extension struct, if any */ 2022 __u64 extensions; 2023 2024 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */ 2025 char uuid[36]; 2026 2027 /** @n_regs: Number of regs in @regs_ptr */ 2028 __u32 n_regs; 2029 2030 /** 2031 * @regs_ptr: Pointer to (register address, value) pairs for OA config 2032 * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs). 2033 */ 2034 __u64 regs_ptr; 2035 }; 2036 2037 /** 2038 * struct drm_xe_oa_stream_status - OA stream status returned from 2039 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can 2040 * call the ioctl to query stream status in response to EIO errno from 2041 * observation fd read(). 2042 */ 2043 struct drm_xe_oa_stream_status { 2044 /** @extensions: Pointer to the first extension struct, if any */ 2045 __u64 extensions; 2046 2047 /** @oa_status: OA stream status (see Bspec 46717/61226) */ 2048 __u64 oa_status; 2049 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3) 2050 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2) 2051 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1) 2052 #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0) 2053 2054 /** @reserved: reserved for future use */ 2055 __u64 reserved[3]; 2056 }; 2057 2058 /** 2059 * struct drm_xe_oa_stream_info - OA stream info returned from 2060 * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl 2061 */ 2062 struct drm_xe_oa_stream_info { 2063 /** @extensions: Pointer to the first extension struct, if any */ 2064 __u64 extensions; 2065 2066 /** @oa_buf_size: OA buffer size */ 2067 __u64 oa_buf_size; 2068 2069 /** @reserved: reserved for future use */ 2070 __u64 reserved[3]; 2071 }; 2072 2073 /** 2074 * enum drm_xe_pxp_session_type - Supported PXP session types. 2075 * 2076 * We currently only support HWDRM sessions, which are used for protected 2077 * content that ends up being displayed, but the HW supports multiple types, so 2078 * we might extend support in the future. 2079 */ 2080 enum drm_xe_pxp_session_type { 2081 /** @DRM_XE_PXP_TYPE_NONE: PXP not used */ 2082 DRM_XE_PXP_TYPE_NONE = 0, 2083 /** 2084 * @DRM_XE_PXP_TYPE_HWDRM: HWDRM sessions are used for content that ends 2085 * up on the display. 2086 */ 2087 DRM_XE_PXP_TYPE_HWDRM = 1, 2088 }; 2089 2090 /* ID of the protected content session managed by Xe when PXP is active */ 2091 #define DRM_XE_PXP_HWDRM_DEFAULT_SESSION 0xf 2092 2093 /** 2094 * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids. 2095 * 2096 * These properties are passed to the driver at open as a chain of 2097 * @drm_xe_ext_set_property structures with @property set to these 2098 * properties' enums and @value set to the corresponding values of these 2099 * properties. @drm_xe_user_extension base.name should be set to 2100 * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY. 2101 * 2102 * With the file descriptor obtained from open, user space must enable 2103 * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before 2104 * calling read(). EIO errno from read() indicates HW dropped data 2105 * due to full buffer. 2106 */ 2107 enum drm_xe_eu_stall_property_id { 2108 #define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0 2109 /** 2110 * @DRM_XE_EU_STALL_PROP_GT_ID: @gt_id of the GT on which 2111 * EU stall data will be captured. 2112 */ 2113 DRM_XE_EU_STALL_PROP_GT_ID = 1, 2114 2115 /** 2116 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate in 2117 * GPU cycles from @sampling_rates in struct @drm_xe_query_eu_stall 2118 */ 2119 DRM_XE_EU_STALL_PROP_SAMPLE_RATE, 2120 2121 /** 2122 * @DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS: Minimum number of 2123 * EU stall data reports to be present in the kernel buffer 2124 * before unblocking a blocked poll or read. 2125 */ 2126 DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS, 2127 }; 2128 2129 /** 2130 * struct drm_xe_query_eu_stall - Information about EU stall sampling. 2131 * 2132 * If a query is made with a struct @drm_xe_device_query where .query 2133 * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses 2134 * struct @drm_xe_query_eu_stall in .data. 2135 */ 2136 struct drm_xe_query_eu_stall { 2137 /** @extensions: Pointer to the first extension struct, if any */ 2138 __u64 extensions; 2139 2140 /** @capabilities: EU stall capabilities bit-mask */ 2141 __u64 capabilities; 2142 #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0) 2143 2144 /** @record_size: size of each EU stall data record */ 2145 __u64 record_size; 2146 2147 /** @per_xecore_buf_size: internal per XeCore buffer size */ 2148 __u64 per_xecore_buf_size; 2149 2150 /** @reserved: Reserved */ 2151 __u64 reserved[5]; 2152 2153 /** @num_sampling_rates: Number of sampling rates in @sampling_rates array */ 2154 __u64 num_sampling_rates; 2155 2156 /** 2157 * @sampling_rates: Flexible array of sampling rates 2158 * sorted in the fastest to slowest order. 2159 * Sampling rates are specified in GPU clock cycles. 2160 */ 2161 __u64 sampling_rates[]; 2162 }; 2163 2164 /** 2165 * struct drm_xe_madvise - Input of &DRM_IOCTL_XE_MADVISE 2166 * 2167 * This structure is used to set memory attributes for a virtual address range 2168 * in a VM. The type of attribute is specified by @type, and the corresponding 2169 * union member is used to provide additional parameters for @type. 2170 * 2171 * Supported attribute types: 2172 * - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location. 2173 * - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy. 2174 * - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index. 2175 * - DRM_XE_VMA_ATTR_PURGEABLE_STATE: Set purgeable state for BOs. 2176 * 2177 * Example: 2178 * 2179 * .. code-block:: C 2180 * 2181 * struct drm_xe_madvise madvise = { 2182 * .vm_id = vm_id, 2183 * .start = 0x100000, 2184 * .range = 0x2000, 2185 * .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, 2186 * .atomic_val = DRM_XE_ATOMIC_DEVICE, 2187 * }; 2188 * 2189 * ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise); 2190 * 2191 */ 2192 struct drm_xe_madvise { 2193 /** @extensions: Pointer to the first extension struct, if any */ 2194 __u64 extensions; 2195 2196 /** @start: start of the virtual address range */ 2197 __u64 start; 2198 2199 /** @range: size of the virtual address range */ 2200 __u64 range; 2201 2202 /** @vm_id: vm_id of the virtual range */ 2203 __u32 vm_id; 2204 2205 #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0 2206 #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1 2207 #define DRM_XE_MEM_RANGE_ATTR_PAT 2 2208 #define DRM_XE_VMA_ATTR_PURGEABLE_STATE 3 2209 /** @type: type of attribute */ 2210 __u32 type; 2211 2212 union { 2213 /** 2214 * @preferred_mem_loc: preferred memory location 2215 * 2216 * Used when @type == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 2217 * 2218 * Supported values for @preferred_mem_loc.devmem_fd: 2219 * - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc 2220 * - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc 2221 * 2222 * Supported values for @preferred_mem_loc.migration_policy: 2223 * - DRM_XE_MIGRATE_ALL_PAGES 2224 * - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 2225 */ 2226 struct { 2227 #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0 2228 #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1 2229 /** 2230 * @preferred_mem_loc.devmem_fd: 2231 * Device file-descriptor of the device where the 2232 * preferred memory is located, or one of the 2233 * above special values. Please also see 2234 * @preferred_mem_loc.region_instance below. 2235 */ 2236 __u32 devmem_fd; 2237 2238 #define DRM_XE_MIGRATE_ALL_PAGES 0 2239 #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1 2240 /** @preferred_mem_loc.migration_policy: Page migration policy */ 2241 __u16 migration_policy; 2242 2243 /** 2244 * @preferred_mem_loc.region_instance : Region instance. 2245 * MBZ if @devmem_fd <= &DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE. 2246 * Otherwise should point to the desired device 2247 * VRAM instance of the device indicated by 2248 * @preferred_mem_loc.devmem_fd. 2249 */ 2250 __u16 region_instance; 2251 2252 /** @preferred_mem_loc.reserved : Reserved */ 2253 __u64 reserved; 2254 } preferred_mem_loc; 2255 2256 /** 2257 * @atomic: Atomic access policy 2258 * 2259 * Used when @type == DRM_XE_MEM_RANGE_ATTR_ATOMIC. 2260 * 2261 * Supported values for @atomic.val: 2262 * - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. 2263 * Support both GPU and CPU atomic operations for system allocator. 2264 * Support GPU atomic operations for normal(bo) allocator. 2265 * - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations. 2266 * - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations. 2267 * - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. 2268 */ 2269 struct { 2270 #define DRM_XE_ATOMIC_UNDEFINED 0 2271 #define DRM_XE_ATOMIC_DEVICE 1 2272 #define DRM_XE_ATOMIC_GLOBAL 2 2273 #define DRM_XE_ATOMIC_CPU 3 2274 /** @atomic.val: value of atomic operation */ 2275 __u32 val; 2276 2277 /** @atomic.pad: MBZ */ 2278 __u32 pad; 2279 2280 /** @atomic.reserved: Reserved */ 2281 __u64 reserved; 2282 } atomic; 2283 2284 /** 2285 * @pat_index: Page attribute table index 2286 * 2287 * Used when @type == DRM_XE_MEM_RANGE_ATTR_PAT. 2288 */ 2289 struct { 2290 /** @pat_index.val: PAT index value */ 2291 __u32 val; 2292 2293 /** @pat_index.pad: MBZ */ 2294 __u32 pad; 2295 2296 /** @pat_index.reserved: Reserved */ 2297 __u64 reserved; 2298 } pat_index; 2299 2300 /** 2301 * @purge_state_val: Purgeable state configuration 2302 * 2303 * Used when @type == DRM_XE_VMA_ATTR_PURGEABLE_STATE. 2304 * 2305 * Configures the purgeable state of buffer objects in the specified 2306 * virtual address range. This allows applications to hint to the kernel 2307 * about bo's usage patterns for better memory management. 2308 * 2309 * By default all VMAs are in WILLNEED state. 2310 * 2311 * Supported values for @purge_state_val.val: 2312 * - DRM_XE_VMA_PURGEABLE_STATE_WILLNEED (0): Marks BO as needed. 2313 * If the BO was previously purged, the kernel sets the __u32 at 2314 * @retained_ptr to 0 (backing store lost) so the application knows 2315 * it must recreate the BO. 2316 * 2317 * - DRM_XE_VMA_PURGEABLE_STATE_DONTNEED (1): Marks BO as not currently 2318 * needed. Kernel may purge it under memory pressure to reclaim memory. 2319 * Only applies to non-shared BOs. The kernel sets the __u32 at 2320 * @retained_ptr to 1 if the backing store still exists (not yet purged), 2321 * or 0 if it was already purged. 2322 * 2323 * Important: Once marked as DONTNEED, touching the BO's memory 2324 * is undefined behavior. It may succeed temporarily (before the 2325 * kernel purges the backing store) but will suddenly fail once 2326 * the BO transitions to PURGED state. 2327 * 2328 * To transition back: use WILLNEED and check @retained_ptr — 2329 * if 0, backing store was lost and the BO must be recreated. 2330 * 2331 * The following operations are blocked in DONTNEED state to 2332 * prevent the BO from being re-mapped after madvise: 2333 * - New mmap() calls: Fail with -EBUSY 2334 * - VM_BIND operations: Fail with -EBUSY 2335 * - New dma-buf exports: Fail with -EBUSY 2336 * - CPU page faults (existing mmap): Fail with SIGBUS 2337 * - GPU page faults (fault-mode VMs): Fail with -EACCES 2338 */ 2339 struct { 2340 #define DRM_XE_VMA_PURGEABLE_STATE_WILLNEED 0 2341 #define DRM_XE_VMA_PURGEABLE_STATE_DONTNEED 1 2342 /** @purge_state_val.val: value for DRM_XE_VMA_ATTR_PURGEABLE_STATE */ 2343 __u32 val; 2344 2345 /** @purge_state_val.pad: MBZ */ 2346 __u32 pad; 2347 /** 2348 * @purge_state_val.retained_ptr: Pointer to a __u32 output 2349 * field for backing store status. 2350 * 2351 * Userspace must initialize the __u32 value at this address 2352 * to 0 before the ioctl. Kernel writes a __u32 after the 2353 * operation: 2354 * - 1 if backing store exists (not purged) 2355 * - 0 if backing store was purged 2356 * 2357 * If userspace fails to initialize to 0, ioctl returns -EINVAL. 2358 * This ensures a safe default (0 = assume purged) if kernel 2359 * cannot write the result. 2360 * 2361 * Similar to i915's drm_i915_gem_madvise.retained field. 2362 */ 2363 __u64 retained_ptr; 2364 } purge_state_val; 2365 }; 2366 2367 /** @reserved: Reserved */ 2368 __u64 reserved[2]; 2369 }; 2370 2371 /** 2372 * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS 2373 * 2374 * This structure is provided by userspace and filled by KMD in response to the 2375 * DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of 2376 * a memory ranges within a user specified address range in a VM. 2377 * 2378 * The structure includes information such as atomic access policy, 2379 * page attribute table (PAT) index, and preferred memory location. 2380 * Userspace allocates an array of these structures and passes a pointer to the 2381 * ioctl to retrieve attributes for each memory ranges 2382 * 2383 * @extensions: Pointer to the first extension struct, if any 2384 * @start: Start address of the memory range 2385 * @end: End address of the virtual memory range 2386 * 2387 */ 2388 struct drm_xe_mem_range_attr { 2389 /** @extensions: Pointer to the first extension struct, if any */ 2390 __u64 extensions; 2391 2392 /** @start: start of the memory range */ 2393 __u64 start; 2394 2395 /** @end: end of the memory range */ 2396 __u64 end; 2397 2398 /** @preferred_mem_loc: preferred memory location */ 2399 struct { 2400 /** @preferred_mem_loc.devmem_fd: fd for preferred loc */ 2401 __u32 devmem_fd; 2402 2403 /** @preferred_mem_loc.migration_policy: Page migration policy */ 2404 __u32 migration_policy; 2405 } preferred_mem_loc; 2406 2407 /** @atomic: Atomic access policy */ 2408 struct { 2409 /** @atomic.val: atomic attribute */ 2410 __u32 val; 2411 2412 /** @atomic.reserved: Reserved */ 2413 __u32 reserved; 2414 } atomic; 2415 2416 /** @pat_index: Page attribute table index */ 2417 struct { 2418 /** @pat_index.val: PAT index */ 2419 __u32 val; 2420 2421 /** @pat_index.reserved: Reserved */ 2422 __u32 reserved; 2423 } pat_index; 2424 2425 /** @reserved: Reserved */ 2426 __u64 reserved[2]; 2427 }; 2428 2429 /** 2430 * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES 2431 * 2432 * This structure is used to query memory attributes of memory regions 2433 * within a user specified address range in a VM. It provides detailed 2434 * information about each memory range, including atomic access policy, 2435 * page attribute table (PAT) index, and preferred memory location. 2436 * 2437 * Userspace first calls the ioctl with @num_mem_ranges = 0, 2438 * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL to retrieve 2439 * the number of memory regions and size of each memory range attribute. 2440 * Then, it allocates a buffer of that size and calls the ioctl again to fill 2441 * the buffer with memory range attributes. 2442 * 2443 * If second call fails with -ENOSPC, it means memory ranges changed between 2444 * first call and now, retry IOCTL again with @num_mem_ranges = 0, 2445 * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL followed by 2446 * Second ioctl call. 2447 * 2448 * Example: 2449 * 2450 * .. code-block:: C 2451 * 2452 * struct drm_xe_vm_query_mem_range_attr query = { 2453 * .vm_id = vm_id, 2454 * .start = 0x100000, 2455 * .range = 0x2000, 2456 * }; 2457 * 2458 * // First ioctl call to get num of mem regions and sizeof each attribute 2459 * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); 2460 * 2461 * // Allocate buffer for the memory region attributes 2462 * void *ptr = malloc(query.num_mem_ranges * query.sizeof_mem_range_attr); 2463 * void *ptr_start = ptr; 2464 * 2465 * query.vector_of_mem_attr = (uintptr_t)ptr; 2466 * 2467 * // Second ioctl call to actually fill the memory attributes 2468 * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); 2469 * 2470 * // Iterate over the returned memory region attributes 2471 * for (unsigned int i = 0; i < query.num_mem_ranges; ++i) { 2472 * struct drm_xe_mem_range_attr *attr = (struct drm_xe_mem_range_attr *)ptr; 2473 * 2474 * // Do something with attr 2475 * 2476 * // Move pointer by one entry 2477 * ptr += query.sizeof_mem_range_attr; 2478 * } 2479 * 2480 * free(ptr_start); 2481 */ 2482 struct drm_xe_vm_query_mem_range_attr { 2483 /** @extensions: Pointer to the first extension struct, if any */ 2484 __u64 extensions; 2485 2486 /** @vm_id: vm_id of the virtual range */ 2487 __u32 vm_id; 2488 2489 /** @num_mem_ranges: number of mem_ranges in range */ 2490 __u32 num_mem_ranges; 2491 2492 /** @start: start of the virtual address range */ 2493 __u64 start; 2494 2495 /** @range: size of the virtual address range */ 2496 __u64 range; 2497 2498 /** @sizeof_mem_range_attr: size of struct drm_xe_mem_range_attr */ 2499 __u64 sizeof_mem_range_attr; 2500 2501 /** @vector_of_mem_attr: userptr to array of struct drm_xe_mem_range_attr */ 2502 __u64 vector_of_mem_attr; 2503 2504 /** @reserved: Reserved */ 2505 __u64 reserved[2]; 2506 2507 }; 2508 2509 /** 2510 * struct drm_xe_exec_queue_set_property - exec queue set property 2511 * 2512 * Sets execution queue properties dynamically. 2513 * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 2514 * property can be dynamically set. 2515 */ 2516 struct drm_xe_exec_queue_set_property { 2517 /** @extensions: Pointer to the first extension struct, if any */ 2518 __u64 extensions; 2519 2520 /** @exec_queue_id: Exec queue ID */ 2521 __u32 exec_queue_id; 2522 2523 /** @property: property to set */ 2524 __u32 property; 2525 2526 /** @value: property value */ 2527 __u64 value; 2528 2529 /** @reserved: Reserved */ 2530 __u64 reserved[2]; 2531 }; 2532 2533 /** 2534 * DOC: Xe DRM RAS 2535 * 2536 * The enums and strings defined below map to the attributes of the DRM RAS Netlink Interface. 2537 * Refer to Documentation/netlink/specs/drm_ras.yaml for complete interface specification. 2538 * 2539 * Node Registration 2540 * ================= 2541 * 2542 * The driver registers DRM RAS nodes for each error severity level. 2543 * enum drm_xe_ras_error_severity defines the node-id, while DRM_XE_RAS_ERROR_SEVERITY_NAMES maps 2544 * node-id to node-name. 2545 * 2546 * Error Classification 2547 * ==================== 2548 * 2549 * Each node contains a list of error counters. Each error is identified by a error-id and 2550 * an error-name. enum drm_xe_ras_error_component defines the error-id, while 2551 * DRM_XE_RAS_ERROR_COMPONENT_NAMES maps error-id to error-name. 2552 * 2553 * User Interface 2554 * ============== 2555 * 2556 * To retrieve error values of a error counter, userspace applications should 2557 * follow the below steps: 2558 * 2559 * 1. Use command LIST_NODES to enumerate all available nodes 2560 * 2. Select node by node-id or node-name 2561 * 3. Use command GET_ERROR_COUNTERS to list errors of specific node 2562 * 4. Query specific error values using either error-id or error-name 2563 * 2564 * .. code-block:: C 2565 * 2566 * // Lookup tables for ID-to-name resolution 2567 * static const char *nodes[] = DRM_XE_RAS_ERROR_SEVERITY_NAMES; 2568 * static const char *errors[] = DRM_XE_RAS_ERROR_COMPONENT_NAMES; 2569 * 2570 */ 2571 2572 /** 2573 * enum drm_xe_ras_error_severity - DRM RAS error severity. 2574 */ 2575 enum drm_xe_ras_error_severity { 2576 /** @DRM_XE_RAS_ERR_SEV_CORRECTABLE: Correctable Error */ 2577 DRM_XE_RAS_ERR_SEV_CORRECTABLE = 0, 2578 /** @DRM_XE_RAS_ERR_SEV_UNCORRECTABLE: Uncorrectable Error */ 2579 DRM_XE_RAS_ERR_SEV_UNCORRECTABLE, 2580 /** @DRM_XE_RAS_ERR_SEV_MAX: Max severity */ 2581 DRM_XE_RAS_ERR_SEV_MAX /* non-ABI */ 2582 }; 2583 2584 /** 2585 * enum drm_xe_ras_error_component - DRM RAS error component. 2586 */ 2587 enum drm_xe_ras_error_component { 2588 /** @DRM_XE_RAS_ERR_COMP_CORE_COMPUTE: Core Compute Error */ 2589 DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1, 2590 /** @DRM_XE_RAS_ERR_COMP_SOC_INTERNAL: SoC Internal Error */ 2591 DRM_XE_RAS_ERR_COMP_SOC_INTERNAL, 2592 /** @DRM_XE_RAS_ERR_COMP_MAX: Max Error */ 2593 DRM_XE_RAS_ERR_COMP_MAX /* non-ABI */ 2594 }; 2595 2596 /* 2597 * Error severity to name mapping. 2598 */ 2599 #define DRM_XE_RAS_ERROR_SEVERITY_NAMES { \ 2600 [DRM_XE_RAS_ERR_SEV_CORRECTABLE] = "correctable-errors", \ 2601 [DRM_XE_RAS_ERR_SEV_UNCORRECTABLE] = "uncorrectable-errors", \ 2602 } 2603 2604 /* 2605 * Error component to name mapping. 2606 */ 2607 #define DRM_XE_RAS_ERROR_COMPONENT_NAMES { \ 2608 [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute", \ 2609 [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal" \ 2610 } 2611 2612 #if defined(__cplusplus) 2613 } 2614 #endif 2615 2616 #endif /* _UAPI_XE_DRM_H_ */ 2617