Home
last modified time | relevance | path

Searched refs:DRAM (Results 1 – 25 of 102) sorted by relevance

12345

/linux/Documentation/hid/ !
H A Damd-sfh-hid.rst60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On
72 2. Data transfer via DRAM.
77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
79 shall allocate minimum of 32 bytes DRAM space.
103 | | | Allocate the DRAM | Enable |
136 | | | Read the DRAM data for| | |
/linux/drivers/memory/tegra/ !
H A DKconfig22 Tegra20 chips. The EMC controls the external DRAM on the board.
34 Tegra30 chips. The EMC controls the external DRAM on the board.
46 Tegra124 chips. The EMC controls the external DRAM on the board.
60 Tegra210 chips. The EMC controls the external DRAM on the board.
/linux/Documentation/driver-api/cxl/platform/acpi/ !
H A Dhmat.rst24 Entry : 0080 <- DRAM LTC
31 Entry : 1200 <- DRAM BW
/linux/Documentation/edac/ !
H A Dmemory_repair.rst30 in a DRAM device.
32 For example, a CXL memory device with DRAM components that support PPR
33 features implements maintenance operations. DRAM components support those
95 media or DRAM trace event to userspace, and userspace tools (e.g.
138 device with DRAM components that support memory sparing features may
146 For example, a CXL device with DRAM components that support PPR features
H A Dscrub.rst19 Increasing DRAM size and cost have made memory subsystem reliability an
47 1. Background (patrol) scrubbing while the DRAM is otherwise idle.
131 allowing DRAM to internally read, correct single-bit errors, and write back
132 corrected data bits to the DRAM array while providing transparency to error
242 | reporting | Exception |media/DRAM |media/DRAM | notify and|
/linux/sound/isa/gus/ !
H A Dgus_dram.c27 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke()
61 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
/linux/drivers/memory/samsung/ !
H A DKconfig19 Frequency Scaling in DMC and DRAM. It also supports changing timings
20 of DRAM running with different frequency. The timings are calculated
/linux/Documentation/devicetree/bindings/firmware/ !
H A Dnvidia,tegra210-bpmp.txt6 (suspend to ram), and also offloading DRAM memory clock scaling on
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
/linux/Documentation/driver-api/ !
H A Dedac.rst18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
112 communication lanes. It uses vertically stacked memory chips (DRAM dies)
202 of 4096-bits of DRAM data bus.
204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
205 channel is interfacing 2GB of DRAM (represented as rank).
/linux/Documentation/admin-guide/perf/ !
H A Dmeson-ddr-pmu.rst7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
9 DRAM. The channel can count up to 3 AXI port simultaneously. It can be helpful
/linux/arch/arm/ !
H A DKconfig-nommu14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
/linux/Documentation/ABI/testing/ !
H A Dsysfs-edac-memory-repair15 replacing it with a spare row in a DRAM device. For example, a
16 CXL memory device with DRAM components that support PPR features may
17 implement PPR maintenance operations. DRAM components may support
142 related error records and trace events, for eg. CXL DRAM
160 in trace events, such as CXL DRAM and CXL general media
/linux/arch/arm/configs/ !
H A Ddram_0x00000000.config1 # Help: DRAM base at 0x00000000
H A Ddram_0xd0000000.config1 # Help: DRAM base at 0xd0000000
H A Ddram_0xc0000000.config1 # Help: DRAM base at 0xc0000000
/linux/Documentation/hwmon/ !
H A Dasus_wmi_sensors.rst37 * DRAM Voltage,
48 * DRAM Voltage,
/linux/Documentation/driver-api/cxl/allocation/ !
H A Dpage-allocator.rst21 Generally, we expect to see local DRAM and CXL memory on separate NUMA nodes,
23 for a compute node to have no local DRAM, and for CXL memory to be the
/linux/Documentation/translations/zh_CN/mm/damon/ !
H A Dindex.rst19 - *准确度* （监测输出对DRAM级别的内存管理足够有用；但可能不适合CPU Cache级别），
/linux/drivers/powercap/ !
H A DKconfig34 fine grained control. These domains include processor package, DRAM
49 fine grained control. These domains include processor package, DRAM
/linux/arch/arm64/boot/dts/broadcom/stingray/ !
H A Dstingray-board-base.dtsi22 &memory { /* Default DRAM banks */
/linux/arch/arm/mach-lpc32xx/ !
H A Dsuspend.S51 @ This guarantees a small windows where DRAM isn't busy
/linux/drivers/ras/amd/atl/ !
H A DKconfig21 Enable this option if using DRAM ECC on Zen-based systems
/linux/Documentation/arch/arm/sa1100/ !
H A Dlart.rst6 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
/linux/Documentation/mm/damon/ !
H A Dindex.rst11 - *accurate* (for DRAM level memory management),
/linux/drivers/edac/ !
H A DKconfig104 Support for error detection and correction of DRAM ECC errors on
113 Correctable errors into DRAM.
123 which trigger the DRAM ECC Read and Write respectively.
186 E3-1200 based DRAM controllers.
362 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
527 SoCs with ARM DMC-520 DRAM controller.

12345