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Searched refs:DPU_IRQ_IDX (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_0_sc8280xp.h41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
209 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
215 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
227 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
H A Ddpu_9_2_x1e80100.h32 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
206 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
212 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
218 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
H A Ddpu_8_4_sa8775p.h41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
209 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
215 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
227 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
H A Ddpu_9_0_sm8550.h33 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
206 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
212 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
218 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
H A Ddpu_9_1_sar2130p.h33 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
206 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
212 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
218 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
H A Ddpu_8_1_sm8450.h42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
210 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
216 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
228 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_interrupts.h39 #define DPU_IRQ_IDX(reg_idx, offset) (1 + reg_idx * 32 + offset) macro