Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 6 of 6) sorted by relevance
228 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()666 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()723 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
159 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
232 #define DPLL_VGA_MODE_DIS (1 << 28) macro
528 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
1258 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; in vlv_display_power_well_init()
8346 DPLL_VGA_MODE_DIS | in i830_enable_pipe()8376 dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()8426 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()