Home
last modified time | relevance | path

Searched refs:DPLL (Results 1 – 23 of 23) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
52 - DPLL mode setting - defining any one or more of the following overrides
54 - ti,low-power-stop : DPLL supports low power stop mode, gating output
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
56 - ti,lock : DPLL locks in programmed rate
[all …]
H A Dapll.txt9 a subtype of a DPLL [2], although a simplified one at that.
/linux/drivers/dpll/
H A DKconfig3 # Generic DPLL drivers configuration
6 menu "DPLL device support"
8 config DPLL config
12 bool "DPLL reference count tracking"
13 depends on DEBUG_KERNEL && STACKTRACE_SUPPORT && DPLL
16 Enable reference count tracking for DPLL devices and pins.
/linux/drivers/dpll/zl3073x/
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
/linux/Documentation/driver-api/
H A Ddpll.rst7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
160 pick a highest priority valid signal and use it to control the DPLL
239 source. However, some DPLL (Digital Phase-Locked Loop) devices may offer
242 message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices.
279 from both inputs are used to synchronize the DPLL device. The higher frequency
280 signal is utilized for the loop bandwidth of the DPLL, while the lower frequency
281 signal is used to syntonize the output signal of the DPLL device. This feature
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A DKconfig204 tristate "Mellanox 5th generation network adapters (ConnectX series) DPLL support"
206 select DPLL
208 DPLL support in Mellanox Technologies ConnectX NICs.
/linux/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
/linux/Documentation/networking/devlink/
H A Dzl3073x.rst21 - Set the clock ID that is used by the driver for registering DPLL devices
H A Ddevlink-params.rst155 - Clock ID used by the device for registering DPLL devices and pins.
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dvo.c461 dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0, in intel_dvo_init_dev()
468 intel_de_write(display, DPLL(display, pipe), dpll[pipe]); in intel_dvo_init_dev()
H A Dintel_display_power_well.c1256 u32 val = intel_de_read(display, DPLL(display, pipe)); in vlv_display_power_well_init()
1262 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_init()
1412 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
H A Dintel_dpio_phy.c1184 dpll_reg = DPLL(display, 0); in vlv_wait_port_ready()
1188 dpll_reg = DPLL(display, 0); in vlv_wait_port_ready()
H A Dintel_display.c8375 intel_de_write(display, DPLL(display, pipe), in i830_enable_pipe()
8377 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8380 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8388 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8392 intel_de_write(display, DPLL(display, pipe), dpll); in i830_enable_pipe()
8393 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8426 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
8427 intel_de_posting_read(display, DPLL(display, pipe)); in i830_disable_pipe()
/linux/Documentation/arch/arm/omap/
H A Ddss.rst32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst937 There are adapters with DPLL, where pins are connected to the DPLL instead of
940 To see input signal on those PTP pins, you need to configure DPLL properly.
941 Output signal is only visible on DPLL and to send it to the board SMA/U.FL pins,
942 DPLL output pins have to be manually configured.
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h256 #define DPLL 0x034A macro
/linux/drivers/ptp/
H A DKconfig220 select DPLL
/linux/drivers/net/ethernet/intel/
H A DKconfig306 select DPLL
/linux/arch/arm/boot/dts/rockchip/
H A Drk3036.dtsi239 * Fix the emac parent clock is DPLL instead of APLL.
/linux/Documentation/networking/device_drivers/hamradio/
H A Dz8530drv.rst308 present at all (BayCom). It feeds back the output of the DPLL
/linux/
H A DMAINTAINERS7760 DPLL SUBSYSTEM