xref: /linux/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h (revision 4a57e0913e8c7fff407e97909f4ae48caa84d612) !
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28 
29 #include <asm/byteorder.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33 
34 #include "atomfirmware.h"
35 
36 //<DMUB_TYPES>==================================================================
37 /* Basic type definitions. */
38 
39 #ifdef __forceinline
40 #undef __forceinline
41 #endif
42 #define __forceinline inline
43 
44 /**
45  * Flag from driver to indicate that ABM should be disabled gradually
46  * by slowly reversing all backlight programming and pixel compensation.
47  */
48 #define SET_ABM_PIPE_GRADUALLY_DISABLE           0
49 
50 /**
51  * Flag from driver to indicate that ABM should be disabled immediately
52  * and undo all backlight programming and pixel compensation.
53  */
54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE         255
55 
56 /**
57  * Flag from driver to indicate that ABM should be disabled immediately
58  * and keep the current backlight programming and pixel compensation.
59  */
60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
61 
62 /**
63  * Flag from driver to set the current ABM pipe index or ABM operating level.
64  */
65 #define SET_ABM_PIPE_NORMAL                      1
66 
67 /**
68  * Number of ambient light levels in ABM algorithm.
69  */
70 #define NUM_AMBI_LEVEL                  5
71 
72 /**
73  * Number of operating/aggression levels in ABM algorithm.
74  */
75 #define NUM_AGGR_LEVEL                  4
76 
77 /**
78  * Number of segments in the gamma curve.
79  */
80 #define NUM_POWER_FN_SEGS               8
81 
82 /**
83  * Number of segments in the backlight curve.
84  */
85 #define NUM_BL_CURVE_SEGS               16
86 
87 /**
88  * Maximum number of segments in ABM ACE curve.
89  */
90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS         64
91 
92 /**
93  * Maximum number of bins in ABM histogram.
94  */
95 #define ABM_MAX_NUM_OF_HG_BINS              64
96 
97 /* Maximum number of SubVP streams */
98 #define DMUB_MAX_SUBVP_STREAMS 2
99 
100 /* Define max FPO streams as 4 for now. Current implementation today
101  * only supports 1, but could be more in the future. Reduce array
102  * size to ensure the command size remains less than 64 bytes if
103  * adding new fields.
104  */
105 #define DMUB_MAX_FPO_STREAMS 4
106 
107 /* Define to ensure that the "common" members always appear in the same
108  * order in different structs for back compat purposes
109  */
110 #define COMMON_STREAM_STATIC_SUB_STATE \
111     struct dmub_fams2_cmd_legacy_stream_static_state legacy; \
112     struct dmub_fams2_cmd_subvp_stream_static_state subvp; \
113     struct dmub_fams2_cmd_drr_stream_static_state drr;
114 
115 /* Maximum number of streams on any ASIC. */
116 #define DMUB_MAX_STREAMS 6
117 
118 /* Maximum number of planes on any ASIC. */
119 #define DMUB_MAX_PLANES 6
120 
121 /* Maximum number of phantom planes on any ASIC */
122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)
123 
124 /* Trace buffer offset for entry */
125 #define TRACE_BUFFER_ENTRY_OFFSET 16
126 
127 /**
128  * Maximum number of dirty rects supported by FW.
129  */
130 #define DMUB_MAX_DIRTY_RECTS 3
131 
132 /**
133  *
134  * PSR control version legacy
135  */
136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
137 /**
138  * PSR control version with multi edp support
139  */
140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
141 
142 /**
143  *
144  * dirty rect cmd version legacy
145  */
146 #define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0
147 /**
148  * dirty rect cmd version with multi edp support
149  */
150 #define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1
151 /**
152  * dirty rect cmd version with external monitor support
153  */
154 #define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2
155 
156 /**
157  *
158  * Cursor update cmd version legacy
159  */
160 #define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0
161 /**
162  * Cursor update cmd version with multi edp support
163  */
164 #define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1
165 /**
166  * Cursor update cmd version with external monitor support
167  */
168 #define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2
169 
170 /**
171  * ABM control version legacy
172  */
173 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
174 
175 /**
176  * ABM control version with multi edp support
177  */
178 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
179 
180 /**
181  * Physical framebuffer address location, 64-bit.
182  */
183 #ifndef PHYSICAL_ADDRESS_LOC
184 #define PHYSICAL_ADDRESS_LOC union large_integer
185 #endif
186 
187 /**
188  * OS/FW agnostic memcpy
189  */
190 #ifndef dmub_memcpy
191 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
192 #endif
193 
194 /**
195  * OS/FW agnostic memset
196  */
197 #ifndef dmub_memset
198 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
199 #endif
200 
201 /**
202  * OS/FW agnostic memcmp
203  */
204 #ifndef dmub_memcmp
205 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes))
206 #endif
207 
208 /**
209  * OS/FW agnostic udelay
210  */
211 #ifndef dmub_udelay
212 #define dmub_udelay(microseconds) udelay(microseconds)
213 #endif
214 
215 #pragma pack(push, 1)
216 #define ABM_NUM_OF_ACE_SEGMENTS         5
217 
218 /**
219  * Debug FW state offset
220  */
221 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300
222 
223 union abm_flags {
224 	struct {
225 		/**
226 		 * @abm_enabled: Indicates if ABM is enabled.
227 		 */
228 		unsigned int abm_enabled : 1;
229 
230 		/**
231 		 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
232 		 */
233 		unsigned int disable_abm_requested : 1;
234 
235 		/**
236 		 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
237 		 */
238 		unsigned int disable_abm_immediately : 1;
239 
240 		/**
241 		 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
242 		 * to be disabled immediately and keep gain.
243 		 */
244 		unsigned int disable_abm_immediate_keep_gain : 1;
245 
246 		/**
247 		 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
248 		 */
249 		unsigned int fractional_pwm : 1;
250 
251 		/**
252 		 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
253 		 * of user backlight level.
254 		 */
255 		unsigned int abm_gradual_bl_change : 1;
256 
257 		/**
258 		 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady
259 		 */
260 		unsigned int abm_new_frame : 1;
261 
262 		/**
263 		 * @vb_scaling_enabled: Indicates variBright Scaling Enable
264 		 */
265 		unsigned int vb_scaling_enabled : 1;
266 	} bitfields;
267 
268 	unsigned int u32All;
269 };
270 
271 struct abm_save_restore {
272 	/**
273 	 * @flags: Misc. ABM flags.
274 	 */
275 	union abm_flags flags;
276 
277 	/**
278 	 * @pause: true:  pause ABM and get state
279 	 *         false: unpause ABM after setting state
280 	 */
281 	uint32_t pause;
282 
283 	/**
284 	 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
285 	 */
286 	uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
287 
288 	/**
289 	 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
290 	 */
291 	uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
292 
293 	/**
294 	 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
295 	 */
296 	uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
297 
298 
299 	/**
300 	 * @knee_threshold: Current x-position of ACE knee (u0.16).
301 	 */
302 	uint32_t knee_threshold;
303 	/**
304 	 * @current_gain: Current backlight reduction (u16.16).
305 	 */
306 	uint32_t current_gain;
307 	/**
308 	 * @curr_bl_level: Current actual backlight level converging to target backlight level.
309 	 */
310 	uint16_t curr_bl_level;
311 
312 	/**
313 	 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
314 	 */
315 	uint16_t curr_user_bl_level;
316 
317 };
318 
319 /**
320  * union dmub_addr - DMUB physical/virtual 64-bit address.
321  */
322 union dmub_addr {
323 	struct {
324 		uint32_t low_part; /**< Lower 32 bits */
325 		uint32_t high_part; /**< Upper 32 bits */
326 	} u; /*<< Low/high bit access */
327 	uint64_t quad_part; /*<< 64 bit address */
328 };
329 
330 /* Flattened structure containing SOC BB parameters stored in the VBIOS
331  * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters.
332  * This also prevents alighment issues when new parameters are added to the SoC BB.
333  * The following parameters should be added since these values can't be obtained elsewhere:
334  * -dml2_soc_power_management_parameters
335  * -dml2_soc_vmin_clock_limits
336  */
337 struct dmub_soc_bb_params {
338 	uint32_t dram_clk_change_blackout_ns;
339 	uint32_t dram_clk_change_read_only_ns;
340 	uint32_t dram_clk_change_write_only_ns;
341 	uint32_t fclk_change_blackout_ns;
342 	uint32_t g7_ppt_blackout_ns;
343 	uint32_t stutter_enter_plus_exit_latency_ns;
344 	uint32_t stutter_exit_latency_ns;
345 	uint32_t z8_stutter_enter_plus_exit_latency_ns;
346 	uint32_t z8_stutter_exit_latency_ns;
347 	uint32_t z8_min_idle_time_ns;
348 	uint32_t type_b_dram_clk_change_blackout_ns;
349 	uint32_t type_b_ppt_blackout_ns;
350 	uint32_t vmin_limit_dispclk_khz;
351 	uint32_t vmin_limit_dcfclk_khz;
352 	uint32_t g7_temperature_read_blackout_ns;
353 };
354 #pragma pack(pop)
355 
356 /**
357  * Dirty rect definition.
358  */
359 struct dmub_rect {
360 	/**
361 	 * Dirty rect x offset.
362 	 */
363 	uint32_t x;
364 
365 	/**
366 	 * Dirty rect y offset.
367 	 */
368 	uint32_t y;
369 
370 	/**
371 	 * Dirty rect width.
372 	 */
373 	uint32_t width;
374 
375 	/**
376 	 * Dirty rect height.
377 	 */
378 	uint32_t height;
379 };
380 
381 /**
382  * Flags that can be set by driver to change some PSR behaviour.
383  */
384 union dmub_psr_debug_flags {
385 	/**
386 	 * Debug flags.
387 	 */
388 	struct {
389 		/**
390 		 * Enable visual confirm in FW.
391 		 */
392 		uint32_t visual_confirm : 1;
393 
394 		/**
395 		 * Force all selective updates to bw full frame updates.
396 		 */
397 		uint32_t force_full_frame_update : 1;
398 
399 		/**
400 		 * Use HW Lock Mgr object to do HW locking in FW.
401 		 */
402 		uint32_t use_hw_lock_mgr : 1;
403 
404 		/**
405 		 * Use TPS3 signal when restore main link.
406 		 */
407 		uint32_t force_wakeup_by_tps3 : 1;
408 
409 		/**
410 		 * Back to back flip, therefore cannot power down PHY
411 		 */
412 		uint32_t back_to_back_flip : 1;
413 
414 		/**
415 		 * Enable visual confirm for IPS
416 		 */
417 		uint32_t enable_ips_visual_confirm : 1;
418 	} bitfields;
419 
420 	/**
421 	 * Union for debug flags.
422 	 */
423 	uint32_t u32All;
424 };
425 
426 /**
427  * Flags that can be set by driver to change some Replay behaviour.
428  */
429 union replay_debug_flags {
430 	struct {
431 		/**
432 		 * 0x1 (bit 0)
433 		 * Enable visual confirm in FW.
434 		 */
435 		uint32_t visual_confirm : 1;
436 
437 		/**
438 		 * 0x2 (bit 1)
439 		 * @skip_crc: Set if need to skip CRC.
440 		 */
441 		uint32_t skip_crc : 1;
442 
443 		/**
444 		 * 0x4 (bit 2)
445 		 * @force_link_power_on: Force disable ALPM control
446 		 */
447 		uint32_t force_link_power_on : 1;
448 
449 		/**
450 		 * 0x8 (bit 3)
451 		 * @force_phy_power_on: Force phy power on
452 		 */
453 		uint32_t force_phy_power_on : 1;
454 
455 		/**
456 		 * 0x10 (bit 4)
457 		 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
458 		 */
459 		uint32_t timing_resync_disabled : 1;
460 
461 		/**
462 		 * 0x20 (bit 5)
463 		 * @skip_crtc_disabled: CRTC disable skipped
464 		 */
465 		uint32_t skip_crtc_disabled : 1;
466 
467 		/**
468 		 * 0x40 (bit 6)
469 		 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
470 		 */
471 		uint32_t force_defer_one_frame_update : 1;
472 
473 		/**
474 		 * 0x80 (bit 7)
475 		 * @disable_delay_alpm_on: Force disable delay alpm on
476 		 */
477 		uint32_t disable_delay_alpm_on : 1;
478 
479 		/**
480 		 * 0x100 (bit 8)
481 		 * @disable_desync_error_check: Force disable desync error check
482 		 */
483 		uint32_t disable_desync_error_check : 1;
484 
485 		/**
486 		 * 0x200 (bit 9)
487 		 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
488 		 */
489 		uint32_t force_self_update_when_abm_non_steady : 1;
490 
491 		/**
492 		 * 0x400 (bit 10)
493 		 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS
494 		 * If we enter IPS2, the Visual confirm bar will change to yellow
495 		 */
496 		uint32_t enable_ips_visual_confirm : 1;
497 
498 		/**
499 		 * 0x800 (bit 11)
500 		 * @enable_ips_residency_profiling: Enable IPS residency profiling
501 		 */
502 		uint32_t enable_ips_residency_profiling : 1;
503 
504 		/**
505 		 * 0x1000 (bit 12)
506 		 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check
507 		 */
508 		uint32_t enable_coasting_vtotal_check : 1;
509 		/**
510 		 * 0x2000 (bit 13)
511 		 * @enable_visual_confirm_debug: Enable Visual Confirm Debug
512 		 */
513 		uint32_t enable_visual_confirm_debug : 1;
514 
515 		/**
516 		 * 0x4000 (bit 14)
517 		 * @debug_log_enabled: Debug Log Enabled
518 		 */
519 		uint32_t debug_log_enabled : 1;
520 
521 		/**
522 		 * 0x8000 (bit 15)
523 		 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm
524 		 */
525 		uint32_t enable_sub_feature_visual_confirm : 1;
526 
527 		uint32_t reserved : 16;
528 	} bitfields;
529 
530 	uint32_t u32All;
531 };
532 
533 /**
534  * Flags record error state.
535  */
536 union replay_visual_confirm_error_state_flags {
537 	struct {
538 		/**
539 		 * 0x1 (bit 0) - Desync Error flag.
540 		 */
541 		uint32_t desync_error : 1;
542 
543 		/**
544 		 * 0x2 (bit 1) - State Transition Error flag.
545 		 */
546 		uint32_t state_transition_error : 1;
547 
548 		/**
549 		 * 0x4 (bit 2) - Crc Error flag
550 		 */
551 		uint32_t crc_error : 1;
552 
553 		/**
554 		 * 0x8 (bit 3) - Reserved
555 		 */
556 		uint32_t reserved_3 : 1;
557 
558 		/**
559 		 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
560 		 * Added new debug flag to control DPCD.
561 		 */
562 		uint32_t incorrect_vtotal_in_static_screen : 1;
563 
564 		/**
565 		 * 0x20 (bit 5) - No doubled Refresh Rate.
566 		 */
567 		uint32_t no_double_rr : 1;
568 
569 		/**
570 		 * Reserved bit 6-7
571 		 */
572 		uint32_t reserved_6_7 : 2;
573 
574 		/**
575 		 * Reserved bit 9-31
576 		 */
577 		uint32_t reserved_9_31 : 24;
578 	} bitfields;
579 
580 	uint32_t u32All;
581 };
582 
583 union replay_hw_flags {
584 	struct {
585 		/**
586 		 * @allow_alpm_fw_standby_mode: To indicate whether the
587 		 * ALPM FW standby mode is allowed
588 		 */
589 		uint32_t allow_alpm_fw_standby_mode : 1;
590 
591 		/*
592 		 * @dsc_enable_status: DSC enable status in driver
593 		 */
594 		uint32_t dsc_enable_status : 1;
595 
596 		/**
597 		 * @fec_enable_status: receive fec enable/disable status from driver
598 		 */
599 		uint32_t fec_enable_status : 1;
600 
601 		/*
602 		 * @smu_optimizations_en: SMU power optimization.
603 		 * Only when active display is Replay capable and display enters Replay.
604 		 * Trigger interrupt to SMU to powerup/down.
605 		 */
606 		uint32_t smu_optimizations_en : 1;
607 
608 		/**
609 		 * @phy_power_state: Indicates current phy power state
610 		 */
611 		uint32_t phy_power_state : 1;
612 
613 		/**
614 		 * @link_power_state: Indicates current link power state
615 		 */
616 		uint32_t link_power_state : 1;
617 		/**
618 		 * Use TPS3 signal when restore main link.
619 		 */
620 		uint32_t force_wakeup_by_tps3 : 1;
621 		/**
622 		 * @is_alpm_initialized: Indicates whether ALPM is initialized
623 		 */
624 		uint32_t is_alpm_initialized : 1;
625 
626 		/**
627 		 * @alpm_mode: Indicates ALPM mode selected
628 		 */
629 		uint32_t alpm_mode : 2;
630 	} bitfields;
631 
632 	uint32_t u32All;
633 };
634 
635 /**
636  * Flags that can be set by driver to change some Panel Replay behaviour.
637  */
638 union pr_debug_flags {
639 	struct {
640 		/**
641 		 * 0x1 (bit 0)
642 		 * Enable visual confirm in FW.
643 		 */
644 		uint32_t visual_confirm : 1;
645 
646 		/**
647 		 * 0x2 (bit 1)
648 		 * @skip_crc: Set if need to skip CRC.
649 		 */
650 		uint32_t skip_crc : 1;
651 
652 		/**
653 		 * 0x4 (bit 2)
654 		 * @force_link_power_on: Force disable ALPM control
655 		 */
656 		uint32_t force_link_power_on : 1;
657 
658 		/**
659 		 * 0x8 (bit 3)
660 		 * @force_phy_power_on: Force phy power on
661 		 */
662 		uint32_t force_phy_power_on : 1;
663 
664 		/**
665 		 * 0x10 (bit 4)
666 		 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection
667 		 */
668 		uint32_t visual_confirm_rate_control : 1;
669 
670 		/**
671 		 * 0x20 (bit 5)
672 		 * @force_full_frame_update: Force all selective updates to be full frame updates
673 		 */
674 		uint32_t force_full_frame_update : 1;
675 
676 		/**
677 		 * 0x40 (bit 6)
678 		 * @force_dpg_on: Force DPG on
679 		 */
680 		uint32_t force_dpg_on : 1;
681 
682 		/**
683 		 * 0x80 (bit 7)
684 		 * @force_hubp_on: Force Hubp on
685 		 */
686 		uint32_t force_hubp_on : 1;
687 
688 		uint32_t reserved : 24;
689 	} bitfields;
690 
691 	uint32_t u32All;
692 };
693 
694 union pr_hw_flags {
695 	struct {
696 		/**
697 		 * @allow_alpm_fw_standby_mode: To indicate whether the
698 		 * ALPM FW standby mode is allowed
699 		 */
700 		uint32_t allow_alpm_fw_standby_mode : 1;
701 
702 		/*
703 		 * @dsc_enable_status: DSC enable status in driver
704 		 */
705 		uint32_t dsc_enable_status : 1;
706 
707 		/**
708 		 * @fec_enable_status: receive fec enable/disable status from driver
709 		 */
710 		uint32_t fec_enable_status : 1;
711 		/*
712 		 * @smu_optimizations_en: SMU power optimization.
713 		 * Only when active display is Replay capable and display enters Replay.
714 		 * Trigger interrupt to SMU to powerup/down.
715 		 */
716 		uint32_t smu_optimizations_en : 1;
717 		/**
718 		 * @link_power_state: Indicates current link power state
719 		 */
720 		uint32_t link_power_state : 1;
721 		/**
722 		 * Use TPS3 signal when restore main link.
723 		 */
724 		uint32_t force_wakeup_by_tps3 : 1;
725 		/**
726 		 * @is_alpm_initialized: Indicates whether ALPM is initialized
727 		 */
728 		uint32_t is_alpm_initialized : 1;
729 		/**
730 		 * @alpm_mode: Indicates ALPM mode selected
731 		 */
732 		uint32_t alpm_mode : 2;
733 		uint32_t reserved : 23;
734 	} bitfields;
735 
736 	uint32_t u32All;
737 };
738 
739 /**
740  * Definition of Panel Replay ML Activity Options
741  */
742 enum pr_ml_activity_option {
743 	OPTION_DEFAULT	= 0x00, // VESA Option Default (1C)
744 	OPTION_1A		= 0x01, // VESA Option 1A
745 	OPTION_1B		= 0x02, // VESA Option 1B
746 	OPTION_1C		= 0x03, // VESA Option 1C
747 };
748 
749 union fw_assisted_mclk_switch_version {
750 	struct {
751 		uint8_t minor : 5;
752 		uint8_t major : 3;
753 	};
754 	uint8_t ver;
755 };
756 
757 /**
758  * DMUB feature capabilities.
759  * After DMUB init, driver will query FW capabilities prior to enabling certain features.
760  */
761 struct dmub_feature_caps {
762 	/**
763 	 * Max PSR version supported by FW.
764 	 */
765 	uint8_t psr;
766 	uint8_t fw_assisted_mclk_switch_ver;
767 	uint8_t reserved[4];
768 	uint8_t subvp_psr_support;
769 	uint8_t gecc_enable;
770 	uint8_t replay_supported;
771 	uint8_t replay_reserved[3];
772 	uint8_t abm_aux_backlight_support;
773 	uint8_t lsdma_support_in_dmu;
774 };
775 
776 struct dmub_visual_confirm_color {
777 	/**
778 	 * Maximum 10 bits color value
779 	 */
780 	uint16_t color_r_cr;
781 	uint16_t color_g_y;
782 	uint16_t color_b_cb;
783 	uint16_t panel_inst;
784 };
785 
786 /**
787  * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data.
788  */
789 struct dmub_cursor_offload_pipe_data_dcn30_v1 {
790 	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
791 	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
792 	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;
793 	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;
794 	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;
795 	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;
796 	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;
797 	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;
798 	uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;
799 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;
800 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;
801 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;
802 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;
803 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;
804 	uint32_t reserved0[4];
805 	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;
806 	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;
807 	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;
808 	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;
809 	uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;
810 	uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;
811 	uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16;
812 	uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16;
813 	uint32_t reserved1[5];
814 	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;
815 	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;
816 	uint32_t reserved2[3];
817 };
818 
819 /**
820  * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data.
821  */
822 struct dmub_cursor_offload_pipe_data_dcn401_v1 {
823 	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
824 	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
825 	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;
826 	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;
827 	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;
828 	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;
829 	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;
830 	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;
831 	uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;
832 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;
833 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;
834 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;
835 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;
836 	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;
837 	uint32_t reserved0[4];
838 	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;
839 	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;
840 	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;
841 	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;
842 	uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;
843 	uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;
844 	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16;
845 	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16;
846 	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16;
847 	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16;
848 	uint32_t reserved1[4];
849 	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;
850 	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;
851 	uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1;
852 	uint32_t reserved2[3];
853 };
854 
855 /**
856  * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload.
857  */
858 struct dmub_cursor_offload_pipe_data_v1 {
859 	union {
860 		struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */
861 		struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */
862 		uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */
863 	};
864 };
865 
866 /**
867  * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data.
868  */
869 struct dmub_cursor_offload_payload_data_v1 {
870 	uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */
871 	uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */
872 	uint32_t pipe_mask; /**< Mask of pipes to update. */
873 	uint32_t reserved; /**< Reserved for future use. */
874 	struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */
875 };
876 
877 /**
878  * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload.
879  */
880 struct dmub_cursor_offload_stream_v1 {
881 	struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */
882 	uint32_t write_idx; /**< The index of the last written payload. */
883 };
884 
885 /**
886  * struct dmub_cursor_offload_v1 - Cursor offload feature state.
887  */
888 struct dmub_cursor_offload_v1 {
889 	struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */
890 };
891 
892 //==============================================================================
893 //</DMUB_TYPES>=================================================================
894 //==============================================================================
895 //< DMUB_META>==================================================================
896 //==============================================================================
897 #pragma pack(push, 1)
898 
899 /* Magic value for identifying dmub_fw_meta_info */
900 #define DMUB_FW_META_MAGIC 0x444D5542
901 
902 /* Offset from the end of the file to the dmub_fw_meta_info */
903 #define DMUB_FW_META_OFFSET 0x24
904 
905 /**
906  * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
907  */
908 union dmub_fw_meta_feature_bits {
909 	struct {
910 		uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */
911 		uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */
912 		uint32_t inbox0_lock_support: 1; /**< 1 supports inbox0 lock mechanism */
913 		uint32_t reserved : 29;
914 	} bits; /**< status bits */
915 	uint32_t all; /**< 32-bit access to status bits */
916 };
917 
918 /**
919  * struct dmub_fw_meta_info - metadata associated with fw binary
920  *
921  * NOTE: This should be considered a stable API. Fields should
922  *       not be repurposed or reordered. New fields should be
923  *       added instead to extend the structure.
924  *
925  * @magic_value: magic value identifying DMUB firmware meta info
926  * @fw_region_size: size of the firmware state region
927  * @trace_buffer_size: size of the tracebuffer region
928  * @fw_version: the firmware version information
929  * @dal_fw: 1 if the firmware is DAL
930  * @shared_state_size: size of the shared state region in bytes
931  * @shared_state_features: number of shared state features
932  */
933 struct dmub_fw_meta_info {
934 	uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
935 	uint32_t fw_region_size; /**< size of the firmware state region */
936 	uint32_t trace_buffer_size; /**< size of the tracebuffer region */
937 	uint32_t fw_version; /**< the firmware version information */
938 	uint8_t dal_fw; /**< 1 if the firmware is DAL */
939 	uint8_t reserved[3]; /**< padding bits */
940 	uint32_t shared_state_size; /**< size of the shared state region in bytes */
941 	uint16_t shared_state_features; /**< number of shared state features */
942 	uint16_t reserved2; /**< padding bytes */
943 	union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */
944 };
945 
946 /**
947  * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
948  */
949 union dmub_fw_meta {
950 	struct dmub_fw_meta_info info; /**< metadata info */
951 	uint8_t reserved[64]; /**< padding bits */
952 };
953 
954 #pragma pack(pop)
955 
956 //==============================================================================
957 //< DMUB Trace Buffer>================================================================
958 //==============================================================================
959 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
960 /**
961  * dmub_trace_code_t - firmware trace code, 32-bits
962  */
963 typedef uint32_t dmub_trace_code_t;
964 
965 /**
966  * struct dmcub_trace_buf_entry - Firmware trace entry
967  */
968 struct dmcub_trace_buf_entry {
969 	dmub_trace_code_t trace_code; /**< trace code for the event */
970 	uint32_t tick_count; /**< the tick count at time of trace */
971 	uint32_t param0; /**< trace defined parameter 0 */
972 	uint32_t param1; /**< trace defined parameter 1 */
973 };
974 #endif
975 
976 //==============================================================================
977 //< DMUB_STATUS>================================================================
978 //==============================================================================
979 
980 /**
981  * DMCUB scratch registers can be used to determine firmware status.
982  * Current scratch register usage is as follows:
983  *
984  * SCRATCH0: FW Boot Status register
985  * SCRATCH5: LVTMA Status Register
986  * SCRATCH15: FW Boot Options register
987  */
988 
989 /**
990  * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
991  */
992 union dmub_fw_boot_status {
993 	struct {
994 		uint32_t dal_fw : 1; /**< 1 if DAL FW */
995 		uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
996 		uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
997 		uint32_t restore_required : 1; /**< 1 if driver should call restore */
998 		uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
999 		uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
1000 		uint32_t detection_required: 1; /**<  if detection need to be triggered by driver */
1001 		uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
1002 		uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
1003 	} bits; /**< status bits */
1004 	uint32_t all; /**< 32-bit access to status bits */
1005 };
1006 
1007 /**
1008  * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
1009  */
1010 enum dmub_fw_boot_status_bit {
1011 	DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
1012 	DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
1013 	DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
1014 	DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
1015 	DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
1016 	DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
1017 	DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
1018 	DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
1019 	DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
1020 };
1021 
1022 /* Register bit definition for SCRATCH5 */
1023 union dmub_lvtma_status {
1024 	struct {
1025 		uint32_t psp_ok : 1;
1026 		uint32_t edp_on : 1;
1027 		uint32_t reserved : 30;
1028 	} bits;
1029 	uint32_t all;
1030 };
1031 
1032 enum dmub_lvtma_status_bit {
1033 	DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
1034 	DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
1035 };
1036 
1037 enum dmub_ips_disable_type {
1038 	DMUB_IPS_ENABLE = 0,
1039 	DMUB_IPS_DISABLE_ALL = 1,
1040 	DMUB_IPS_DISABLE_IPS1 = 2,
1041 	DMUB_IPS_DISABLE_IPS2 = 3,
1042 	DMUB_IPS_DISABLE_IPS2_Z10 = 4,
1043 	DMUB_IPS_DISABLE_DYNAMIC = 5,
1044 	DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,
1045 	DMUB_IPS_DISABLE_Z8_RETENTION = 7,
1046 };
1047 
1048 enum dmub_ips_rcg_disable_type {
1049 	DMUB_IPS_RCG_ENABLE = 0,
1050 	DMUB_IPS0_RCG_DISABLE = 1,
1051 	DMUB_IPS1_RCG_DISABLE = 2,
1052 	DMUB_IPS_RCG_DISABLE = 3
1053 };
1054 
1055 enum dmub_ips_in_vpb_disable_type {
1056 	DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour
1057 	DMUB_IPS_VPB_DISABLE_ALL = 1,
1058 	DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2,
1059 	DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG
1060 };
1061 
1062 #define DMUB_IPS1_ALLOW_MASK 0x00000001
1063 #define DMUB_IPS2_ALLOW_MASK 0x00000002
1064 #define DMUB_IPS1_COMMIT_MASK 0x00000004
1065 #define DMUB_IPS2_COMMIT_MASK 0x00000008
1066 
1067 enum dmub_ips_comand_type {
1068 	/**
1069 	 * Start/stop IPS residency measurements for a given IPS mode
1070 	 */
1071 	DMUB_CMD__IPS_RESIDENCY_CNTL = 0,
1072 	/**
1073 	 * Query IPS residency information for a given IPS mode
1074 	 */
1075 	DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1,
1076 };
1077 
1078 /**
1079  * enum dmub_cursor_offload_comand_type - Cursor offload subcommands.
1080  */
1081 enum dmub_cursor_offload_comand_type {
1082 	/**
1083 	 * Initializes the cursor offload feature.
1084 	 */
1085 	DMUB_CMD__CURSOR_OFFLOAD_INIT = 0,
1086 	/**
1087 	 * Enables cursor offloading for a stream and updates the timing parameters.
1088 	 */
1089 	DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1,
1090 	/**
1091 	 * Disables cursor offloading for a given stream.
1092 	 */
1093 	DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2,
1094 	/**
1095 	 * Programs the latest data for a given stream.
1096 	 */
1097 	DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3,
1098 };
1099 
1100 /**
1101  * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
1102  */
1103 union dmub_fw_boot_options {
1104 	struct {
1105 		uint32_t pemu_env : 1; /**< 1 if PEMU */
1106 		uint32_t fpga_env : 1; /**< 1 if FPGA */
1107 		uint32_t optimized_init : 1; /**< 1 if optimized init */
1108 		uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
1109 		uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
1110 		uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
1111 		uint32_t z10_disable: 1; /**< 1 to disable z10 */
1112 		uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
1113 		uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
1114 		uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
1115 		uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
1116 		/**< 1 if all root clock gating is enabled and low power memory is enabled*/
1117 		uint32_t power_optimization: 1;
1118 		uint32_t diag_env: 1; /* 1 if diagnostic environment */
1119 		uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
1120 		uint32_t usb4_cm_version: 1; /**< 1 CM support */
1121 		uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
1122 		uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/
1123 		uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
1124 		uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
1125 		uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
1126 		uint32_t ips_disable: 3; /* options to disable ips support*/
1127 		uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
1128 		uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
1129 		uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */
1130 		uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */
1131 		uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */
1132 		uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/
1133 		uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/
1134 		uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/
1135 		uint32_t reserved : 1; /**< reserved */
1136 	} bits; /**< boot bits */
1137 	uint32_t all; /**< 32-bit access to bits */
1138 };
1139 
1140 enum dmub_fw_boot_options_bit {
1141 	DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
1142 	DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
1143 	DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
1144 };
1145 
1146 //==============================================================================
1147 //< DMUB_SHARED_STATE>==========================================================
1148 //==============================================================================
1149 
1150 /**
1151  * Shared firmware state between driver and firmware for lockless communication
1152  * in situations where the inbox/outbox may be unavailable.
1153  *
1154  * Each structure *must* be at most 256-bytes in size. The layout allocation is
1155  * described below:
1156  *
1157  * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...
1158  */
1159 
1160 /**
1161  * enum dmub_shared_state_feature_id - List of shared state features.
1162  */
1163 enum dmub_shared_state_feature_id {
1164 	DMUB_SHARED_SHARE_FEATURE__INVALID = 0,
1165 	DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,
1166 	DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,
1167 	DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3,
1168 	DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4,
1169 	DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */
1170 };
1171 
1172 /**
1173  * struct dmub_shared_state_ips_fw - Firmware signals for IPS.
1174  */
1175 union dmub_shared_state_ips_fw_signals {
1176 	struct {
1177 		uint32_t ips1_commit : 1;  /**< 1 if in IPS1 or IPS0 RCG */
1178 		uint32_t ips2_commit : 1; /**< 1 if in IPS2 */
1179 		uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */
1180 		uint32_t detection_required : 1; /**< 1 if detection is required */
1181 		uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */
1182 		uint32_t reserved_bits : 27; /**< Reversed */
1183 	} bits;
1184 	uint32_t all;
1185 };
1186 
1187 /**
1188  * struct dmub_shared_state_ips_signals - Firmware signals for IPS.
1189  */
1190 union dmub_shared_state_ips_driver_signals {
1191 	struct {
1192 		uint32_t allow_pg : 1; /**< 1 if PG is allowed */
1193 		uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */
1194 		uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */
1195 		uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */
1196 		uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */
1197 		uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */
1198 		uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */
1199 		uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */
1200 		uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */
1201 		uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */
1202 		uint32_t reserved_bits : 22; /**< Reversed bits */
1203 	} bits;
1204 	uint32_t all;
1205 };
1206 
1207 /**
1208  * IPS FW Version
1209  */
1210 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1
1211 
1212 struct dmub_shared_state_debug_setup {
1213 	union {
1214 		struct {
1215 			uint32_t exclude_points[62];
1216 		} profile_mode;
1217 	};
1218 };
1219 
1220 /**
1221  * struct dmub_shared_state_ips_fw - Firmware state for IPS.
1222  */
1223 struct dmub_shared_state_ips_fw {
1224 	union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */
1225 	uint32_t rcg_entry_count; /**< Entry counter for RCG */
1226 	uint32_t rcg_exit_count; /**< Exit counter for RCG */
1227 	uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
1228 	uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
1229 	uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
1230 	uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
1231 	uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */
1232 	uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */
1233 	uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */
1234 }; /* 248-bytes, fixed */
1235 
1236 /**
1237  * IPS Driver Version
1238  */
1239 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1
1240 
1241 /**
1242  * struct dmub_shared_state_ips_driver - Driver state for IPS.
1243  */
1244 struct dmub_shared_state_ips_driver {
1245 	union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */
1246 	uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */
1247 }; /* 248-bytes, fixed */
1248 
1249 /**
1250  * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload.
1251  */
1252 struct dmub_shared_state_cursor_offload_stream_v1 {
1253 	uint32_t last_write_idx; /**< Last write index */
1254 	uint8_t reserved[28]; /**< Reserved bytes. */
1255 }; /* 32-bytes, fixed */
1256 
1257 /**
1258  * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload.
1259  */
1260 struct dmub_shared_state_cursor_offload_v1 {
1261 	struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */
1262 	uint8_t reserved[56]; /**< reserved for future use */
1263 }; /* 248-bytes, fixed */
1264 
1265 /**
1266  * enum dmub_shared_state_feature_common - Generic payload.
1267  */
1268 struct dmub_shared_state_feature_common {
1269 	uint32_t padding[62];
1270 }; /* 248-bytes, fixed */
1271 
1272 /**
1273  * enum dmub_shared_state_feature_header - Feature description.
1274  */
1275 struct dmub_shared_state_feature_header {
1276 	uint16_t id; /**< Feature ID */
1277 	uint16_t version; /**< Feature version */
1278 	uint32_t reserved; /**< Reserved bytes. */
1279 }; /* 8 bytes, fixed */
1280 
1281 /**
1282  * struct dmub_shared_state_feature_block - Feature block.
1283  */
1284 struct dmub_shared_state_feature_block {
1285 	struct dmub_shared_state_feature_header header; /**< Shared state header. */
1286 	union dmub_shared_feature_state_union {
1287 		struct dmub_shared_state_feature_common common; /**< Generic data */
1288 		struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */
1289 		struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */
1290 		struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */
1291 		struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */
1292 	} data; /**< Shared state data. */
1293 }; /* 256-bytes, fixed */
1294 
1295 /**
1296  * Shared state size in bytes.
1297  */
1298 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \
1299 	((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block))
1300 
1301 //==============================================================================
1302 //</DMUB_STATUS>================================================================
1303 //==============================================================================
1304 //< DMUB_VBIOS>=================================================================
1305 //==============================================================================
1306 
1307 /*
1308  * enum dmub_cmd_vbios_type - VBIOS commands.
1309  *
1310  * Command IDs should be treated as stable ABI.
1311  * Do not reuse or modify IDs.
1312  */
1313 enum dmub_cmd_vbios_type {
1314 	/**
1315 	 * Configures the DIG encoder.
1316 	 */
1317 	DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
1318 	/**
1319 	 * Controls the PHY.
1320 	 */
1321 	DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
1322 	/**
1323 	 * Sets the pixel clock/symbol clock.
1324 	 */
1325 	DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
1326 	/**
1327 	 * Enables or disables power gating.
1328 	 */
1329 	DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
1330 	/**
1331 	 * Controls embedded panels.
1332 	 */
1333 	DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
1334 	/**
1335 	 * Query DP alt status on a transmitter.
1336 	 */
1337 	DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT  = 26,
1338 	/**
1339 	 * Control PHY FSM
1340 	 */
1341 	DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM  = 29,
1342 	/**
1343 	 * Controls domain power gating
1344 	 */
1345 	DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
1346 };
1347 
1348 //==============================================================================
1349 //</DMUB_VBIOS>=================================================================
1350 //==============================================================================
1351 //< DMUB_GPINT>=================================================================
1352 //==============================================================================
1353 
1354 /**
1355  * The shifts and masks below may alternatively be used to format and read
1356  * the command register bits.
1357  */
1358 
1359 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
1360 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
1361 
1362 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
1363 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
1364 
1365 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
1366 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
1367 
1368 /**
1369  * Command responses.
1370  */
1371 
1372 /**
1373  * Return response for DMUB_GPINT__STOP_FW command.
1374  */
1375 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
1376 
1377 /**
1378  * union dmub_gpint_data_register - Format for sending a command via the GPINT.
1379  */
1380 union dmub_gpint_data_register {
1381 	struct {
1382 		uint32_t param : 16; /**< 16-bit parameter */
1383 		uint32_t command_code : 12; /**< GPINT command */
1384 		uint32_t status : 4; /**< Command status bit */
1385 	} bits; /**< GPINT bit access */
1386 	uint32_t all; /**< GPINT  32-bit access */
1387 };
1388 
1389 /*
1390  * enum dmub_gpint_command - GPINT command to DMCUB FW
1391  *
1392  * Command IDs should be treated as stable ABI.
1393  * Do not reuse or modify IDs.
1394  */
1395 enum dmub_gpint_command {
1396 	/**
1397 	 * Invalid command, ignored.
1398 	 */
1399 	DMUB_GPINT__INVALID_COMMAND = 0,
1400 	/**
1401 	 * DESC: Queries the firmware version.
1402 	 * RETURN: Firmware version.
1403 	 */
1404 	DMUB_GPINT__GET_FW_VERSION = 1,
1405 	/**
1406 	 * DESC: Halts the firmware.
1407 	 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
1408 	 */
1409 	DMUB_GPINT__STOP_FW = 2,
1410 	/**
1411 	 * DESC: Get PSR state from FW.
1412 	 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
1413 	 */
1414 	DMUB_GPINT__GET_PSR_STATE = 7,
1415 	/**
1416 	 * DESC: Notifies DMCUB of the currently active streams.
1417 	 * ARGS: Stream mask, 1 bit per active stream index.
1418 	 */
1419 	DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
1420 	/**
1421 	 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
1422 	 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
1423 	 *       By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
1424 	 * RETURN: PSR residency in milli-percent.
1425 	 */
1426 	DMUB_GPINT__PSR_RESIDENCY = 9,
1427 
1428 	/**
1429 	 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
1430 	 */
1431 	DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
1432 
1433 	/**
1434 	 * DESC: Get REPLAY state from FW.
1435 	 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
1436 	 */
1437 	DMUB_GPINT__GET_REPLAY_STATE = 13,
1438 
1439 	/**
1440 	 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
1441 	 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
1442 	 *       By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
1443 	 * RETURN: REPLAY residency in milli-percent.
1444 	 */
1445 	DMUB_GPINT__REPLAY_RESIDENCY = 14,
1446 
1447 	/**
1448 	 * DESC: Copy bounding box to the host.
1449 	 * ARGS: Version of bounding box to copy
1450 	 * RETURN: Result of copying bounding box
1451 	 */
1452 	DMUB_GPINT__BB_COPY = 96,
1453 
1454 	/**
1455 	 * DESC: Updates the host addresses bit48~bit63 for bounding box.
1456 	 * ARGS: The word3 for the 64 bit address
1457 	 */
1458 	DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
1459 
1460 	/**
1461 	 * DESC: Updates the host addresses bit32~bit47 for bounding box.
1462 	 * ARGS: The word2 for the 64 bit address
1463 	 */
1464 	DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
1465 
1466 	/**
1467 	 * DESC: Updates the host addresses bit16~bit31 for bounding box.
1468 	 * ARGS: The word1 for the 64 bit address
1469 	 */
1470 	DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
1471 
1472 	/**
1473 	 * DESC: Updates the host addresses bit0~bit15 for bounding box.
1474 	 * ARGS: The word0 for the 64 bit address
1475 	 */
1476 	DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
1477 
1478 	/**
1479 	 * DESC: Updates the trace buffer lower 32-bit mask.
1480 	 * ARGS: The new mask
1481 	 * RETURN: Lower 32-bit mask.
1482 	 */
1483 	DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
1484 
1485 	/**
1486 	 * DESC: Updates the trace buffer mask bit0~bit15.
1487 	 * ARGS: The new mask
1488 	 * RETURN: Lower 32-bit mask.
1489 	 */
1490 	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
1491 
1492 	/**
1493 	 * DESC: Updates the trace buffer mask bit16~bit31.
1494 	 * ARGS: The new mask
1495 	 * RETURN: Lower 32-bit mask.
1496 	 */
1497 	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
1498 
1499 	/**
1500 	 * DESC: Updates the trace buffer mask bit32~bit47.
1501 	 * ARGS: The new mask
1502 	 * RETURN: Lower 32-bit mask.
1503 	 */
1504 	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
1505 
1506 	/**
1507 	 * DESC: Updates the trace buffer mask bit48~bit63.
1508 	 * ARGS: The new mask
1509 	 * RETURN: Lower 32-bit mask.
1510 	 */
1511 	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
1512 
1513 	/**
1514 	 * DESC: Read the trace buffer mask bi0~bit15.
1515 	 */
1516 	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,
1517 
1518 	/**
1519 	 * DESC: Read the trace buffer mask bit16~bit31.
1520 	 */
1521 	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,
1522 
1523 	/**
1524 	 * DESC: Read the trace buffer mask bi32~bit47.
1525 	 */
1526 	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,
1527 
1528 	/**
1529 	 * DESC: Updates the trace buffer mask bit32~bit63.
1530 	 */
1531 	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
1532 
1533 	/**
1534 	 * DESC: Set IPS residency measurement
1535 	 * ARGS: 0 - Disable ips measurement
1536 	 *       1 - Enable ips measurement
1537 	 */
1538 	DMUB_GPINT__IPS_RESIDENCY = 121,
1539 	/**
1540 	 * DESC: Enable measurements for various task duration
1541 	 * ARGS: 0 - Disable measurement
1542 	 *       1 - Enable measurement
1543 	 */
1544 	DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,
1545 	/**
1546 	 * DESC: Gets IPS residency in microseconds
1547 	 * ARGS: 0 - Return IPS1 residency
1548 	 *       1 - Return IPS2 residency
1549 	 *       2 - Return IPS1_RCG residency
1550 	 *       3 - Return IPS1_ONO2_ON residency
1551 	 * RETURN: Total residency in microseconds - lower 32 bits
1552 	 */
1553 	DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124,
1554 	/**
1555 	 * DESC: Gets IPS1 histogram counts
1556 	 * ARGS: Bucket index
1557 	 * RETURN: Total count for the bucket
1558 	 */
1559 	DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125,
1560 	/**
1561 	 * DESC: Gets IPS2 histogram counts
1562 	 * ARGS: Bucket index
1563 	 * RETURN: Total count for the bucket
1564 	 */
1565 	DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126,
1566 	/**
1567 	 * DESC: Gets IPS residency
1568 	 * ARGS: 0 - Return IPS1 residency
1569 	 *       1 - Return IPS2 residency
1570 	 *       2 - Return IPS1_RCG residency
1571 	 *       3 - Return IPS1_ONO2_ON residency
1572 	 * RETURN: Total residency in milli-percent.
1573 	 */
1574 	DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127,
1575 	/**
1576 	 * DESC: Gets IPS1_RCG histogram counts
1577 	 * ARGS: Bucket index
1578 	 * RETURN: Total count for the bucket
1579 	 */
1580 	DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128,
1581 	/**
1582 	 * DESC: Gets IPS1_ONO2_ON histogram counts
1583 	 * ARGS: Bucket index
1584 	 * RETURN: Total count for the bucket
1585 	 */
1586 	DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129,
1587 	/**
1588 	 * DESC: Gets IPS entry counter during residency measurement
1589 	 * ARGS: 0 - Return IPS1 entry counts
1590 	 *       1 - Return IPS2 entry counts
1591 	 *       2 - Return IPS1_RCG entry counts
1592 	 *       3 - Return IPS2_ONO2_ON entry counts
1593 	 * RETURN: Entry counter for selected IPS mode
1594 	 */
1595 	DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130,
1596 	/**
1597 	 * DESC: Gets IPS inactive residency in microseconds
1598 	 * ARGS: 0 - Return IPS1_MAX residency
1599 	 *       1 - Return IPS2 residency
1600 	 *       2 - Return IPS1_RCG residency
1601 	 *       3 - Return IPS1_ONO2_ON residency
1602 	 * RETURN: Total inactive residency in microseconds - lower 32 bits
1603 	 */
1604 	DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131,
1605 	/**
1606 	 * DESC: Gets IPS inactive residency in microseconds
1607 	 * ARGS: 0 - Return IPS1_MAX residency
1608 	 *       1 - Return IPS2 residency
1609 	 *       2 - Return IPS1_RCG residency
1610 	 *       3 - Return IPS1_ONO2_ON residency
1611 	 * RETURN: Total inactive residency in microseconds - upper 32 bits
1612 	 */
1613 	DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132,
1614 	/**
1615 	 * DESC: Gets IPS residency in microseconds
1616 	 * ARGS: 0 - Return IPS1 residency
1617 	 *       1 - Return IPS2 residency
1618 	 *       2 - Return IPS1_RCG residency
1619 	 *       3 - Return IPS1_ONO2_ON residency
1620 	 * RETURN: Total residency in microseconds - upper 32 bits
1621 	 */
1622 	DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133,
1623 	/**
1624 	 * DESC: Setup debug configs.
1625 	 */
1626 	DMUB_GPINT__SETUP_DEBUG_MODE = 136,
1627 	/**
1628 	 * DESC: Initiates IPS wake sequence.
1629 	 */
1630 	DMUB_GPINT__IPS_DEBUG_WAKE = 137,
1631 	/**
1632 	 * DESC: Do panel power off sequence
1633 	 * ARGS: 1 - Power off
1634 	 */
1635 	DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138,
1636 };
1637 
1638 /**
1639  * INBOX0 generic command definition
1640  */
1641 union dmub_inbox0_cmd_common {
1642 	struct {
1643 		uint32_t command_code: 8; /**< INBOX0 command code */
1644 		uint32_t param: 24; /**< 24-bit parameter */
1645 	} bits;
1646 	uint32_t all;
1647 };
1648 
1649 /**
1650  * INBOX0 hw_lock command definition
1651  */
1652 union dmub_inbox0_cmd_lock_hw {
1653 	struct {
1654 		uint32_t command_code: 8;
1655 
1656 		/* NOTE: Must be have enough bits to match: enum hw_lock_client */
1657 		uint32_t hw_lock_client: 2;
1658 
1659 		/* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
1660 		uint32_t otg_inst: 3;
1661 		uint32_t opp_inst: 3;
1662 		uint32_t dig_inst: 3;
1663 
1664 		/* NOTE: Below fields must match with: union dmub_hw_lock_flags */
1665 		uint32_t lock_pipe: 1;
1666 		uint32_t lock_cursor: 1;
1667 		uint32_t lock_dig: 1;
1668 		uint32_t triple_buffer_lock: 1;
1669 
1670 		uint32_t lock: 1;			/**< Lock */
1671 		uint32_t should_release: 1;		/**< Release */
1672 		uint32_t reserved: 7; 			/**< Reserved for extending more clients, HW, etc. */
1673 	} bits;
1674 	uint32_t all;
1675 };
1676 
1677 union dmub_inbox0_data_register {
1678 	union dmub_inbox0_cmd_common inbox0_cmd_common;
1679 	union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
1680 };
1681 
1682 enum dmub_inbox0_command {
1683 	/**
1684 	 * DESC: Invalid command, ignored.
1685 	 */
1686 	DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
1687 	/**
1688 	 * DESC: Notification to acquire/release HW lock
1689 	 * ARGS:
1690 	 */
1691 	DMUB_INBOX0_CMD__HW_LOCK = 1,
1692 };
1693 //==============================================================================
1694 //</DMUB_GPINT>=================================================================
1695 //==============================================================================
1696 //< DMUB_CMD>===================================================================
1697 //==============================================================================
1698 
1699 /**
1700  * Size in bytes of each DMUB command.
1701  */
1702 #define DMUB_RB_CMD_SIZE 64
1703 
1704 /**
1705  * Maximum number of items in the DMUB ringbuffer.
1706  */
1707 #define DMUB_RB_MAX_ENTRY 128
1708 
1709 /**
1710  * Ringbuffer size in bytes.
1711  */
1712 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
1713 
1714 /**
1715  * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer.
1716  */
1717 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16
1718 
1719 /**
1720  * Ringbuffer size in bytes.
1721  */
1722 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY)
1723 
1724 /**
1725  * REG_SET mask for reg offload.
1726  */
1727 #define REG_SET_MASK 0xFFFF
1728 
1729 /*
1730  * enum dmub_cmd_type - DMUB inbox command.
1731  *
1732  * Command IDs should be treated as stable ABI.
1733  * Do not reuse or modify IDs.
1734  */
1735 enum dmub_cmd_type {
1736 	/**
1737 	 * Invalid command.
1738 	 */
1739 	DMUB_CMD__NULL = 0,
1740 	/**
1741 	 * Read modify write register sequence offload.
1742 	 */
1743 	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
1744 	/**
1745 	 * Field update register sequence offload.
1746 	 */
1747 	DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
1748 	/**
1749 	 * Burst write sequence offload.
1750 	 */
1751 	DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
1752 	/**
1753 	 * Reg wait sequence offload.
1754 	 */
1755 	DMUB_CMD__REG_REG_WAIT = 4,
1756 	/**
1757 	 * Workaround to avoid HUBP underflow during NV12 playback.
1758 	 */
1759 	DMUB_CMD__PLAT_54186_WA = 5,
1760 	/**
1761 	 * Command type used to query FW feature caps.
1762 	 */
1763 	DMUB_CMD__QUERY_FEATURE_CAPS = 6,
1764 	/**
1765 	 * Command type used to get visual confirm color.
1766 	 */
1767 	DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
1768 	/**
1769 	 * Command type used for all PSR commands.
1770 	 */
1771 	DMUB_CMD__PSR = 64,
1772 	/**
1773 	 * Command type used for all MALL commands.
1774 	 */
1775 	DMUB_CMD__MALL = 65,
1776 	/**
1777 	 * Command type used for all ABM commands.
1778 	 */
1779 	DMUB_CMD__ABM = 66,
1780 	/**
1781 	 * Command type used to update dirty rects in FW.
1782 	 */
1783 	DMUB_CMD__UPDATE_DIRTY_RECT = 67,
1784 	/**
1785 	 * Command type used to update cursor info in FW.
1786 	 */
1787 	DMUB_CMD__UPDATE_CURSOR_INFO = 68,
1788 	/**
1789 	 * Command type used for HW locking in FW.
1790 	 */
1791 	DMUB_CMD__HW_LOCK = 69,
1792 	/**
1793 	 * Command type used to access DP AUX.
1794 	 */
1795 	DMUB_CMD__DP_AUX_ACCESS = 70,
1796 	/**
1797 	 * Command type used for OUTBOX1 notification enable
1798 	 */
1799 	DMUB_CMD__OUTBOX1_ENABLE = 71,
1800 
1801 	/**
1802 	 * Command type used for all idle optimization commands.
1803 	 */
1804 	DMUB_CMD__IDLE_OPT = 72,
1805 	/**
1806 	 * Command type used for all clock manager commands.
1807 	 */
1808 	DMUB_CMD__CLK_MGR = 73,
1809 	/**
1810 	 * Command type used for all panel control commands.
1811 	 */
1812 	DMUB_CMD__PANEL_CNTL = 74,
1813 
1814 	/**
1815 	 * Command type used for all CAB commands.
1816 	 */
1817 	DMUB_CMD__CAB_FOR_SS = 75,
1818 
1819 	DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
1820 
1821 	/**
1822 	 * Command type used for interfacing with DPIA.
1823 	 */
1824 	DMUB_CMD__DPIA = 77,
1825 	/**
1826 	 * Command type used for EDID CEA parsing
1827 	 */
1828 	DMUB_CMD__EDID_CEA = 79,
1829 	/**
1830 	 * Command type used for getting usbc cable ID
1831 	 */
1832 	DMUB_CMD_GET_USBC_CABLE_ID = 81,
1833 	/**
1834 	 * Command type used to query HPD state.
1835 	 */
1836 	DMUB_CMD__QUERY_HPD_STATE = 82,
1837 	/**
1838 	 * Command type used for all VBIOS interface commands.
1839 	 */
1840 	/**
1841 	 * Command type used for all REPLAY commands.
1842 	 */
1843 	DMUB_CMD__REPLAY = 83,
1844 
1845 	/**
1846 	 * Command type used for all SECURE_DISPLAY commands.
1847 	 */
1848 	DMUB_CMD__SECURE_DISPLAY = 85,
1849 
1850 	/**
1851 	 * Command type used to set DPIA HPD interrupt state
1852 	 */
1853 	DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1854 
1855 	/**
1856 	 * Command type used for all PSP commands.
1857 	 */
1858 	DMUB_CMD__PSP = 88,
1859 
1860 	/**
1861 	 * Command type used for all Fused IO commands.
1862 	 */
1863 	DMUB_CMD__FUSED_IO = 89,
1864 
1865 	/**
1866 	 * Command type used for all LSDMA commands.
1867 	 */
1868 	DMUB_CMD__LSDMA = 90,
1869 
1870 	/**
1871 	 * Command type use for all IPS commands.
1872 	 */
1873 	DMUB_CMD__IPS = 91,
1874 
1875 	/**
1876 	 * Command type use for Cursor offload.
1877 	 */
1878 	DMUB_CMD__CURSOR_OFFLOAD = 92,
1879 
1880 	/**
1881 	 * Command type used for all SMART_POWER_OLED commands.
1882 	 */
1883 	DMUB_CMD__SMART_POWER_OLED = 93,
1884 
1885 	/**
1886 	 * Command type use for all Panel Replay commands.
1887 	 */
1888 	DMUB_CMD__PR = 94,
1889 
1890 	/**
1891 	 * Command type used for all IHC commands.
1892 	 */
1893 	DMUB_CMD__IHC = 95,
1894 
1895 	/**
1896 	 * Command type use for boot time crc commands.
1897 	 */
1898 	DMUB_CMD__BOOT_TIME_CRC = 96,
1899 
1900 	/**
1901 	 * Command type use for VBIOS shared commands.
1902 	 */
1903 	DMUB_CMD__VBIOS = 128,
1904 };
1905 
1906 /**
1907  * enum dmub_out_cmd_type - DMUB outbox commands.
1908  */
1909 enum dmub_out_cmd_type {
1910 	/**
1911 	 * Invalid outbox command, ignored.
1912 	 */
1913 	DMUB_OUT_CMD__NULL = 0,
1914 	/**
1915 	 * Command type used for DP AUX Reply data notification
1916 	 */
1917 	DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1918 	/**
1919 	 * Command type used for DP HPD event notification
1920 	 */
1921 	DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1922 	/**
1923 	 * Command type used for SET_CONFIG Reply notification
1924 	 */
1925 	DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1926 	/**
1927 	 * Command type used for USB4 DPIA notification
1928 	 */
1929 	DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1930 	/**
1931 	 * Command type used for HPD redetect notification
1932 	 */
1933 	DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,
1934 	/**
1935 	 * Command type used for Fused IO notification
1936 	 */
1937 	DMUB_OUT_CMD__FUSED_IO = 7,
1938 };
1939 
1940 /* DMUB_CMD__DPIA command sub-types. */
1941 enum dmub_cmd_dpia_type {
1942 	DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1943 	DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST
1944 	DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1945 	DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,
1946 	DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4,
1947 };
1948 
1949 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1950 enum dmub_cmd_dpia_notification_type {
1951 	DPIA_NOTIFY__BW_ALLOCATION = 0,
1952 };
1953 
1954 #pragma pack(push, 1)
1955 
1956 /**
1957  * struct dmub_cmd_header - Common command header fields.
1958  */
1959 struct dmub_cmd_header {
1960 	unsigned int type : 8; /**< command type */
1961 	unsigned int sub_type : 8; /**< command sub type */
1962 	unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1963 	unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1964 	unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */
1965 	unsigned int reserved0 : 5; /**< reserved bits */
1966 	unsigned int payload_bytes : 6;  /* payload excluding header - up to 60 bytes */
1967 	unsigned int reserved1 : 2; /**< reserved bits */
1968 };
1969 
1970 /*
1971  * struct dmub_cmd_read_modify_write_sequence - Read modify write
1972  *
1973  * 60 payload bytes can hold up to 5 sets of read modify writes,
1974  * each take 3 dwords.
1975  *
1976  * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1977  *
1978  * modify_mask = 0xffff'ffff means all fields are going to be updated.  in this case
1979  * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1980  */
1981 struct dmub_cmd_read_modify_write_sequence {
1982 	uint32_t addr; /**< register address */
1983 	uint32_t modify_mask; /**< modify mask */
1984 	uint32_t modify_value; /**< modify value */
1985 };
1986 
1987 /**
1988  * Maximum number of ops in read modify write sequence.
1989  */
1990 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1991 
1992 /**
1993  * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1994  */
1995 struct dmub_rb_cmd_read_modify_write {
1996 	struct dmub_cmd_header header;  /**< command header */
1997 	/**
1998 	 * Read modify write sequence.
1999 	 */
2000 	struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
2001 };
2002 
2003 /*
2004  * Update a register with specified masks and values sequeunce
2005  *
2006  * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
2007  *
2008  * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
2009  *
2010  *
2011  * USE CASE:
2012  *   1. auto-increment register where additional read would update pointer and produce wrong result
2013  *   2. toggle a bit without read in the middle
2014  */
2015 
2016 struct dmub_cmd_reg_field_update_sequence {
2017 	uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
2018 	uint32_t modify_value; /**< value to update with */
2019 };
2020 
2021 /**
2022  * Maximum number of ops in field update sequence.
2023  */
2024 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
2025 
2026 /**
2027  * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
2028  */
2029 struct dmub_rb_cmd_reg_field_update_sequence {
2030 	struct dmub_cmd_header header; /**< command header */
2031 	uint32_t addr; /**< register address */
2032 	/**
2033 	 * Field update sequence.
2034 	 */
2035 	struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
2036 };
2037 
2038 
2039 /**
2040  * Maximum number of burst write values.
2041  */
2042 #define DMUB_BURST_WRITE_VALUES__MAX  14
2043 
2044 /*
2045  * struct dmub_rb_cmd_burst_write - Burst write
2046  *
2047  * support use case such as writing out LUTs.
2048  *
2049  * 60 payload bytes can hold up to 14 values to write to given address
2050  *
2051  * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
2052  */
2053 struct dmub_rb_cmd_burst_write {
2054 	struct dmub_cmd_header header; /**< command header */
2055 	uint32_t addr; /**< register start address */
2056 	/**
2057 	 * Burst write register values.
2058 	 */
2059 	uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
2060 };
2061 
2062 /**
2063  * struct dmub_rb_cmd_common - Common command header
2064  */
2065 struct dmub_rb_cmd_common {
2066 	struct dmub_cmd_header header; /**< command header */
2067 	/**
2068 	 * Padding to RB_CMD_SIZE
2069 	 */
2070 	uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
2071 };
2072 
2073 /**
2074  * struct dmub_cmd_reg_wait_data - Register wait data
2075  */
2076 struct dmub_cmd_reg_wait_data {
2077 	uint32_t addr; /**< Register address */
2078 	uint32_t mask; /**< Mask for register bits */
2079 	uint32_t condition_field_value; /**< Value to wait for */
2080 	uint32_t time_out_us; /**< Time out for reg wait in microseconds */
2081 };
2082 
2083 /**
2084  * struct dmub_rb_cmd_reg_wait - Register wait command
2085  */
2086 struct dmub_rb_cmd_reg_wait {
2087 	struct dmub_cmd_header header; /**< Command header */
2088 	struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
2089 };
2090 
2091 /**
2092  * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
2093  *
2094  * Reprograms surface parameters to avoid underflow.
2095  */
2096 struct dmub_cmd_PLAT_54186_wa {
2097 	uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
2098 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
2099 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
2100 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
2101 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
2102 	struct {
2103 		uint32_t hubp_inst : 4; /**< HUBP instance */
2104 		uint32_t tmz_surface : 1; /**< TMZ enable or disable */
2105 		uint32_t immediate :1; /**< Immediate flip */
2106 		uint32_t vmid : 4; /**< VMID */
2107 		uint32_t grph_stereo : 1; /**< 1 if stereo */
2108 		uint32_t reserved : 21; /**< Reserved */
2109 	} flip_params; /**< Pageflip parameters */
2110 	uint32_t reserved[9]; /**< Reserved bits */
2111 };
2112 
2113 /**
2114  * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
2115  */
2116 struct dmub_rb_cmd_PLAT_54186_wa {
2117 	struct dmub_cmd_header header; /**< Command header */
2118 	struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
2119 };
2120 
2121 /**
2122  * enum dmub_cmd_mall_type - MALL commands
2123  */
2124 enum dmub_cmd_mall_type {
2125 	/**
2126 	 * Allows display refresh from MALL.
2127 	 */
2128 	DMUB_CMD__MALL_ACTION_ALLOW = 0,
2129 	/**
2130 	 * Disallows display refresh from MALL.
2131 	 */
2132 	DMUB_CMD__MALL_ACTION_DISALLOW = 1,
2133 	/**
2134 	 * Cursor copy for MALL.
2135 	 */
2136 	DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
2137 	/**
2138 	 * Controls DF requests.
2139 	 */
2140 	DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
2141 };
2142 
2143 /**
2144  * struct dmub_rb_cmd_mall - MALL command data.
2145  */
2146 struct dmub_rb_cmd_mall {
2147 	struct dmub_cmd_header header; /**< Common command header */
2148 	union dmub_addr cursor_copy_src; /**< Cursor copy address */
2149 	union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
2150 	uint32_t tmr_delay; /**< Timer delay */
2151 	uint32_t tmr_scale; /**< Timer scale */
2152 	uint16_t cursor_width; /**< Cursor width in pixels */
2153 	uint16_t cursor_pitch; /**< Cursor pitch in pixels */
2154 	uint16_t cursor_height; /**< Cursor height in pixels */
2155 	uint8_t cursor_bpp; /**< Cursor bits per pixel */
2156 	uint8_t debug_bits; /**< Debug bits */
2157 
2158 	uint8_t reserved1; /**< Reserved bits */
2159 	uint8_t reserved2; /**< Reserved bits */
2160 };
2161 
2162 /**
2163  * enum dmub_cmd_cab_type - CAB command data.
2164  */
2165 enum dmub_cmd_cab_type {
2166 	/**
2167 	 * No idle optimizations (i.e. no CAB)
2168 	 */
2169 	DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
2170 	/**
2171 	 * No DCN requests for memory
2172 	 */
2173 	DMUB_CMD__CAB_NO_DCN_REQ = 1,
2174 	/**
2175 	 * Fit surfaces in CAB (i.e. CAB enable)
2176 	 */
2177 	DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
2178 	/**
2179 	 * Do not fit surfaces in CAB (i.e. no CAB)
2180 	 */
2181 	DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
2182 };
2183 
2184 /**
2185  * struct dmub_rb_cmd_cab - CAB command data.
2186  */
2187 struct dmub_rb_cmd_cab_for_ss {
2188 	struct dmub_cmd_header header;
2189 	uint8_t cab_alloc_ways; /* total number of ways */
2190 	uint8_t debug_bits;     /* debug bits */
2191 };
2192 
2193 /**
2194  * Enum for indicating which MCLK switch mode per pipe
2195  */
2196 enum mclk_switch_mode {
2197 	NONE = 0,
2198 	FPO = 1,
2199 	SUBVP = 2,
2200 	VBLANK = 3,
2201 };
2202 
2203 /* Per pipe struct which stores the MCLK switch mode
2204  * data to be sent to DMUB.
2205  * Named "v2" for now -- once FPO and SUBVP are fully merged
2206  * the type name can be updated
2207  */
2208 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
2209 	union {
2210 		struct {
2211 			uint32_t pix_clk_100hz;
2212 			uint16_t main_vblank_start;
2213 			uint16_t main_vblank_end;
2214 			uint16_t mall_region_lines;
2215 			uint16_t prefetch_lines;
2216 			uint16_t prefetch_to_mall_start_lines;
2217 			uint16_t processing_delay_lines;
2218 			uint16_t htotal; // required to calculate line time for multi-display cases
2219 			uint16_t vtotal;
2220 			uint8_t main_pipe_index;
2221 			uint8_t phantom_pipe_index;
2222 			/* Since the microschedule is calculated in terms of OTG lines,
2223 			 * include any scaling factors to make sure when we get accurate
2224 			 * conversion when programming MALL_START_LINE (which is in terms
2225 			 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
2226 			 * is 1/2 (numerator = 1, denominator = 2).
2227 			 */
2228 			uint8_t scale_factor_numerator;
2229 			uint8_t scale_factor_denominator;
2230 			uint8_t is_drr;
2231 			uint8_t main_split_pipe_index;
2232 			uint8_t phantom_split_pipe_index;
2233 		} subvp_data;
2234 
2235 		struct {
2236 			uint32_t pix_clk_100hz;
2237 			uint16_t vblank_start;
2238 			uint16_t vblank_end;
2239 			uint16_t vstartup_start;
2240 			uint16_t vtotal;
2241 			uint16_t htotal;
2242 			uint8_t vblank_pipe_index;
2243 			uint8_t padding[1];
2244 			struct {
2245 				uint8_t drr_in_use;
2246 				uint8_t drr_window_size_ms;	// Indicates largest VMIN/VMAX adjustment per frame
2247 				uint16_t min_vtotal_supported;	// Min VTOTAL that supports switching in VBLANK
2248 				uint16_t max_vtotal_supported;	// Max VTOTAL that can support SubVP static scheduling
2249 				uint8_t use_ramping;		// Use ramping or not
2250 				uint8_t drr_vblank_start_margin;
2251 			} drr_info;				// DRR considered as part of SubVP + VBLANK case
2252 		} vblank_data;
2253 	} pipe_config;
2254 
2255 	/* - subvp_data in the union (pipe_config) takes up 27 bytes.
2256 	 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
2257 	 *   for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
2258 	 */
2259 	uint8_t mode; // enum mclk_switch_mode
2260 };
2261 
2262 /**
2263  * Config data for Sub-VP and FPO
2264  * Named "v2" for now -- once FPO and SUBVP are fully merged
2265  * the type name can be updated
2266  */
2267 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
2268 	uint16_t watermark_a_cache;
2269 	uint8_t vertical_int_margin_us;
2270 	uint8_t pstate_allow_width_us;
2271 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
2272 };
2273 
2274 /**
2275  * DMUB rb command definition for Sub-VP and FPO
2276  * Named "v2" for now -- once FPO and SUBVP are fully merged
2277  * the type name can be updated
2278  */
2279 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
2280 	struct dmub_cmd_header header;
2281 	struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
2282 };
2283 
2284 struct dmub_flip_addr_info {
2285 	uint32_t surf_addr_lo;
2286 	uint32_t surf_addr_c_lo;
2287 	uint32_t meta_addr_lo;
2288 	uint32_t meta_addr_c_lo;
2289 	uint16_t surf_addr_hi;
2290 	uint16_t surf_addr_c_hi;
2291 	uint16_t meta_addr_hi;
2292 	uint16_t meta_addr_c_hi;
2293 };
2294 
2295 struct dmub_fams2_flip_info {
2296 	union {
2297 		struct {
2298 			uint8_t is_immediate: 1;
2299 		} bits;
2300 		uint8_t all;
2301 	} config;
2302 	uint8_t otg_inst;
2303 	uint8_t pipe_mask;
2304 	uint8_t pad;
2305 	struct dmub_flip_addr_info addr_info;
2306 };
2307 
2308 struct dmub_rb_cmd_fams2_flip {
2309 	struct dmub_cmd_header header;
2310 	struct dmub_fams2_flip_info flip_info;
2311 };
2312 
2313 struct dmub_cmd_lsdma_data {
2314 	union {
2315 		struct lsdma_init_data {
2316 			union dmub_addr gpu_addr_base;
2317 			uint32_t ring_size;
2318 		} init_data;
2319 		struct lsdma_tiled_copy_data {
2320 			uint32_t src_addr_lo;
2321 			uint32_t src_addr_hi;
2322 
2323 			uint32_t dst_addr_lo;
2324 			uint32_t dst_addr_hi;
2325 
2326 			uint32_t src_x            : 16;
2327 			uint32_t src_y            : 16;
2328 
2329 			uint32_t dst_x            : 16;
2330 			uint32_t dst_y            : 16;
2331 
2332 			uint32_t src_width        : 16;
2333 			uint32_t src_height       : 16;
2334 
2335 			uint32_t dst_width        : 16;
2336 			uint32_t dst_height       : 16;
2337 
2338 			uint32_t rect_x           : 16;
2339 			uint32_t rect_y           : 16;
2340 
2341 			uint32_t src_swizzle_mode : 5;
2342 			uint32_t src_mip_max      : 5;
2343 			uint32_t src_mip_id       : 5;
2344 			uint32_t dst_mip_max      : 5;
2345 			uint32_t dst_swizzle_mode : 5;
2346 			uint32_t dst_mip_id       : 5;
2347 			uint32_t tmz              : 1;
2348 			uint32_t dcc              : 1;
2349 
2350 			uint32_t data_format      : 6;
2351 			uint32_t padding1         : 4;
2352 			uint32_t dst_element_size : 3;
2353 			uint32_t num_type         : 3;
2354 			uint32_t src_element_size : 3;
2355 			uint32_t write_compress   : 2;
2356 			uint32_t cache_policy_dst : 2;
2357 			uint32_t cache_policy_src : 2;
2358 			uint32_t read_compress    : 2;
2359 			uint32_t src_dim          : 2;
2360 			uint32_t dst_dim          : 2;
2361 			uint32_t max_uncom        : 1;
2362 
2363 			uint32_t max_com          : 2;
2364 			uint32_t padding          : 30;
2365 		} tiled_copy_data;
2366 		struct lsdma_linear_copy_data {
2367 			uint32_t src_lo;
2368 			uint32_t src_hi;
2369 
2370 			uint32_t dst_lo;
2371 			uint32_t dst_hi;
2372 
2373 			uint32_t count            : 30;
2374 			uint32_t cache_policy_dst : 2;
2375 
2376 			uint32_t tmz              : 1;
2377 			uint32_t cache_policy_src : 2;
2378 			uint32_t padding          : 29;
2379 		} linear_copy_data;
2380 		struct lsdma_linear_sub_window_copy_data {
2381 			uint32_t src_lo;
2382 			uint32_t src_hi;
2383 
2384 			uint32_t dst_lo;
2385 			uint32_t dst_hi;
2386 
2387 			uint32_t src_x        : 16;
2388 			uint32_t src_y        : 16;
2389 
2390 			uint32_t dst_x        : 16;
2391 			uint32_t dst_y        : 16;
2392 
2393 			uint32_t rect_x       : 16;
2394 			uint32_t rect_y       : 16;
2395 
2396 			uint32_t src_pitch    : 16;
2397 			uint32_t dst_pitch    : 16;
2398 
2399 			uint32_t src_slice_pitch;
2400 			uint32_t dst_slice_pitch;
2401 
2402 			uint32_t tmz              : 1;
2403 			uint32_t element_size     : 3;
2404 			uint32_t src_cache_policy : 3;
2405 			uint32_t dst_cache_policy : 3;
2406 			uint32_t reserved0        : 22;
2407 		} linear_sub_window_copy_data;
2408 		struct lsdma_reg_write_data {
2409 			uint32_t reg_addr;
2410 			uint32_t reg_data;
2411 		} reg_write_data;
2412 		struct lsdma_pio_copy_data {
2413 			uint32_t src_lo;
2414 			uint32_t src_hi;
2415 
2416 			uint32_t dst_lo;
2417 			uint32_t dst_hi;
2418 
2419 			union {
2420 				struct {
2421 					uint32_t byte_count      : 26;
2422 					uint32_t src_loc         : 1;
2423 					uint32_t dst_loc         : 1;
2424 					uint32_t src_addr_inc    : 1;
2425 					uint32_t dst_addr_inc    : 1;
2426 					uint32_t overlap_disable : 1;
2427 					uint32_t constant_fill   : 1;
2428 				} fields;
2429 				uint32_t raw;
2430 			} packet;
2431 		} pio_copy_data;
2432 		struct lsdma_pio_constfill_data {
2433 			uint32_t dst_lo;
2434 			uint32_t dst_hi;
2435 
2436 			union {
2437 				struct {
2438 					uint32_t byte_count      : 26;
2439 					uint32_t src_loc         : 1;
2440 					uint32_t dst_loc         : 1;
2441 					uint32_t src_addr_inc    : 1;
2442 					uint32_t dst_addr_inc    : 1;
2443 					uint32_t overlap_disable : 1;
2444 					uint32_t constant_fill   : 1;
2445 				} fields;
2446 				uint32_t raw;
2447 			} packet;
2448 
2449 			uint32_t data;
2450 		} pio_constfill_data;
2451 
2452 		uint32_t all[14];
2453 	} u;
2454 };
2455 
2456 struct dmub_rb_cmd_lsdma {
2457 	struct dmub_cmd_header header;
2458 	struct dmub_cmd_lsdma_data lsdma_data;
2459 };
2460 
2461 struct dmub_optc_state_v2 {
2462 	uint32_t v_total_min;
2463 	uint32_t v_total_max;
2464 	uint32_t v_total_mid;
2465 	uint32_t v_total_mid_frame_num;
2466 	uint8_t program_manual_trigger;
2467 	uint8_t tg_inst;
2468 	uint8_t pad[2];
2469 };
2470 
2471 struct dmub_optc_position {
2472 	uint32_t vpos;
2473 	uint32_t hpos;
2474 	uint32_t frame;
2475 };
2476 
2477 struct dmub_rb_cmd_fams2_drr_update {
2478 	struct dmub_cmd_header header;
2479 	struct dmub_optc_state_v2 dmub_optc_state_req;
2480 };
2481 
2482 /* HW and FW global configuration data for FAMS2 */
2483 /* FAMS2 types and structs */
2484 enum fams2_stream_type {
2485 	FAMS2_STREAM_TYPE_NONE = 0,
2486 	FAMS2_STREAM_TYPE_VBLANK = 1,
2487 	FAMS2_STREAM_TYPE_VACTIVE = 2,
2488 	FAMS2_STREAM_TYPE_DRR = 3,
2489 	FAMS2_STREAM_TYPE_SUBVP = 4,
2490 };
2491 
2492 struct dmub_rect16 {
2493 	/**
2494 	 * Dirty rect x offset.
2495 	 */
2496 	uint16_t x;
2497 
2498 	/**
2499 	 * Dirty rect y offset.
2500 	 */
2501 	uint16_t y;
2502 
2503 	/**
2504 	 * Dirty rect width.
2505 	 */
2506 	uint16_t width;
2507 
2508 	/**
2509 	 * Dirty rect height.
2510 	 */
2511 	uint16_t height;
2512 };
2513 
2514 /* static stream state */
2515 struct dmub_fams2_legacy_stream_static_state {
2516 	uint8_t vactive_det_fill_delay_otg_vlines;
2517 	uint8_t programming_delay_otg_vlines;
2518 }; //v0
2519 
2520 struct dmub_fams2_subvp_stream_static_state {
2521 	uint16_t vratio_numerator;
2522 	uint16_t vratio_denominator;
2523 	uint16_t phantom_vtotal;
2524 	uint16_t phantom_vactive;
2525 	union {
2526 		struct {
2527 			uint8_t is_multi_planar : 1;
2528 			uint8_t is_yuv420 : 1;
2529 		} bits;
2530 		uint8_t all;
2531 	} config;
2532 	uint8_t programming_delay_otg_vlines;
2533 	uint8_t prefetch_to_mall_otg_vlines;
2534 	uint8_t phantom_otg_inst;
2535 	uint8_t phantom_pipe_mask;
2536 	uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
2537 }; //v0
2538 
2539 struct dmub_fams2_drr_stream_static_state {
2540 	uint16_t nom_stretched_vtotal;
2541 	uint8_t programming_delay_otg_vlines;
2542 	uint8_t only_stretch_if_required;
2543 	uint8_t pad[2];
2544 }; //v0
2545 
2546 struct dmub_fams2_cmd_legacy_stream_static_state {
2547 	uint16_t vactive_det_fill_delay_otg_vlines;
2548 	uint16_t programming_delay_otg_vlines;
2549 	uint32_t disallow_time_us;
2550 }; //v1
2551 
2552 struct dmub_fams2_cmd_subvp_stream_static_state {
2553 	uint16_t vratio_numerator;
2554 	uint16_t vratio_denominator;
2555 	uint16_t phantom_vtotal;
2556 	uint16_t phantom_vactive;
2557 	uint16_t programming_delay_otg_vlines;
2558 	uint16_t prefetch_to_mall_otg_vlines;
2559 	union {
2560 		struct {
2561 			uint8_t is_multi_planar : 1;
2562 			uint8_t is_yuv420 : 1;
2563 		} bits;
2564 		uint8_t all;
2565 	} config;
2566 	uint8_t phantom_otg_inst;
2567 	uint8_t phantom_pipe_mask;
2568 	uint8_t pad0;
2569 	uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
2570 	uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];
2571 }; //v1
2572 
2573 struct dmub_fams2_cmd_drr_stream_static_state {
2574 	uint16_t nom_stretched_vtotal;
2575 	uint16_t programming_delay_otg_vlines;
2576 	uint8_t only_stretch_if_required;
2577 	uint8_t pad[3];
2578 }; //v1
2579 
2580 union dmub_fams2_stream_static_sub_state {
2581 	struct dmub_fams2_legacy_stream_static_state legacy;
2582 	struct dmub_fams2_subvp_stream_static_state subvp;
2583 	struct dmub_fams2_drr_stream_static_state drr;
2584 }; //v0
2585 
2586 union dmub_fams2_cmd_stream_static_sub_state {
2587 	COMMON_STREAM_STATIC_SUB_STATE
2588 }; //v1
2589 
2590 union dmub_fams2_stream_static_sub_state_v2 {
2591 	COMMON_STREAM_STATIC_SUB_STATE
2592 }; //v2
2593 
2594 struct dmub_fams2_stream_static_state {
2595 	enum fams2_stream_type type;
2596 	uint32_t otg_vline_time_ns;
2597 	uint32_t otg_vline_time_ticks;
2598 	uint16_t htotal;
2599 	uint16_t vtotal; // nominal vtotal
2600 	uint16_t vblank_start;
2601 	uint16_t vblank_end;
2602 	uint16_t max_vtotal;
2603 	uint16_t allow_start_otg_vline;
2604 	uint16_t allow_end_otg_vline;
2605 	uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
2606 	uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
2607 	uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
2608 	uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
2609 	uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
2610 	union {
2611 		struct {
2612 			uint8_t is_drr : 1; // stream is DRR enabled
2613 			uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
2614 			uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
2615 		} bits;
2616 		uint8_t all;
2617 	} config;
2618 	uint8_t otg_inst;
2619 	uint8_t pipe_mask; // pipe mask for the whole config
2620 	uint8_t num_planes;
2621 	uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
2622 	uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
2623 	union dmub_fams2_stream_static_sub_state sub_state;
2624 }; //v0
2625 
2626 struct dmub_fams2_cmd_stream_static_base_state {
2627 	enum fams2_stream_type type;
2628 	uint32_t otg_vline_time_ns;
2629 	uint32_t otg_vline_time_ticks;
2630 	uint16_t htotal;
2631 	uint16_t vtotal; // nominal vtotal
2632 	uint16_t vblank_start;
2633 	uint16_t vblank_end;
2634 	uint16_t max_vtotal;
2635 	uint16_t allow_start_otg_vline;
2636 	uint16_t allow_end_otg_vline;
2637 	uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
2638 	uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
2639 	uint16_t contention_delay_otg_vlines; // time to budget for contention on execution
2640 	uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
2641 	uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
2642 	union {
2643 		struct {
2644 			uint8_t is_drr : 1; // stream is DRR enabled
2645 			uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
2646 			uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
2647 		} bits;
2648 		uint8_t all;
2649 	} config;
2650 	uint8_t otg_inst;
2651 	uint8_t pipe_mask; // pipe mask for the whole config
2652 	uint8_t num_planes;
2653 	uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
2654 	uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
2655 }; //v1
2656 
2657 struct dmub_fams2_stream_static_state_v1 {
2658 	struct dmub_fams2_cmd_stream_static_base_state base;
2659 	union dmub_fams2_stream_static_sub_state_v2 sub_state;
2660 }; //v1
2661 
2662 /**
2663  * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
2664  * p-state request to allow latency
2665  */
2666 enum dmub_fams2_allow_delay_check_mode {
2667 	/* No check for request to allow delay */
2668 	FAMS2_ALLOW_DELAY_CHECK_NONE = 0,
2669 	/* Check for request to allow delay */
2670 	FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,
2671 	/* Check for prepare to allow delay */
2672 	FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,
2673 };
2674 
2675 union dmub_fams2_global_feature_config {
2676 	struct {
2677 		uint32_t enable: 1;
2678 		uint32_t enable_ppt_check: 1;
2679 		uint32_t enable_stall_recovery: 1;
2680 		uint32_t enable_debug: 1;
2681 		uint32_t enable_offload_flip: 1;
2682 		uint32_t enable_visual_confirm: 1;
2683 		uint32_t allow_delay_check_mode: 2;
2684 		uint32_t legacy_method_no_fams2 : 1;
2685 		uint32_t reserved : 23;
2686 	} bits;
2687 	uint32_t all;
2688 };
2689 
2690 struct dmub_cmd_fams2_global_config {
2691 	uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
2692 	uint32_t lock_wait_time_us; // time to forecast acquisition of lock
2693 	uint32_t num_streams;
2694 	union dmub_fams2_global_feature_config features;
2695 	uint32_t recovery_timeout_us;
2696 	uint32_t hwfq_flip_programming_delay_us;
2697 	uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target
2698 };
2699 
2700 union dmub_cmd_fams2_config {
2701 	struct dmub_cmd_fams2_global_config global;
2702 	struct dmub_fams2_stream_static_state stream; //v0
2703 	union {
2704 		struct dmub_fams2_cmd_stream_static_base_state base;
2705 		union dmub_fams2_cmd_stream_static_sub_state sub_state;
2706 	} stream_v1; //v1
2707 };
2708 
2709 struct dmub_fams2_config_v2 {
2710 	struct dmub_cmd_fams2_global_config global;
2711 	struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1
2712 };
2713 
2714 /**
2715  * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)
2716  */
2717 struct dmub_rb_cmd_fams2 {
2718 	struct dmub_cmd_header header;
2719 	union dmub_cmd_fams2_config config;
2720 };
2721 
2722 /**
2723  * Indirect buffer descriptor
2724  */
2725 struct dmub_ib_data {
2726 	union dmub_addr src; // location of indirect buffer in memory
2727 	uint16_t size; // indirect buffer size in bytes
2728 };
2729 
2730 /**
2731  * DMUB rb command definition for commands passed over indirect buffer
2732  */
2733 struct dmub_rb_cmd_ib {
2734 	struct dmub_cmd_header header;
2735 	struct dmub_ib_data ib_data;
2736 };
2737 
2738 /**
2739  * enum dmub_cmd_idle_opt_type - Idle optimization command type.
2740  */
2741 enum dmub_cmd_idle_opt_type {
2742 	/**
2743 	 * DCN hardware restore.
2744 	 */
2745 	DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
2746 
2747 	/**
2748 	 * DCN hardware save.
2749 	 */
2750 	DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
2751 
2752 	/**
2753 	 * DCN hardware notify idle.
2754 	 */
2755 	DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,
2756 
2757 	/**
2758 	 * DCN hardware notify power state.
2759 	 */
2760 	DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,
2761 
2762 	/**
2763 	 * DCN notify to release HW.
2764 	 */
2765 	 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4,
2766 };
2767 
2768 /**
2769  * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
2770  */
2771 struct dmub_rb_cmd_idle_opt_dcn_restore {
2772 	struct dmub_cmd_header header; /**< header */
2773 };
2774 
2775 /**
2776  * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
2777  */
2778 struct dmub_dcn_notify_idle_cntl_data {
2779 	uint8_t driver_idle;
2780 	uint8_t skip_otg_disable;
2781 	uint8_t reserved[58];
2782 };
2783 
2784 /**
2785  * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
2786  */
2787 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
2788 	struct dmub_cmd_header header; /**< header */
2789 	struct dmub_dcn_notify_idle_cntl_data cntl_data;
2790 };
2791 
2792 /**
2793  * enum dmub_idle_opt_dc_power_state - DC power states.
2794  */
2795 enum dmub_idle_opt_dc_power_state {
2796 	DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,
2797 	DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,
2798 	DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,
2799 	DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,
2800 	DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,
2801 };
2802 
2803 /**
2804  * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
2805  */
2806 struct dmub_idle_opt_set_dc_power_state_data {
2807 	uint8_t power_state; /**< power state */
2808 	uint8_t pad[3]; /**< padding */
2809 };
2810 
2811 /**
2812  * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
2813  */
2814 struct dmub_rb_cmd_idle_opt_set_dc_power_state {
2815 	struct dmub_cmd_header header; /**< header */
2816 	struct dmub_idle_opt_set_dc_power_state_data data;
2817 };
2818 
2819 /**
2820  * struct dmub_clocks - Clock update notification.
2821  */
2822 struct dmub_clocks {
2823 	uint32_t dispclk_khz; /**< dispclk kHz */
2824 	uint32_t dppclk_khz; /**< dppclk kHz */
2825 	uint32_t dcfclk_khz; /**< dcfclk kHz */
2826 	uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
2827 };
2828 
2829 /**
2830  * enum dmub_cmd_clk_mgr_type - Clock manager commands.
2831  */
2832 enum dmub_cmd_clk_mgr_type {
2833 	/**
2834 	 * Notify DMCUB of clock update.
2835 	 */
2836 	DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
2837 };
2838 
2839 /**
2840  * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
2841  */
2842 struct dmub_rb_cmd_clk_mgr_notify_clocks {
2843 	struct dmub_cmd_header header; /**< header */
2844 	struct dmub_clocks clocks; /**< clock data */
2845 };
2846 
2847 /**
2848  * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
2849  */
2850 struct dmub_cmd_digx_encoder_control_data {
2851 	union dig_encoder_control_parameters_v1_5 dig; /**< payload */
2852 };
2853 
2854 /**
2855  * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
2856  */
2857 struct dmub_rb_cmd_digx_encoder_control {
2858 	struct dmub_cmd_header header;  /**< header */
2859 	struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
2860 };
2861 
2862 /**
2863  * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
2864  */
2865 struct dmub_cmd_set_pixel_clock_data {
2866 	struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
2867 };
2868 
2869 /**
2870  * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
2871  */
2872 struct dmub_rb_cmd_set_pixel_clock {
2873 	struct dmub_cmd_header header; /**< header */
2874 	struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
2875 };
2876 
2877 /**
2878  * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
2879  */
2880 struct dmub_cmd_enable_disp_power_gating_data {
2881 	struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
2882 };
2883 
2884 /**
2885  * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
2886  */
2887 struct dmub_rb_cmd_enable_disp_power_gating {
2888 	struct dmub_cmd_header header; /**< header */
2889 	struct dmub_cmd_enable_disp_power_gating_data power_gating;  /**< payload */
2890 };
2891 
2892 /**
2893  * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
2894  */
2895 struct dmub_dig_transmitter_control_data_v1_7 {
2896 	uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
2897 	uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
2898 	union {
2899 		uint8_t digmode; /**< enum atom_encode_mode_def */
2900 		uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
2901 	} mode_laneset;
2902 	uint8_t lanenum; /**< Number of lanes */
2903 	union {
2904 		uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
2905 	} symclk_units;
2906 	uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
2907 	uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
2908 	uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
2909 	uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
2910 	uint8_t reserved1; /**< For future use */
2911 	uint8_t skip_phy_ssc_reduction;
2912 	uint8_t reserved2[2]; /**< For future use */
2913 	uint32_t reserved3[11]; /**< For future use */
2914 };
2915 
2916 /**
2917  * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
2918  */
2919 union dmub_cmd_dig1_transmitter_control_data {
2920 	struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
2921 	struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7;  /**< payload 1.7 */
2922 };
2923 
2924 /**
2925  * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
2926  */
2927 struct dmub_rb_cmd_dig1_transmitter_control {
2928 	struct dmub_cmd_header header; /**< header */
2929 	union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
2930 };
2931 
2932 /**
2933  * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
2934  */
2935 struct dmub_rb_cmd_domain_control_data {
2936 	uint8_t inst : 6; /**< DOMAIN instance to control */
2937 	uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
2938 	uint8_t reserved[3]; /**< Reserved for future use */
2939 };
2940 
2941 /**
2942  * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
2943  */
2944 struct dmub_rb_cmd_domain_control {
2945 	struct dmub_cmd_header header; /**< header */
2946 	struct dmub_rb_cmd_domain_control_data data; /**< payload */
2947 };
2948 
2949 /**
2950  * DPIA tunnel command parameters.
2951  */
2952 struct dmub_cmd_dig_dpia_control_data {
2953 	uint8_t enc_id;         /** 0 = ENGINE_ID_DIGA, ... */
2954 	uint8_t action;         /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
2955 	union {
2956 		uint8_t digmode;    /** enum atom_encode_mode_def */
2957 		uint8_t dplaneset;  /** DP voltage swing and pre-emphasis value */
2958 	} mode_laneset;
2959 	uint8_t lanenum;        /** Lane number 1, 2, 4, 8 */
2960 	uint32_t symclk_10khz;  /** Symbol Clock in 10Khz */
2961 	uint8_t hpdsel;         /** =0: HPD is not assigned */
2962 	uint8_t digfe_sel;      /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
2963 	uint8_t dpia_id;        /** Index of DPIA */
2964 	uint8_t fec_rdy : 1;
2965 	uint8_t reserved : 7;
2966 	uint32_t reserved1;
2967 };
2968 
2969 /**
2970  * DMUB command for DPIA tunnel control.
2971  */
2972 struct dmub_rb_cmd_dig1_dpia_control {
2973 	struct dmub_cmd_header header;
2974 	struct dmub_cmd_dig_dpia_control_data dpia_control;
2975 };
2976 
2977 /**
2978  * SET_CONFIG Command Payload (deprecated)
2979  */
2980 struct set_config_cmd_payload {
2981 	uint8_t msg_type; /* set config message type */
2982 	uint8_t msg_data; /* set config message data */
2983 };
2984 
2985 /**
2986  * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated)
2987  */
2988 struct dmub_cmd_set_config_control_data {
2989 	struct set_config_cmd_payload cmd_pkt;
2990 	uint8_t instance; /* DPIA instance */
2991 	uint8_t immed_status; /* Immediate status returned in case of error */
2992 };
2993 
2994 /**
2995  * SET_CONFIG Request Command Payload
2996  */
2997 struct set_config_request_cmd_payload {
2998 	uint8_t instance; /* DPIA instance */
2999 	uint8_t immed_status; /* Immediate status returned in case of error */
3000 	uint8_t msg_type; /* set config message type */
3001 	uint8_t reserved;
3002 	uint32_t msg_data; /* set config message data */
3003 };
3004 
3005 /**
3006  * DMUB command structure for SET_CONFIG command.
3007  */
3008 struct dmub_rb_cmd_set_config_access {
3009 	struct dmub_cmd_header header; /* header */
3010 	struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
3011 };
3012 
3013 /**
3014  * DMUB command structure for SET_CONFIG request command.
3015  */
3016 struct dmub_rb_cmd_set_config_request {
3017 	struct dmub_cmd_header header; /* header */
3018 	struct set_config_request_cmd_payload payload; /* set config request payload */
3019 };
3020 
3021 /**
3022  * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
3023  */
3024 struct dmub_cmd_mst_alloc_slots_control_data {
3025 	uint8_t mst_alloc_slots; /* mst slots to be allotted */
3026 	uint8_t instance; /* DPIA instance */
3027 	uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
3028 	uint8_t mst_slots_in_use; /* returns slots in use for error cases */
3029 };
3030 
3031 /**
3032  * DMUB command structure for SET_ command.
3033  */
3034 struct dmub_rb_cmd_set_mst_alloc_slots {
3035 	struct dmub_cmd_header header; /* header */
3036 	struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
3037 };
3038 
3039 /**
3040  * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command.
3041  */
3042 struct dmub_cmd_tps_notification_data {
3043 	uint8_t instance; /* DPIA instance */
3044 	uint8_t tps; /* requested training pattern */
3045 	uint8_t reserved1;
3046 	uint8_t reserved2;
3047 };
3048 
3049 /**
3050  * DMUB command structure for SET_TPS_NOTIFICATION command.
3051  */
3052 struct dmub_rb_cmd_set_tps_notification {
3053 	struct dmub_cmd_header header; /* header */
3054 	struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */
3055 };
3056 
3057 /**
3058  * DMUB command structure for DPIA HPD int enable control.
3059  */
3060 struct dmub_rb_cmd_dpia_hpd_int_enable {
3061 	struct dmub_cmd_header header; /* header */
3062 	uint32_t enable; /* dpia hpd interrupt enable */
3063 };
3064 
3065 /**
3066  * struct dmub_rb_cmd_dpphy_init - DPPHY init.
3067  */
3068 struct dmub_rb_cmd_dpphy_init {
3069 	struct dmub_cmd_header header; /**< header */
3070 	uint8_t reserved[60]; /**< reserved bits */
3071 };
3072 
3073 /**
3074  * enum dp_aux_request_action - DP AUX request command listing.
3075  *
3076  * 4 AUX request command bits are shifted to high nibble.
3077  */
3078 enum dp_aux_request_action {
3079 	/** I2C-over-AUX write request */
3080 	DP_AUX_REQ_ACTION_I2C_WRITE		= 0x00,
3081 	/** I2C-over-AUX read request */
3082 	DP_AUX_REQ_ACTION_I2C_READ		= 0x10,
3083 	/** I2C-over-AUX write status request */
3084 	DP_AUX_REQ_ACTION_I2C_STATUS_REQ	= 0x20,
3085 	/** I2C-over-AUX write request with MOT=1 */
3086 	DP_AUX_REQ_ACTION_I2C_WRITE_MOT		= 0x40,
3087 	/** I2C-over-AUX read request with MOT=1 */
3088 	DP_AUX_REQ_ACTION_I2C_READ_MOT		= 0x50,
3089 	/** I2C-over-AUX write status request with MOT=1 */
3090 	DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT	= 0x60,
3091 	/** Native AUX write request */
3092 	DP_AUX_REQ_ACTION_DPCD_WRITE		= 0x80,
3093 	/** Native AUX read request */
3094 	DP_AUX_REQ_ACTION_DPCD_READ		= 0x90
3095 };
3096 
3097 /**
3098  * enum aux_return_code_type - DP AUX process return code listing.
3099  */
3100 enum aux_return_code_type {
3101 	/** AUX process succeeded */
3102 	AUX_RET_SUCCESS = 0,
3103 	/** AUX process failed with unknown reason */
3104 	AUX_RET_ERROR_UNKNOWN,
3105 	/** AUX process completed with invalid reply */
3106 	AUX_RET_ERROR_INVALID_REPLY,
3107 	/** AUX process timed out */
3108 	AUX_RET_ERROR_TIMEOUT,
3109 	/** HPD was low during AUX process */
3110 	AUX_RET_ERROR_HPD_DISCON,
3111 	/** Failed to acquire AUX engine */
3112 	AUX_RET_ERROR_ENGINE_ACQUIRE,
3113 	/** AUX request not supported */
3114 	AUX_RET_ERROR_INVALID_OPERATION,
3115 	/** AUX process not available */
3116 	AUX_RET_ERROR_PROTOCOL_ERROR,
3117 };
3118 
3119 /**
3120  * enum aux_channel_type - DP AUX channel type listing.
3121  */
3122 enum aux_channel_type {
3123 	/** AUX thru Legacy DP AUX */
3124 	AUX_CHANNEL_LEGACY_DDC,
3125 	/** AUX thru DPIA DP tunneling */
3126 	AUX_CHANNEL_DPIA
3127 };
3128 
3129 /**
3130  * struct aux_transaction_parameters - DP AUX request transaction data
3131  */
3132 struct aux_transaction_parameters {
3133 	uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
3134 	uint8_t action; /**< enum dp_aux_request_action */
3135 	uint8_t length; /**< DP AUX request data length */
3136 	uint8_t reserved; /**< For future use */
3137 	uint32_t address; /**< DP AUX address */
3138 	uint8_t data[16]; /**< DP AUX write data */
3139 };
3140 
3141 /**
3142  * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
3143  */
3144 struct dmub_cmd_dp_aux_control_data {
3145 	uint8_t instance; /**< AUX instance or DPIA instance */
3146 	uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
3147 	uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
3148 	uint8_t reserved0; /**< For future use */
3149 	uint16_t timeout; /**< timeout time in us */
3150 	uint16_t reserved1; /**< For future use */
3151 	enum aux_channel_type type; /**< enum aux_channel_type */
3152 	struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
3153 };
3154 
3155 /**
3156  * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
3157  */
3158 struct dmub_rb_cmd_dp_aux_access {
3159 	/**
3160 	 * Command header.
3161 	 */
3162 	struct dmub_cmd_header header;
3163 	/**
3164 	 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
3165 	 */
3166 	struct dmub_cmd_dp_aux_control_data aux_control;
3167 };
3168 
3169 /**
3170  * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
3171  */
3172 struct dmub_rb_cmd_outbox1_enable {
3173 	/**
3174 	 * Command header.
3175 	 */
3176 	struct dmub_cmd_header header;
3177 	/**
3178 	 *  enable: 0x0 -> disable outbox1 notification (default value)
3179 	 *			0x1 -> enable outbox1 notification
3180 	 */
3181 	uint32_t enable;
3182 };
3183 
3184 /* DP AUX Reply command - OutBox Cmd */
3185 /**
3186  * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3187  */
3188 struct aux_reply_data {
3189 	/**
3190 	 * Aux cmd
3191 	 */
3192 	uint8_t command;
3193 	/**
3194 	 * Aux reply data length (max: 16 bytes)
3195 	 */
3196 	uint8_t length;
3197 	/**
3198 	 * Alignment only
3199 	 */
3200 	uint8_t pad[2];
3201 	/**
3202 	 * Aux reply data
3203 	 */
3204 	uint8_t data[16];
3205 };
3206 
3207 /**
3208  * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3209  */
3210 struct aux_reply_control_data {
3211 	/**
3212 	 * Reserved for future use
3213 	 */
3214 	uint32_t handle;
3215 	/**
3216 	 * Aux Instance
3217 	 */
3218 	uint8_t instance;
3219 	/**
3220 	 * Aux transaction result: definition in enum aux_return_code_type
3221 	 */
3222 	uint8_t result;
3223 	/**
3224 	 * Alignment only
3225 	 */
3226 	uint16_t pad;
3227 };
3228 
3229 /**
3230  * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
3231  */
3232 struct dmub_rb_cmd_dp_aux_reply {
3233 	/**
3234 	 * Command header.
3235 	 */
3236 	struct dmub_cmd_header header;
3237 	/**
3238 	 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3239 	 */
3240 	struct aux_reply_control_data control;
3241 	/**
3242 	 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3243 	 */
3244 	struct aux_reply_data reply_data;
3245 };
3246 
3247 /* DP HPD Notify command - OutBox Cmd */
3248 /**
3249  * DP HPD Type
3250  */
3251 enum dp_hpd_type {
3252 	/**
3253 	 * Normal DP HPD
3254 	 */
3255 	DP_HPD = 0,
3256 	/**
3257 	 * DP HPD short pulse
3258 	 */
3259 	DP_IRQ = 1,
3260 	/**
3261 	 * Failure to acquire DP HPD state
3262 	 */
3263 	DP_NONE_HPD = 2
3264 };
3265 
3266 /**
3267  * DP HPD Status
3268  */
3269 enum dp_hpd_status {
3270 	/**
3271 	 * DP_HPD status low
3272 	 */
3273 	DP_HPD_UNPLUG = 0,
3274 	/**
3275 	 * DP_HPD status high
3276 	 */
3277 	DP_HPD_PLUG
3278 };
3279 
3280 /**
3281  * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
3282  */
3283 struct dp_hpd_data {
3284 	/**
3285 	 * DP HPD instance
3286 	 */
3287 	uint8_t instance;
3288 	/**
3289 	 * HPD type
3290 	 */
3291 	uint8_t hpd_type;
3292 	/**
3293 	 * HPD status: only for type: DP_HPD to indicate status
3294 	 */
3295 	uint8_t hpd_status;
3296 	/**
3297 	 * Alignment only
3298 	 */
3299 	uint8_t pad;
3300 };
3301 
3302 /**
3303  * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
3304  */
3305 struct dmub_rb_cmd_dp_hpd_notify {
3306 	/**
3307 	 * Command header.
3308 	 */
3309 	struct dmub_cmd_header header;
3310 	/**
3311 	 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
3312 	 */
3313 	struct dp_hpd_data hpd_data;
3314 };
3315 
3316 /**
3317  * Definition of a SET_CONFIG reply from DPOA.
3318  */
3319 enum set_config_status {
3320 	SET_CONFIG_PENDING = 0,
3321 	SET_CONFIG_ACK_RECEIVED,
3322 	SET_CONFIG_RX_TIMEOUT,
3323 	SET_CONFIG_UNKNOWN_ERROR,
3324 };
3325 
3326 /**
3327  * Definition of a set_config reply
3328  */
3329 struct set_config_reply_control_data {
3330 	uint8_t instance; /* DPIA Instance */
3331 	uint8_t status; /* Set Config reply */
3332 	uint16_t pad; /* Alignment */
3333 };
3334 
3335 /**
3336  * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
3337  */
3338 struct dmub_rb_cmd_dp_set_config_reply {
3339 	struct dmub_cmd_header header;
3340 	struct set_config_reply_control_data set_config_reply_control;
3341 };
3342 
3343 /**
3344  * Definition of a DPIA notification header
3345  */
3346 struct dpia_notification_header {
3347 	uint8_t instance; /**< DPIA Instance */
3348 	uint8_t reserved[3];
3349 	enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
3350 };
3351 
3352 /**
3353  * Definition of the common data struct of DPIA notification
3354  */
3355 struct dpia_notification_common {
3356 	uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
3357 								- sizeof(struct dpia_notification_header)];
3358 };
3359 
3360 /**
3361  * Definition of a DPIA notification data
3362  */
3363 struct dpia_bw_allocation_notify_data {
3364 	union {
3365 		struct {
3366 			uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
3367 			uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
3368 			uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
3369 			uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
3370 			uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
3371 			uint16_t reserved: 11; /**< Reserved */
3372 		} bits;
3373 
3374 		uint16_t flags;
3375 	};
3376 
3377 	uint8_t cm_id; /**< CM ID */
3378 	uint8_t group_id; /**< Group ID */
3379 	uint8_t granularity; /**< BW Allocation Granularity */
3380 	uint8_t estimated_bw; /**< Estimated_BW */
3381 	uint8_t allocated_bw; /**< Allocated_BW */
3382 	uint8_t reserved;
3383 };
3384 
3385 /**
3386  * union dpia_notify_data_type - DPIA Notification in Outbox command
3387  */
3388 union dpia_notification_data {
3389 	/**
3390 	 * DPIA Notification for common data struct
3391 	 */
3392 	struct dpia_notification_common common_data;
3393 
3394 	/**
3395 	 * DPIA Notification for DP BW Allocation support
3396 	 */
3397 	struct dpia_bw_allocation_notify_data dpia_bw_alloc;
3398 };
3399 
3400 /**
3401  * Definition of a DPIA notification payload
3402  */
3403 struct dpia_notification_payload {
3404 	struct dpia_notification_header header;
3405 	union dpia_notification_data data; /**< DPIA notification payload data */
3406 };
3407 
3408 /**
3409  * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
3410  */
3411 struct dmub_rb_cmd_dpia_notification {
3412 	struct dmub_cmd_header header; /**< DPIA notification header */
3413 	struct dpia_notification_payload payload; /**< DPIA notification payload */
3414 };
3415 
3416 /**
3417  * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
3418  */
3419 struct dmub_cmd_hpd_state_query_data {
3420 	uint8_t instance; /**< HPD instance or DPIA instance */
3421 	uint8_t result; /**< For returning HPD state */
3422 	uint16_t pad; /** < Alignment */
3423 	enum aux_channel_type ch_type; /**< enum aux_channel_type */
3424 	enum aux_return_code_type status; /**< for returning the status of command */
3425 };
3426 
3427 /**
3428  * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
3429  */
3430 struct dmub_rb_cmd_query_hpd_state {
3431 	/**
3432 	 * Command header.
3433 	 */
3434 	struct dmub_cmd_header header;
3435 	/**
3436 	 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
3437 	 */
3438 	struct dmub_cmd_hpd_state_query_data data;
3439 };
3440 
3441 /**
3442  * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.
3443  */
3444 struct dmub_rb_cmd_hpd_sense_notify_data {
3445 	uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */
3446 	uint32_t new_hpd_sense_mask; /**< New HPD sense mask */
3447 };
3448 
3449 /**
3450  * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.
3451  */
3452 struct dmub_rb_cmd_hpd_sense_notify {
3453 	struct dmub_cmd_header header; /**< header */
3454 	struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */
3455 };
3456 
3457 /*
3458  * Command IDs should be treated as stable ABI.
3459  * Do not reuse or modify IDs.
3460  */
3461 
3462 /**
3463  * PSR command sub-types.
3464  */
3465 enum dmub_cmd_psr_type {
3466 	/**
3467 	 * Set PSR version support.
3468 	 */
3469 	DMUB_CMD__PSR_SET_VERSION		= 0,
3470 	/**
3471 	 * Copy driver-calculated parameters to PSR state.
3472 	 */
3473 	DMUB_CMD__PSR_COPY_SETTINGS		= 1,
3474 	/**
3475 	 * Enable PSR.
3476 	 */
3477 	DMUB_CMD__PSR_ENABLE			= 2,
3478 
3479 	/**
3480 	 * Disable PSR.
3481 	 */
3482 	DMUB_CMD__PSR_DISABLE			= 3,
3483 
3484 	/**
3485 	 * Set PSR level.
3486 	 * PSR level is a 16-bit value dicated by driver that
3487 	 * will enable/disable different functionality.
3488 	 */
3489 	DMUB_CMD__PSR_SET_LEVEL			= 4,
3490 
3491 	/**
3492 	 * Forces PSR enabled until an explicit PSR disable call.
3493 	 */
3494 	DMUB_CMD__PSR_FORCE_STATIC		= 5,
3495 	/**
3496 	 * Set vtotal in psr active for FreeSync PSR.
3497 	 */
3498 	DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
3499 	/**
3500 	 * Set PSR power option
3501 	 */
3502 	DMUB_CMD__SET_PSR_POWER_OPT = 7,
3503 };
3504 
3505 /**
3506  * Different PSR residency modes.
3507  * Different modes change the definition of PSR residency.
3508  */
3509 enum psr_residency_mode {
3510 	PSR_RESIDENCY_MODE_PHY = 0,
3511 	PSR_RESIDENCY_MODE_ALPM,
3512 	PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
3513 	/* Do not add below. */
3514 	PSR_RESIDENCY_MODE_LAST_ELEMENT,
3515 };
3516 
3517 enum dmub_cmd_fams_type {
3518 	DMUB_CMD__FAMS_SETUP_FW_CTRL	= 0,
3519 	DMUB_CMD__FAMS_DRR_UPDATE		= 1,
3520 	DMUB_CMD__HANDLE_SUBVP_CMD	= 2, // specifically for SubVP cmd
3521 	/**
3522 	 * For SubVP set manual trigger in FW because it
3523 	 * triggers DRR_UPDATE_PENDING which SubVP relies
3524 	 * on (for any SubVP cases that use a DRR display)
3525 	 */
3526 	DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
3527 	DMUB_CMD__FAMS2_CONFIG = 4,
3528 	DMUB_CMD__FAMS2_DRR_UPDATE = 5,
3529 	DMUB_CMD__FAMS2_FLIP = 6,
3530 	DMUB_CMD__FAMS2_IB_CONFIG = 7,
3531 };
3532 
3533 /**
3534  * PSR versions.
3535  */
3536 enum psr_version {
3537 	/**
3538 	 * PSR version 1.
3539 	 */
3540 	PSR_VERSION_1				= 0,
3541 	/**
3542 	 * Freesync PSR SU.
3543 	 */
3544 	PSR_VERSION_SU_1			= 1,
3545 	/**
3546 	 * PSR not supported.
3547 	 */
3548 	PSR_VERSION_UNSUPPORTED			= 0xFF,	// psr_version field is only 8 bits wide
3549 };
3550 
3551 /**
3552  * PHY Link rate for DP.
3553  */
3554 enum phy_link_rate {
3555 	/**
3556 	 * not supported.
3557 	 */
3558 	PHY_RATE_UNKNOWN = 0,
3559 	/**
3560 	 * Rate_1 (RBR)	- 1.62 Gbps/Lane
3561 	 */
3562 	PHY_RATE_162 = 1,
3563 	/**
3564 	 * Rate_2		- 2.16 Gbps/Lane
3565 	 */
3566 	PHY_RATE_216 = 2,
3567 	/**
3568 	 * Rate_3		- 2.43 Gbps/Lane
3569 	 */
3570 	PHY_RATE_243 = 3,
3571 	/**
3572 	 * Rate_4 (HBR)	- 2.70 Gbps/Lane
3573 	 */
3574 	PHY_RATE_270 = 4,
3575 	/**
3576 	 * Rate_5 (RBR2)- 3.24 Gbps/Lane
3577 	 */
3578 	PHY_RATE_324 = 5,
3579 	/**
3580 	 * Rate_6		- 4.32 Gbps/Lane
3581 	 */
3582 	PHY_RATE_432 = 6,
3583 	/**
3584 	 * Rate_7 (HBR2)- 5.40 Gbps/Lane
3585 	 */
3586 	PHY_RATE_540 = 7,
3587 	/**
3588 	 * Rate_8 (HBR3)- 8.10 Gbps/Lane
3589 	 */
3590 	PHY_RATE_810 = 8,
3591 	/**
3592 	 * UHBR10 - 10.0 Gbps/Lane
3593 	 */
3594 	PHY_RATE_1000 = 9,
3595 	/**
3596 	 * UHBR13.5 - 13.5 Gbps/Lane
3597 	 */
3598 	PHY_RATE_1350 = 10,
3599 	/**
3600 	 * UHBR10 - 20.0 Gbps/Lane
3601 	 */
3602 	PHY_RATE_2000 = 11,
3603 
3604 	PHY_RATE_675 = 12,
3605 	/**
3606 	 * Rate 12 - 6.75 Gbps/Lane
3607 	 */
3608 };
3609 
3610 /**
3611  * enum dmub_phy_fsm_state - PHY FSM states.
3612  * PHY FSM state to transit to during PSR enable/disable.
3613  */
3614 enum dmub_phy_fsm_state {
3615 	DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
3616 	DMUB_PHY_FSM_RESET,
3617 	DMUB_PHY_FSM_RESET_RELEASED,
3618 	DMUB_PHY_FSM_SRAM_LOAD_DONE,
3619 	DMUB_PHY_FSM_INITIALIZED,
3620 	DMUB_PHY_FSM_CALIBRATED,
3621 	DMUB_PHY_FSM_CALIBRATED_LP,
3622 	DMUB_PHY_FSM_CALIBRATED_PG,
3623 	DMUB_PHY_FSM_POWER_DOWN,
3624 	DMUB_PHY_FSM_PLL_EN,
3625 	DMUB_PHY_FSM_TX_EN,
3626 	DMUB_PHY_FSM_TX_EN_TEST_MODE,
3627 	DMUB_PHY_FSM_FAST_LP,
3628 	DMUB_PHY_FSM_P2_PLL_OFF_CPM,
3629 	DMUB_PHY_FSM_P2_PLL_OFF_PG,
3630 	DMUB_PHY_FSM_P2_PLL_OFF,
3631 	DMUB_PHY_FSM_P2_PLL_ON,
3632 };
3633 
3634 /**
3635  * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
3636  */
3637 struct dmub_cmd_psr_copy_settings_data {
3638 	/**
3639 	 * Flags that can be set by driver to change some PSR behaviour.
3640 	 */
3641 	union dmub_psr_debug_flags debug;
3642 	/**
3643 	 * 16-bit value dicated by driver that will enable/disable different functionality.
3644 	 */
3645 	uint16_t psr_level;
3646 	/**
3647 	 * DPP HW instance.
3648 	 */
3649 	uint8_t dpp_inst;
3650 	/**
3651 	 * MPCC HW instance.
3652 	 * Not used in dmub fw,
3653 	 * dmub fw will get active opp by reading odm registers.
3654 	 */
3655 	uint8_t mpcc_inst;
3656 	/**
3657 	 * OPP HW instance.
3658 	 * Not used in dmub fw,
3659 	 * dmub fw will get active opp by reading odm registers.
3660 	 */
3661 	uint8_t opp_inst;
3662 	/**
3663 	 * OTG HW instance.
3664 	 */
3665 	uint8_t otg_inst;
3666 	/**
3667 	 * DIG FE HW instance.
3668 	 */
3669 	uint8_t digfe_inst;
3670 	/**
3671 	 * DIG BE HW instance.
3672 	 */
3673 	uint8_t digbe_inst;
3674 	/**
3675 	 * DP PHY HW instance.
3676 	 */
3677 	uint8_t dpphy_inst;
3678 	/**
3679 	 * AUX HW instance.
3680 	 */
3681 	uint8_t aux_inst;
3682 	/**
3683 	 * Determines if SMU optimzations are enabled/disabled.
3684 	 */
3685 	uint8_t smu_optimizations_en;
3686 	/**
3687 	 * Unused.
3688 	 * TODO: Remove.
3689 	 */
3690 	uint8_t frame_delay;
3691 	/**
3692 	 * If RFB setup time is greater than the total VBLANK time,
3693 	 * it is not possible for the sink to capture the video frame
3694 	 * in the same frame the SDP is sent. In this case,
3695 	 * the frame capture indication bit should be set and an extra
3696 	 * static frame should be transmitted to the sink.
3697 	 */
3698 	uint8_t frame_cap_ind;
3699 	/**
3700 	 * Granularity of Y offset supported by sink.
3701 	 */
3702 	uint8_t su_y_granularity;
3703 	/**
3704 	 * Indicates whether sink should start capturing
3705 	 * immediately following active scan line,
3706 	 * or starting with the 2nd active scan line.
3707 	 */
3708 	uint8_t line_capture_indication;
3709 	/**
3710 	 * Multi-display optimizations are implemented on certain ASICs.
3711 	 */
3712 	uint8_t multi_disp_optimizations_en;
3713 	/**
3714 	 * The last possible line SDP may be transmitted without violating
3715 	 * the RFB setup time or entering the active video frame.
3716 	 */
3717 	uint16_t init_sdp_deadline;
3718 	/**
3719 	 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
3720 	 */
3721 	uint8_t rate_control_caps;
3722 	/*
3723 	 * Force PSRSU always doing full frame update
3724 	 */
3725 	uint8_t force_ffu_mode;
3726 	/**
3727 	 * Length of each horizontal line in us.
3728 	 */
3729 	uint32_t line_time_in_us;
3730 	/**
3731 	 * FEC enable status in driver
3732 	 */
3733 	uint8_t fec_enable_status;
3734 	/**
3735 	 * FEC re-enable delay when PSR exit.
3736 	 * unit is 100us, range form 0~255(0xFF).
3737 	 */
3738 	uint8_t fec_enable_delay_in100us;
3739 	/**
3740 	 * PSR control version.
3741 	 */
3742 	uint8_t cmd_version;
3743 	/**
3744 	 * Panel Instance.
3745 	 * Panel instance to identify which psr_state to use
3746 	 * Currently the support is only for 0 or 1
3747 	 */
3748 	uint8_t panel_inst;
3749 	/*
3750 	 * DSC enable status in driver
3751 	 */
3752 	uint8_t dsc_enable_status;
3753 	/*
3754 	 * Use FSM state for PSR power up/down
3755 	 */
3756 	uint8_t use_phy_fsm;
3757 	/**
3758 	 * frame delay for frame re-lock
3759 	 */
3760 	uint8_t relock_delay_frame_cnt;
3761 	/**
3762 	 * esd recovery indicate.
3763 	 */
3764 	uint8_t esd_recovery;
3765 	/**
3766 	 * DSC Slice height.
3767 	 */
3768 	uint16_t dsc_slice_height;
3769 	/**
3770 	 * Some panels request main link off before xth vertical line
3771 	 */
3772 	uint16_t poweroff_before_vertical_line;
3773 	/**
3774 	 * Some panels cannot handle idle pattern during PSR entry.
3775 	 * To power down phy before disable stream to avoid sending
3776 	 * idle pattern.
3777 	 */
3778 	uint8_t power_down_phy_before_disable_stream;
3779 };
3780 
3781 /**
3782  * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3783  */
3784 struct dmub_rb_cmd_psr_copy_settings {
3785 	/**
3786 	 * Command header.
3787 	 */
3788 	struct dmub_cmd_header header;
3789 	/**
3790 	 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
3791 	 */
3792 	struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
3793 };
3794 
3795 /**
3796  * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
3797  */
3798 struct dmub_cmd_psr_set_level_data {
3799 	/**
3800 	 * 16-bit value dicated by driver that will enable/disable different functionality.
3801 	 */
3802 	uint16_t psr_level;
3803 	/**
3804 	 * PSR control version.
3805 	 */
3806 	uint8_t cmd_version;
3807 	/**
3808 	 * Panel Instance.
3809 	 * Panel instance to identify which psr_state to use
3810 	 * Currently the support is only for 0 or 1
3811 	 */
3812 	uint8_t panel_inst;
3813 };
3814 
3815 /**
3816  * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3817  */
3818 struct dmub_rb_cmd_psr_set_level {
3819 	/**
3820 	 * Command header.
3821 	 */
3822 	struct dmub_cmd_header header;
3823 	/**
3824 	 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3825 	 */
3826 	struct dmub_cmd_psr_set_level_data psr_set_level_data;
3827 };
3828 
3829 struct dmub_rb_cmd_psr_enable_data {
3830 	/**
3831 	 * PSR control version.
3832 	 */
3833 	uint8_t cmd_version;
3834 	/**
3835 	 * Panel Instance.
3836 	 * Panel instance to identify which psr_state to use
3837 	 * Currently the support is only for 0 or 1
3838 	 */
3839 	uint8_t panel_inst;
3840 	/**
3841 	 * Phy state to enter.
3842 	 * Values to use are defined in dmub_phy_fsm_state
3843 	 */
3844 	uint8_t phy_fsm_state;
3845 	/**
3846 	 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3847 	 * Set this using enum phy_link_rate.
3848 	 * This does not support HDMI/DP2 for now.
3849 	 */
3850 	uint8_t phy_rate;
3851 };
3852 
3853 /**
3854  * Definition of a DMUB_CMD__PSR_ENABLE command.
3855  * PSR enable/disable is controlled using the sub_type.
3856  */
3857 struct dmub_rb_cmd_psr_enable {
3858 	/**
3859 	 * Command header.
3860 	 */
3861 	struct dmub_cmd_header header;
3862 
3863 	struct dmub_rb_cmd_psr_enable_data data;
3864 };
3865 
3866 /**
3867  * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
3868  */
3869 struct dmub_cmd_psr_set_version_data {
3870 	/**
3871 	 * PSR version that FW should implement.
3872 	 */
3873 	enum psr_version version;
3874 	/**
3875 	 * PSR control version.
3876 	 */
3877 	uint8_t cmd_version;
3878 	/**
3879 	 * Panel Instance.
3880 	 * Panel instance to identify which psr_state to use
3881 	 * Currently the support is only for 0 or 1
3882 	 */
3883 	uint8_t panel_inst;
3884 	/**
3885 	 * Explicit padding to 4 byte boundary.
3886 	 */
3887 	uint8_t pad[2];
3888 };
3889 
3890 /**
3891  * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3892  */
3893 struct dmub_rb_cmd_psr_set_version {
3894 	/**
3895 	 * Command header.
3896 	 */
3897 	struct dmub_cmd_header header;
3898 	/**
3899 	 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
3900 	 */
3901 	struct dmub_cmd_psr_set_version_data psr_set_version_data;
3902 };
3903 
3904 struct dmub_cmd_psr_force_static_data {
3905 	/**
3906 	 * PSR control version.
3907 	 */
3908 	uint8_t cmd_version;
3909 	/**
3910 	 * Panel Instance.
3911 	 * Panel instance to identify which psr_state to use
3912 	 * Currently the support is only for 0 or 1
3913 	 */
3914 	uint8_t panel_inst;
3915 	/**
3916 	 * Explicit padding to 4 byte boundary.
3917 	 */
3918 	uint8_t pad[2];
3919 };
3920 
3921 /**
3922  * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3923  */
3924 struct dmub_rb_cmd_psr_force_static {
3925 	/**
3926 	 * Command header.
3927 	 */
3928 	struct dmub_cmd_header header;
3929 	/**
3930 	 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
3931 	 */
3932 	struct dmub_cmd_psr_force_static_data psr_force_static_data;
3933 };
3934 
3935 /**
3936  * PSR SU debug flags.
3937  */
3938 union dmub_psr_su_debug_flags {
3939 	/**
3940 	 * PSR SU debug flags.
3941 	 */
3942 	struct {
3943 		/**
3944 		 * Update dirty rect in SW only.
3945 		 */
3946 		uint8_t update_dirty_rect_only : 1;
3947 		/**
3948 		 * Reset the cursor/plane state before processing the call.
3949 		 */
3950 		uint8_t reset_state : 1;
3951 	} bitfields;
3952 
3953 	/**
3954 	 * Union for debug flags.
3955 	 */
3956 	uint32_t u32All;
3957 };
3958 
3959 /**
3960  * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3961  * This triggers a selective update for PSR SU.
3962  */
3963 struct dmub_cmd_update_dirty_rect_data {
3964 	/**
3965 	 * Dirty rects from OS.
3966 	 */
3967 	struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
3968 	/**
3969 	 * PSR SU debug flags.
3970 	 */
3971 	union dmub_psr_su_debug_flags debug_flags;
3972 	/**
3973 	 * Pipe index.
3974 	 */
3975 	uint8_t pipe_idx;
3976 	/**
3977 	 * Number of dirty rects.
3978 	 */
3979 	uint8_t dirty_rect_count;
3980 	/**
3981 	 * dirty rects cmd version.
3982 	 */
3983 	uint8_t cmd_version;
3984 	/**
3985 	 * Panel Instance.
3986 	 * Panel instance to identify which psr_state to use
3987 	 * Currently the support is only for 0 or 1
3988 	 */
3989 	uint8_t panel_inst;
3990 	/**
3991 	 * OTG HW instance
3992 	 */
3993 	uint8_t otg_inst;
3994 	/**
3995 	 * Padding for 4 byte alignment
3996 	 */
3997 	uint8_t padding[3];
3998 };
3999 
4000 /**
4001  * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
4002  */
4003 struct dmub_rb_cmd_update_dirty_rect {
4004 	/**
4005 	 * Command header.
4006 	 */
4007 	struct dmub_cmd_header header;
4008 	/**
4009 	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
4010 	 */
4011 	struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
4012 };
4013 
4014 /**
4015  * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
4016  */
4017 union dmub_reg_cursor_control_cfg {
4018 	struct {
4019 		uint32_t     cur_enable: 1;
4020 		uint32_t         reser0: 3;
4021 		uint32_t cur_2x_magnify: 1;
4022 		uint32_t         reser1: 3;
4023 		uint32_t           mode: 3;
4024 		uint32_t         reser2: 5;
4025 		uint32_t          pitch: 2;
4026 		uint32_t         reser3: 6;
4027 		uint32_t line_per_chunk: 5;
4028 		uint32_t         reser4: 3;
4029 	} bits;
4030 	uint32_t raw;
4031 };
4032 struct dmub_cursor_position_cache_hubp {
4033 	union dmub_reg_cursor_control_cfg cur_ctl;
4034 	union dmub_reg_position_cfg {
4035 		struct {
4036 			uint32_t cur_x_pos: 16;
4037 			uint32_t cur_y_pos: 16;
4038 		} bits;
4039 		uint32_t raw;
4040 	} position;
4041 	union dmub_reg_hot_spot_cfg {
4042 		struct {
4043 			uint32_t hot_x: 16;
4044 			uint32_t hot_y: 16;
4045 		} bits;
4046 		uint32_t raw;
4047 	} hot_spot;
4048 	union dmub_reg_dst_offset_cfg {
4049 		struct {
4050 			uint32_t dst_x_offset: 13;
4051 			uint32_t reserved: 19;
4052 		} bits;
4053 		uint32_t raw;
4054 	} dst_offset;
4055 };
4056 
4057 union dmub_reg_cur0_control_cfg {
4058 	struct {
4059 		uint32_t     cur0_enable: 1;
4060 		uint32_t  expansion_mode: 1;
4061 		uint32_t          reser0: 1;
4062 		uint32_t     cur0_rom_en: 1;
4063 		uint32_t            mode: 3;
4064 		uint32_t        reserved: 25;
4065 	} bits;
4066 	uint32_t raw;
4067 };
4068 struct dmub_cursor_position_cache_dpp {
4069 	union dmub_reg_cur0_control_cfg cur0_ctl;
4070 };
4071 struct dmub_cursor_position_cfg {
4072 	struct  dmub_cursor_position_cache_hubp pHubp;
4073 	struct  dmub_cursor_position_cache_dpp  pDpp;
4074 	uint8_t pipe_idx;
4075 	/*
4076 	 * Padding is required. To be 4 Bytes Aligned.
4077 	 */
4078 	uint8_t padding[3];
4079 };
4080 
4081 struct dmub_cursor_attribute_cache_hubp {
4082 	uint32_t SURFACE_ADDR_HIGH;
4083 	uint32_t SURFACE_ADDR;
4084 	union    dmub_reg_cursor_control_cfg  cur_ctl;
4085 	union    dmub_reg_cursor_size_cfg {
4086 		struct {
4087 			uint32_t width: 16;
4088 			uint32_t height: 16;
4089 		} bits;
4090 		uint32_t raw;
4091 	} size;
4092 	union    dmub_reg_cursor_settings_cfg {
4093 		struct {
4094 			uint32_t     dst_y_offset: 8;
4095 			uint32_t chunk_hdl_adjust: 2;
4096 			uint32_t         reserved: 22;
4097 		} bits;
4098 		uint32_t raw;
4099 	} settings;
4100 };
4101 struct dmub_cursor_attribute_cache_dpp {
4102 	union dmub_reg_cur0_control_cfg cur0_ctl;
4103 };
4104 struct dmub_cursor_attributes_cfg {
4105 	struct  dmub_cursor_attribute_cache_hubp aHubp;
4106 	struct  dmub_cursor_attribute_cache_dpp  aDpp;
4107 };
4108 
4109 struct dmub_cmd_update_cursor_payload0 {
4110 	/**
4111 	 * Cursor dirty rects.
4112 	 */
4113 	struct dmub_rect cursor_rect;
4114 	/**
4115 	 * PSR SU debug flags.
4116 	 */
4117 	union dmub_psr_su_debug_flags debug_flags;
4118 	/**
4119 	 * Cursor enable/disable.
4120 	 */
4121 	uint8_t enable;
4122 	/**
4123 	 * Pipe index.
4124 	 */
4125 	uint8_t pipe_idx;
4126 	/**
4127 	 * Cursor update cmd version.
4128 	 */
4129 	uint8_t cmd_version;
4130 	/**
4131 	 * Panel Instance.
4132 	 * Panel instance to identify which psr_state to use
4133 	 * Currently the support is only for 0 or 1
4134 	 */
4135 	uint8_t panel_inst;
4136 	/**
4137 	 * Cursor Position Register.
4138 	 * Registers contains Hubp & Dpp modules
4139 	 */
4140 	struct dmub_cursor_position_cfg position_cfg;
4141 	/**
4142 	 * OTG HW instance
4143 	 */
4144 	uint8_t otg_inst;
4145 	/**
4146 	 * Padding for 4 byte alignment
4147 	 */
4148 	uint8_t padding[3];
4149 };
4150 
4151 struct dmub_cmd_update_cursor_payload1 {
4152 	struct dmub_cursor_attributes_cfg attribute_cfg;
4153 };
4154 
4155 union dmub_cmd_update_cursor_info_data {
4156 	struct dmub_cmd_update_cursor_payload0 payload0;
4157 	struct dmub_cmd_update_cursor_payload1 payload1;
4158 };
4159 /**
4160  * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
4161  */
4162 struct dmub_rb_cmd_update_cursor_info {
4163 	/**
4164 	 * Command header.
4165 	 */
4166 	struct dmub_cmd_header header;
4167 	/**
4168 	 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
4169 	 */
4170 	union dmub_cmd_update_cursor_info_data update_cursor_info_data;
4171 };
4172 
4173 /**
4174  * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4175  */
4176 struct dmub_cmd_psr_set_vtotal_data {
4177 	/**
4178 	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
4179 	 */
4180 	uint16_t psr_vtotal_idle;
4181 	/**
4182 	 * PSR control version.
4183 	 */
4184 	uint8_t cmd_version;
4185 	/**
4186 	 * Panel Instance.
4187 	 * Panel instance to identify which psr_state to use
4188 	 * Currently the support is only for 0 or 1
4189 	 */
4190 	uint8_t panel_inst;
4191 	/*
4192 	 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
4193 	 */
4194 	uint16_t psr_vtotal_su;
4195 	/**
4196 	 * Explicit padding to 4 byte boundary.
4197 	 */
4198 	uint8_t pad2[2];
4199 };
4200 
4201 /**
4202  * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4203  */
4204 struct dmub_rb_cmd_psr_set_vtotal {
4205 	/**
4206 	 * Command header.
4207 	 */
4208 	struct dmub_cmd_header header;
4209 	/**
4210 	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4211 	 */
4212 	struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
4213 };
4214 
4215 /**
4216  * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
4217  */
4218 struct dmub_cmd_psr_set_power_opt_data {
4219 	/**
4220 	 * PSR control version.
4221 	 */
4222 	uint8_t cmd_version;
4223 	/**
4224 	 * Panel Instance.
4225 	 * Panel instance to identify which psr_state to use
4226 	 * Currently the support is only for 0 or 1
4227 	 */
4228 	uint8_t panel_inst;
4229 	/**
4230 	 * Explicit padding to 4 byte boundary.
4231 	 */
4232 	uint8_t pad[2];
4233 	/**
4234 	 * PSR power option
4235 	 */
4236 	uint32_t power_opt;
4237 };
4238 
4239 /**
4240  * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
4241  */
4242 struct dmub_rb_cmd_psr_set_power_opt {
4243 	/**
4244 	 * Command header.
4245 	 */
4246 	struct dmub_cmd_header header;
4247 	/**
4248 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
4249 	 */
4250 	struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
4251 };
4252 
4253 enum dmub_alpm_mode {
4254 	ALPM_AUXWAKE = 0,
4255 	ALPM_AUXLESS = 1,
4256 	ALPM_UNSUPPORTED = 2,
4257 };
4258 
4259 /**
4260  * Definition of Replay Residency GPINT command.
4261  * Bit[0] - Residency mode for Revision 0
4262  * Bit[1] - Enable/Disable state
4263  * Bit[2-3] - Revision number
4264  * Bit[4-7] - Residency mode for Revision 1
4265  * Bit[8] - Panel instance
4266  * Bit[9-15] - Reserved
4267  */
4268 
4269 enum pr_residency_mode {
4270 	PR_RESIDENCY_MODE_PHY = 0x0,
4271 	PR_RESIDENCY_MODE_ALPM,
4272 	PR_RESIDENCY_MODE_IPS2,
4273 	PR_RESIDENCY_MODE_FRAME_CNT,
4274 	PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
4275 };
4276 
4277 #define REPLAY_RESIDENCY_MODE_SHIFT            (0)
4278 #define REPLAY_RESIDENCY_ENABLE_SHIFT          (1)
4279 #define REPLAY_RESIDENCY_REVISION_SHIFT        (2)
4280 #define REPLAY_RESIDENCY_MODE2_SHIFT           (4)
4281 
4282 #define REPLAY_RESIDENCY_MODE_MASK             (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
4283 # define REPLAY_RESIDENCY_FIELD_MODE_PHY       (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
4284 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM      (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
4285 
4286 #define REPLAY_RESIDENCY_MODE2_MASK            (0xF << REPLAY_RESIDENCY_MODE2_SHIFT)
4287 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS      (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT)
4288 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT    (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT)
4289 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD	(0x3 << REPLAY_RESIDENCY_MODE2_SHIFT)
4290 
4291 #define REPLAY_RESIDENCY_ENABLE_MASK           (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
4292 # define REPLAY_RESIDENCY_DISABLE              (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
4293 # define REPLAY_RESIDENCY_ENABLE               (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
4294 
4295 #define REPLAY_RESIDENCY_REVISION_MASK         (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT)
4296 # define REPLAY_RESIDENCY_REVISION_0           (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT)
4297 # define REPLAY_RESIDENCY_REVISION_1           (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT)
4298 
4299 /**
4300  * Definition of a replay_state.
4301  */
4302 enum replay_state {
4303 	REPLAY_STATE_0			= 0x0,
4304 	REPLAY_STATE_1			= 0x10,
4305 	REPLAY_STATE_1A			= 0x11,
4306 	REPLAY_STATE_2			= 0x20,
4307 	REPLAY_STATE_2A			= 0x21,
4308 	REPLAY_STATE_3			= 0x30,
4309 	REPLAY_STATE_3INIT		= 0x31,
4310 	REPLAY_STATE_4			= 0x40,
4311 	REPLAY_STATE_4A			= 0x41,
4312 	REPLAY_STATE_4B			= 0x42,
4313 	REPLAY_STATE_4C			= 0x43,
4314 	REPLAY_STATE_4D			= 0x44,
4315 	REPLAY_STATE_4E			= 0x45,
4316 	REPLAY_STATE_4B_LOCKED		= 0x4A,
4317 	REPLAY_STATE_4C_UNLOCKED	= 0x4B,
4318 	REPLAY_STATE_5			= 0x50,
4319 	REPLAY_STATE_5A			= 0x51,
4320 	REPLAY_STATE_5B			= 0x52,
4321 	REPLAY_STATE_5A_LOCKED		= 0x5A,
4322 	REPLAY_STATE_5B_UNLOCKED	= 0x5B,
4323 	REPLAY_STATE_6			= 0x60,
4324 	REPLAY_STATE_6A			= 0x61,
4325 	REPLAY_STATE_6B			= 0x62,
4326 	REPLAY_STATE_INVALID		= 0xFF,
4327 };
4328 
4329 /**
4330  * Definition of a panel replay state
4331  */
4332 enum pr_state {
4333 	PR_STATE_0									= 0x00, // State 0 steady state
4334 	// Pending SDP and Unlock before back to State 0
4335 	PR_STATE_0_PENDING_SDP_AND_UNLOCK			= 0x01,
4336 	PR_STATE_1									= 0x10, // State 1
4337 	PR_STATE_2									= 0x20, // State 2 steady state
4338 	// Pending frame transmission before transition to State 2
4339 	PR_STATE_2_PENDING_FRAME_TRANSMISSION		= 0x30,
4340 	// Active and Powered Up
4341 	PR_STATE_2_POWERED							= 0x31,
4342 	// Active and Powered Down, but need to blank HUBP after DPG_EN latch
4343 	PR_STATE_2_PENDING_HUBP_BLANK				= 0x32,
4344 	// Active and Pending Power Up
4345 	PR_STATE_2_PENDING_POWER_UP					= 0x33,
4346 	// Active and Powered Up, Pending DPG latch
4347 	PR_STATE_2_PENDING_LOCK	= 0x34,
4348 	// Active and Powered Up, Pending SDP and Unlock
4349 	PR_STATE_2_PENDING_SDP_AND_UNLOCK			= 0x35,
4350 	// Pending transmission of AS SDP for timing sync, but no rfb update
4351 	PR_STATE_2_PENDING_AS_SDP					= 0x36,
4352 	// Invalid
4353 	PR_STATE_INVALID							= 0xFF,
4354 };
4355 
4356 /**
4357  * Replay command sub-types.
4358  */
4359 enum dmub_cmd_replay_type {
4360 	/**
4361 	 * Copy driver-calculated parameters to REPLAY state.
4362 	 */
4363 	DMUB_CMD__REPLAY_COPY_SETTINGS		= 0,
4364 	/**
4365 	 * Enable REPLAY.
4366 	 */
4367 	DMUB_CMD__REPLAY_ENABLE			= 1,
4368 	/**
4369 	 * Set Replay power option.
4370 	 */
4371 	DMUB_CMD__SET_REPLAY_POWER_OPT		= 2,
4372 	/**
4373 	 * Set coasting vtotal.
4374 	 */
4375 	DMUB_CMD__REPLAY_SET_COASTING_VTOTAL	= 3,
4376 	/**
4377 	 * Set power opt and coasting vtotal.
4378 	 */
4379 	DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL	= 4,
4380 	/**
4381 	 * Set disabled iiming sync.
4382 	 */
4383 	DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED	= 5,
4384 	/**
4385 	 * Set Residency Frameupdate Timer.
4386 	 */
4387 	DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
4388 	/**
4389 	 * Set pseudo vtotal
4390 	 */
4391 	DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
4392 	/**
4393 	 * Set adaptive sync sdp enabled
4394 	 */
4395 	DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
4396 	/**
4397 	 * Set Replay General command.
4398 	 */
4399 	DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
4400 };
4401 
4402 /*
4403  * Panel Replay sub-types
4404  */
4405 enum dmub_cmd_panel_replay_type {
4406 	DMUB_CMD__PR_ENABLE = 0,
4407 	DMUB_CMD__PR_COPY_SETTINGS = 1,
4408 	DMUB_CMD__PR_UPDATE_STATE = 2,
4409 	DMUB_CMD__PR_GENERAL_CMD = 3,
4410 };
4411 
4412 enum dmub_cmd_panel_replay_state_update_subtype {
4413 	PR_STATE_UPDATE_COASTING_VTOTAL = 0x1,
4414 	PR_STATE_UPDATE_SYNC_MODE = 0x2,
4415 	PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3,
4416 };
4417 
4418 enum dmub_cmd_panel_replay_general_subtype {
4419 	PR_GENERAL_CMD_DEBUG_OPTION = 0x1,
4420 };
4421 
4422 /**
4423  * Replay general command sub-types.
4424  */
4425 enum dmub_cmd_replay_general_subtype {
4426 	REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,
4427 	/**
4428 	 * TODO: For backward compatible, allow new command only.
4429 	 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,
4430 	 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,
4431 	 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,
4432 	 */
4433 	REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
4434 	REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
4435 	REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS,
4436 	REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE,
4437 	REPLAY_GENERAL_CMD_VIDEO_CONFERENCING,
4438 	REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC,
4439 	REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE,
4440 	REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT,
4441 };
4442 
4443 struct dmub_alpm_auxless_data {
4444 	uint16_t lfps_setup_ns;
4445 	uint16_t lfps_period_ns;
4446 	uint16_t lfps_silence_ns;
4447 	uint16_t lfps_t1_t2_override_us;
4448 	short lfps_t1_t2_offset_us;
4449 	uint8_t lttpr_count;
4450 	/*
4451 	 * Padding to align structure to 4 byte boundary.
4452 	 */
4453 	uint8_t pad[1];
4454 };
4455 
4456 /**
4457  * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4458  */
4459 struct dmub_cmd_replay_copy_settings_data {
4460 	/**
4461 	 * Flags that can be set by driver to change some replay behaviour.
4462 	 */
4463 	union replay_debug_flags debug;
4464 
4465 	/**
4466 	 * @flags: Flags used to determine feature functionality.
4467 	 */
4468 	union replay_hw_flags flags;
4469 
4470 	/**
4471 	 * DPP HW instance.
4472 	 */
4473 	uint8_t dpp_inst;
4474 	/**
4475 	 * OTG HW instance.
4476 	 */
4477 	uint8_t otg_inst;
4478 	/**
4479 	 * DIG FE HW instance.
4480 	 */
4481 	uint8_t digfe_inst;
4482 	/**
4483 	 * DIG BE HW instance.
4484 	 */
4485 	uint8_t digbe_inst;
4486 	/**
4487 	 * AUX HW instance.
4488 	 */
4489 	uint8_t aux_inst;
4490 	/**
4491 	 * Panel Instance.
4492 	 * Panel isntance to identify which psr_state to use
4493 	 * Currently the support is only for 0 or 1
4494 	 */
4495 	uint8_t panel_inst;
4496 	/**
4497 	 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
4498 	 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
4499 	 */
4500 	uint8_t pixel_deviation_per_line;
4501 	/**
4502 	 * @max_deviation_line: The max number of deviation line that can keep the timing
4503 	 * synchronized between the Source and Sink during Replay normal sleep mode.
4504 	 */
4505 	uint8_t max_deviation_line;
4506 	/**
4507 	 * Length of each horizontal line in ns.
4508 	 */
4509 	uint32_t line_time_in_ns;
4510 	/**
4511 	 * PHY instance.
4512 	 */
4513 	uint8_t dpphy_inst;
4514 	/**
4515 	 * Determines if SMU optimzations are enabled/disabled.
4516 	 */
4517 	uint8_t smu_optimizations_en;
4518 	/**
4519 	 * Determines if timing sync are enabled/disabled.
4520 	 */
4521 	uint8_t replay_timing_sync_supported;
4522 	/*
4523 	 * Use FSM state for Replay power up/down
4524 	 */
4525 	uint8_t use_phy_fsm;
4526 	/**
4527 	 * Use for AUX-less ALPM LFPS wake operation
4528 	 */
4529 	struct dmub_alpm_auxless_data auxless_alpm_data;
4530 	/**
4531 	 * @hpo_stream_enc_inst: HPO stream encoder instance
4532 	 */
4533 	uint8_t hpo_stream_enc_inst;
4534 	/**
4535 	 * @hpo_link_enc_inst: HPO link encoder instance
4536 	 */
4537 	uint8_t hpo_link_enc_inst;
4538 	/**
4539 	 * Determines if fast resync in ultra sleep mode is enabled/disabled.
4540 	 */
4541 	uint8_t replay_support_fast_resync_in_ultra_sleep_mode;
4542 	/**
4543 	 * @pad: Align structure to 4 byte boundary.
4544 	 */
4545 	uint8_t pad[1];
4546 };
4547 
4548 
4549 /**
4550  * Replay versions.
4551  */
4552 enum replay_version {
4553 	/**
4554 	 * FreeSync Replay
4555 	 */
4556 	REPLAY_VERSION_FREESYNC_REPLAY	= 0,
4557 	/**
4558 	 * Panel Replay
4559 	 */
4560 	REPLAY_VERSION_PANEL_REPLAY		= 1,
4561 	/**
4562 	 * Replay not supported.
4563 	 */
4564 	REPLAY_VERSION_UNSUPPORTED		= 0xFF,
4565 };
4566 
4567 /**
4568  * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4569  */
4570 struct dmub_rb_cmd_replay_copy_settings {
4571 	/**
4572 	 * Command header.
4573 	 */
4574 	struct dmub_cmd_header header;
4575 	/**
4576 	 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4577 	 */
4578 	struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
4579 };
4580 
4581 /**
4582  * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
4583  */
4584 enum replay_enable {
4585 	/**
4586 	 * Disable REPLAY.
4587 	 */
4588 	REPLAY_DISABLE				= 0,
4589 	/**
4590 	 * Enable REPLAY.
4591 	 */
4592 	REPLAY_ENABLE				= 1,
4593 };
4594 
4595 /**
4596  * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command.
4597  */
4598 struct dmub_rb_cmd_smart_power_oled_enable_data {
4599 	/**
4600 	 * SMART_POWER_OLED enable or disable.
4601 	 */
4602 	uint8_t enable;
4603 	/**
4604 	 * Panel Instance.
4605 	 * Panel isntance to identify which replay_state to use
4606 	 * Currently the support is only for 0 or 1
4607 	 */
4608 	uint8_t panel_inst;
4609 
4610 	uint16_t peak_nits;
4611 	/**
4612 	 * OTG HW instance.
4613 	 */
4614 	uint8_t otg_inst;
4615 	/**
4616 	 * DIG FE HW instance.
4617 	 */
4618 	uint8_t digfe_inst;
4619 	/**
4620 	 * DIG BE HW instance.
4621 	 */
4622 	uint8_t digbe_inst;
4623 	uint8_t debugcontrol;
4624 	/*
4625 	 * vertical interrupt trigger line
4626 	 */
4627 	uint32_t triggerline;
4628 
4629 	uint16_t fixed_max_cll;
4630 
4631 	uint8_t pad[2];
4632 };
4633 
4634 /**
4635  * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
4636  */
4637 struct dmub_rb_cmd_replay_enable_data {
4638 	/**
4639 	 * Replay enable or disable.
4640 	 */
4641 	uint8_t enable;
4642 	/**
4643 	 * Panel Instance.
4644 	 * Panel isntance to identify which replay_state to use
4645 	 * Currently the support is only for 0 or 1
4646 	 */
4647 	uint8_t panel_inst;
4648 	/**
4649 	 * Phy state to enter.
4650 	 * Values to use are defined in dmub_phy_fsm_state
4651 	 */
4652 	uint8_t phy_fsm_state;
4653 	/**
4654 	 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
4655 	 * Set this using enum phy_link_rate.
4656 	 * This does not support HDMI/DP2 for now.
4657 	 */
4658 	uint8_t phy_rate;
4659 	/**
4660 	 * @hpo_stream_enc_inst: HPO stream encoder instance
4661 	 */
4662 	uint8_t hpo_stream_enc_inst;
4663 	/**
4664 	 * @hpo_link_enc_inst: HPO link encoder instance
4665 	 */
4666 	uint8_t hpo_link_enc_inst;
4667 	/**
4668 	 * @pad: Align structure to 4 byte boundary.
4669 	 */
4670 	uint8_t pad[2];
4671 };
4672 
4673 /**
4674  * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4675  * Replay enable/disable is controlled using action in data.
4676  */
4677 struct dmub_rb_cmd_replay_enable {
4678 	/**
4679 	 * Command header.
4680 	 */
4681 	struct dmub_cmd_header header;
4682 
4683 	struct dmub_rb_cmd_replay_enable_data data;
4684 };
4685 
4686 /**
4687  * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4688  */
4689 struct dmub_cmd_replay_set_power_opt_data {
4690 	/**
4691 	 * Panel Instance.
4692 	 * Panel isntance to identify which replay_state to use
4693 	 * Currently the support is only for 0 or 1
4694 	 */
4695 	uint8_t panel_inst;
4696 	/**
4697 	 * Explicit padding to 4 byte boundary.
4698 	 */
4699 	uint8_t pad[3];
4700 	/**
4701 	 * REPLAY power option
4702 	 */
4703 	uint32_t power_opt;
4704 };
4705 
4706 /**
4707  * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4708  */
4709 struct dmub_cmd_replay_set_timing_sync_data {
4710 	/**
4711 	 * Panel Instance.
4712 	 * Panel isntance to identify which replay_state to use
4713 	 * Currently the support is only for 0 or 1
4714 	 */
4715 	uint8_t panel_inst;
4716 	/**
4717 	 * REPLAY set_timing_sync
4718 	 */
4719 	uint8_t timing_sync_supported;
4720 	/**
4721 	 * Explicit padding to 4 byte boundary.
4722 	 */
4723 	uint8_t pad[2];
4724 };
4725 
4726 /**
4727  * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4728  */
4729 struct dmub_cmd_replay_set_pseudo_vtotal {
4730 	/**
4731 	 * Panel Instance.
4732 	 * Panel isntance to identify which replay_state to use
4733 	 * Currently the support is only for 0 or 1
4734 	 */
4735 	uint8_t panel_inst;
4736 	/**
4737 	 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal
4738 	 */
4739 	uint16_t vtotal;
4740 	/**
4741 	 * Explicit padding to 4 byte boundary.
4742 	 */
4743 	uint8_t pad;
4744 };
4745 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
4746 	/**
4747 	 * Panel Instance.
4748 	 * Panel isntance to identify which replay_state to use
4749 	 * Currently the support is only for 0 or 1
4750 	 */
4751 	uint8_t panel_inst;
4752 	/**
4753 	 * enabled: set adaptive sync sdp enabled
4754 	 */
4755 	uint8_t force_disabled;
4756 
4757 	uint8_t pad[2];
4758 };
4759 struct dmub_cmd_replay_set_general_cmd_data {
4760 	/**
4761 	 * Panel Instance.
4762 	 * Panel isntance to identify which replay_state to use
4763 	 * Currently the support is only for 0 or 1
4764 	 */
4765 	uint8_t panel_inst;
4766 	/**
4767 	 * subtype: replay general cmd sub type
4768 	 */
4769 	uint8_t subtype;
4770 
4771 	uint8_t pad[2];
4772 	/**
4773 	 * config data with param1 and param2
4774 	 */
4775 	uint32_t param1;
4776 
4777 	uint32_t param2;
4778 };
4779 
4780 /**
4781  * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4782  */
4783 struct dmub_rb_cmd_replay_set_power_opt {
4784 	/**
4785 	 * Command header.
4786 	 */
4787 	struct dmub_cmd_header header;
4788 	/**
4789 	 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4790 	 */
4791 	struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
4792 };
4793 
4794 /**
4795  * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4796  */
4797 struct dmub_cmd_replay_set_coasting_vtotal_data {
4798 	/**
4799 	 * 16-bit value dicated by driver that indicates the coasting vtotal.
4800 	 */
4801 	uint16_t coasting_vtotal;
4802 	/**
4803 	 * REPLAY control version.
4804 	 */
4805 	uint8_t cmd_version;
4806 	/**
4807 	 * Panel Instance.
4808 	 * Panel isntance to identify which replay_state to use
4809 	 * Currently the support is only for 0 or 1
4810 	 */
4811 	uint8_t panel_inst;
4812 	/**
4813 	 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
4814 	 */
4815 	uint16_t coasting_vtotal_high;
4816 	/**
4817 	 * frame skip number.
4818 	 */
4819 	uint16_t frame_skip_number;
4820 };
4821 
4822 /**
4823  * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4824  */
4825 struct dmub_rb_cmd_replay_set_coasting_vtotal {
4826 	/**
4827 	 * Command header.
4828 	 */
4829 	struct dmub_cmd_header header;
4830 	/**
4831 	 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4832 	 */
4833 	struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
4834 };
4835 
4836 /**
4837  * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
4838  */
4839 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
4840 	/**
4841 	 * Command header.
4842 	 */
4843 	struct dmub_cmd_header header;
4844 	/**
4845 	 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4846 	 */
4847 	struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
4848 	/**
4849 	 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4850 	 */
4851 	struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
4852 };
4853 
4854 /**
4855  * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4856  */
4857 struct dmub_rb_cmd_replay_set_timing_sync {
4858 	/**
4859 	 * Command header.
4860 	 */
4861 	struct dmub_cmd_header header;
4862 	/**
4863 	 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4864 	 */
4865 	struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
4866 };
4867 
4868 /**
4869  * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4870  */
4871 struct dmub_rb_cmd_replay_set_pseudo_vtotal {
4872 	/**
4873 	 * Command header.
4874 	 */
4875 	struct dmub_cmd_header header;
4876 	/**
4877 	 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4878 	 */
4879 	struct dmub_cmd_replay_set_pseudo_vtotal data;
4880 };
4881 
4882 /**
4883  * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
4884  */
4885 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
4886 	/**
4887 	 * Command header.
4888 	 */
4889 	struct dmub_cmd_header header;
4890 	/**
4891 	 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
4892 	 */
4893 	struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
4894 };
4895 
4896 /**
4897  * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
4898  */
4899 struct dmub_rb_cmd_replay_set_general_cmd {
4900 	/**
4901 	 * Command header.
4902 	 */
4903 	struct dmub_cmd_header header;
4904 	/**
4905 	 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
4906 	 */
4907 	struct dmub_cmd_replay_set_general_cmd_data data;
4908 };
4909 
4910 /**
4911  * Data passed from driver to FW in  DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
4912  */
4913 struct dmub_cmd_replay_frameupdate_timer_data {
4914 	/**
4915 	 * Panel Instance.
4916 	 * Panel isntance to identify which replay_state to use
4917 	 * Currently the support is only for 0 or 1
4918 	 */
4919 	uint8_t panel_inst;
4920 	/**
4921 	 * Replay Frameupdate Timer Enable or not
4922 	 */
4923 	uint8_t enable;
4924 	/**
4925 	 * REPLAY force reflash frame update number
4926 	 */
4927 	uint16_t frameupdate_count;
4928 };
4929 /**
4930  * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
4931  */
4932 struct dmub_rb_cmd_replay_set_frameupdate_timer {
4933 	/**
4934 	 * Command header.
4935 	 */
4936 	struct dmub_cmd_header header;
4937 	/**
4938 	 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4939 	 */
4940 	struct dmub_cmd_replay_frameupdate_timer_data data;
4941 };
4942 
4943 /**
4944  * Definition union of replay command set
4945  */
4946 union dmub_replay_cmd_set {
4947 	/**
4948 	 * Panel Instance.
4949 	 * Panel isntance to identify which replay_state to use
4950 	 * Currently the support is only for 0 or 1
4951 	 */
4952 	uint8_t panel_inst;
4953 	/**
4954 	 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.
4955 	 */
4956 	struct dmub_cmd_replay_set_timing_sync_data sync_data;
4957 	/**
4958 	 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.
4959 	 */
4960 	struct dmub_cmd_replay_frameupdate_timer_data timer_data;
4961 	/**
4962 	 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
4963 	 */
4964 	struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
4965 	/**
4966 	 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
4967 	 */
4968 	struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
4969 	/**
4970 	 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.
4971 	 */
4972 	struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
4973 };
4974 
4975 /**
4976  * IHC command sub-types.
4977  */
4978 enum dmub_cmd_ihc_type {
4979 	/**
4980 	 * Set DIG HDCP interrupt destination.
4981 	 */
4982 	DMUB_CMD__IHC_SET_DIG_HDCP_INTERRUPT_DEST = 0,
4983 };
4984 
4985 /**
4986  * Data passed from driver to FW in a DMUB_CMD__IHC command.
4987  */
4988 struct dmub_cmd_ihc_data {
4989 	/**
4990 	 * DIG engine ID (0-3).
4991 	 */
4992 	uint8_t dig_id;
4993 	/**
4994 	 * 1 = route to DMU, 0 = route to CPU.
4995 	 */
4996 	uint8_t to_dmu : 1;
4997 	/**
4998 	 * Reserved bits.
4999 	 */
5000 	uint8_t reserved : 7;
5001 	/**
5002 	 * Padding.
5003 	 */
5004 	uint8_t pad[2];
5005 };
5006 
5007 /**
5008  * Definition of a DMUB_CMD__IHC command.
5009  */
5010 struct dmub_rb_cmd_ihc {
5011 	/**
5012 	 * Command header.
5013 	 */
5014 	struct dmub_cmd_header header;
5015 	/**
5016 	 * IHC command data.
5017 	 */
5018 	struct dmub_cmd_ihc_data data;
5019 };
5020 
5021 /**
5022  * SMART POWER OLED command sub-types.
5023  */
5024 enum dmub_cmd_smart_power_oled_type {
5025 
5026 	/**
5027 	 * Enable/Disable SMART_POWER_OLED.
5028 	 */
5029 	DMUB_CMD__SMART_POWER_OLED_ENABLE = 1,
5030 	/**
5031 	 * Get current MaxCLL value if SMART POWER OLED is enabled.
5032 	 */
5033 	DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2,
5034 };
5035 
5036 /**
5037  * Definition of a DMUB_CMD__SMART_POWER_OLED command.
5038  */
5039 struct dmub_rb_cmd_smart_power_oled_enable {
5040 	/**
5041 	 * Command header.
5042 	 */
5043 	struct dmub_cmd_header header;
5044 
5045 	struct dmub_rb_cmd_smart_power_oled_enable_data data;
5046 };
5047 
5048 struct dmub_cmd_smart_power_oled_getmaxcll_input {
5049 	uint8_t panel_inst;
5050 	uint8_t pad[3];
5051 };
5052 
5053 struct dmub_cmd_smart_power_oled_getmaxcll_output {
5054 	uint16_t current_max_cll;
5055 	uint8_t pad[2];
5056 };
5057 
5058 /**
5059  * Definition of a DMUB_CMD__SMART_POWER_OLED command.
5060  */
5061 struct dmub_rb_cmd_smart_power_oled_getmaxcll {
5062 	struct dmub_cmd_header header; /**< Command header */
5063 	/**
5064 	 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.
5065 	 */
5066 	union dmub_cmd_smart_power_oled_getmaxcll_data {
5067 		struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */
5068 		struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */
5069 		uint32_t output_raw; /**< Raw data output */
5070 	} data;
5071 };
5072 
5073 /**
5074  * Set of HW components that can be locked.
5075  *
5076  * Note: If updating with more HW components, fields
5077  * in dmub_inbox0_cmd_lock_hw must be updated to match.
5078  */
5079 union dmub_hw_lock_flags {
5080 	/**
5081 	 * Set of HW components that can be locked.
5082 	 */
5083 	struct {
5084 		/**
5085 		 * Lock/unlock OTG master update lock.
5086 		 */
5087 		uint8_t lock_pipe   : 1;
5088 		/**
5089 		 * Lock/unlock cursor.
5090 		 */
5091 		uint8_t lock_cursor : 1;
5092 		/**
5093 		 * Lock/unlock global update lock.
5094 		 */
5095 		uint8_t lock_dig    : 1;
5096 		/**
5097 		 * Triple buffer lock requires additional hw programming to usual OTG master lock.
5098 		 */
5099 		uint8_t triple_buffer_lock : 1;
5100 	} bits;
5101 
5102 	/**
5103 	 * Union for HW Lock flags.
5104 	 */
5105 	uint8_t u8All;
5106 };
5107 
5108 /**
5109  * Instances of HW to be locked.
5110  *
5111  * Note: If updating with more HW components, fields
5112  * in dmub_inbox0_cmd_lock_hw must be updated to match.
5113  */
5114 struct dmub_hw_lock_inst_flags {
5115 	/**
5116 	 * OTG HW instance for OTG master update lock.
5117 	 */
5118 	uint8_t otg_inst;
5119 	/**
5120 	 * OPP instance for cursor lock.
5121 	 */
5122 	uint8_t opp_inst;
5123 	/**
5124 	 * OTG HW instance for global update lock.
5125 	 * TODO: Remove, and re-use otg_inst.
5126 	 */
5127 	uint8_t dig_inst;
5128 	/**
5129 	 * Explicit pad to 4 byte boundary.
5130 	 */
5131 	uint8_t pad;
5132 };
5133 
5134 /**
5135  * Clients that can acquire the HW Lock Manager.
5136  *
5137  * Note: If updating with more clients, fields in
5138  * dmub_inbox0_cmd_lock_hw must be updated to match.
5139  */
5140 enum hw_lock_client {
5141 	/**
5142 	 * Driver is the client of HW Lock Manager.
5143 	 */
5144 	HW_LOCK_CLIENT_DRIVER = 0,
5145 	/**
5146 	 * PSR SU is the client of HW Lock Manager.
5147 	 */
5148 	HW_LOCK_CLIENT_PSR_SU		= 1,
5149 	HW_LOCK_CLIENT_SUBVP = 3,
5150 	/**
5151 	 * Replay is the client of HW Lock Manager.
5152 	 */
5153 	HW_LOCK_CLIENT_REPLAY		= 4,
5154 	HW_LOCK_CLIENT_FAMS2 = 5,
5155 	HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6,
5156 	/**
5157 	 * Invalid client.
5158 	 */
5159 	HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
5160 };
5161 
5162 /**
5163  * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
5164  */
5165 struct dmub_cmd_lock_hw_data {
5166 	/**
5167 	 * Specifies the client accessing HW Lock Manager.
5168 	 */
5169 	enum hw_lock_client client;
5170 	/**
5171 	 * HW instances to be locked.
5172 	 */
5173 	struct dmub_hw_lock_inst_flags inst_flags;
5174 	/**
5175 	 * Which components to be locked.
5176 	 */
5177 	union dmub_hw_lock_flags hw_locks;
5178 	/**
5179 	 * Specifies lock/unlock.
5180 	 */
5181 	uint8_t lock;
5182 	/**
5183 	 * HW can be unlocked separately from releasing the HW Lock Mgr.
5184 	 * This flag is set if the client wishes to release the object.
5185 	 */
5186 	uint8_t should_release;
5187 	/**
5188 	 * Explicit padding to 4 byte boundary.
5189 	 */
5190 	uint8_t pad;
5191 };
5192 
5193 /**
5194  * Definition of a DMUB_CMD__HW_LOCK command.
5195  * Command is used by driver and FW.
5196  */
5197 struct dmub_rb_cmd_lock_hw {
5198 	/**
5199 	 * Command header.
5200 	 */
5201 	struct dmub_cmd_header header;
5202 	/**
5203 	 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
5204 	 */
5205 	struct dmub_cmd_lock_hw_data lock_hw_data;
5206 };
5207 
5208 /**
5209  * ABM command sub-types.
5210  */
5211 enum dmub_cmd_abm_type {
5212 	/**
5213 	 * Initialize parameters for ABM algorithm.
5214 	 * Data is passed through an indirect buffer.
5215 	 */
5216 	DMUB_CMD__ABM_INIT_CONFIG	= 0,
5217 	/**
5218 	 * Set OTG and panel HW instance.
5219 	 */
5220 	DMUB_CMD__ABM_SET_PIPE		= 1,
5221 	/**
5222 	 * Set user requested backklight level.
5223 	 */
5224 	DMUB_CMD__ABM_SET_BACKLIGHT	= 2,
5225 	/**
5226 	 * Set ABM operating/aggression level.
5227 	 */
5228 	DMUB_CMD__ABM_SET_LEVEL		= 3,
5229 	/**
5230 	 * Set ambient light level.
5231 	 */
5232 	DMUB_CMD__ABM_SET_AMBIENT_LEVEL	= 4,
5233 	/**
5234 	 * Enable/disable fractional duty cycle for backlight PWM.
5235 	 */
5236 	DMUB_CMD__ABM_SET_PWM_FRAC	= 5,
5237 
5238 	/**
5239 	 * unregister vertical interrupt after steady state is reached
5240 	 */
5241 	DMUB_CMD__ABM_PAUSE	= 6,
5242 
5243 	/**
5244 	 * Save and Restore ABM state. On save we save parameters, and
5245 	 * on restore we update state with passed in data.
5246 	 */
5247 	DMUB_CMD__ABM_SAVE_RESTORE	= 7,
5248 
5249 	/**
5250 	 * Query ABM caps.
5251 	 */
5252 	DMUB_CMD__ABM_QUERY_CAPS	= 8,
5253 
5254 	/**
5255 	 * Set ABM Events
5256 	 */
5257 	DMUB_CMD__ABM_SET_EVENT	= 9,
5258 
5259 	/**
5260 	 * Get the current ACE curve.
5261 	 */
5262 	DMUB_CMD__ABM_GET_ACE_CURVE = 10,
5263 
5264 	/**
5265 	 * Get current histogram data
5266 	 */
5267 	DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11,
5268 };
5269 
5270 /**
5271  * LSDMA command sub-types.
5272  */
5273 enum dmub_cmd_lsdma_type {
5274 	/**
5275 	 * Initialize parameters for LSDMA.
5276 	 * Ring buffer is mapped to the ring buffer
5277 	 */
5278 	DMUB_CMD__LSDMA_INIT_CONFIG	= 0,
5279 	/**
5280 	 * LSDMA copies data from source to destination linearly
5281 	 */
5282 	DMUB_CMD__LSDMA_LINEAR_COPY = 1,
5283 	/**
5284 	* LSDMA copies data from source to destination linearly in sub window
5285 	*/
5286 	DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2,
5287 	/**
5288 	 * Send the tiled-to-tiled copy command
5289 	 */
5290 	DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3,
5291 	/**
5292 	 * Send the poll reg write command
5293 	 */
5294 	DMUB_CMD__LSDMA_POLL_REG_WRITE = 4,
5295 	/**
5296 	 * Send the pio copy command
5297 	 */
5298 	DMUB_CMD__LSDMA_PIO_COPY = 5,
5299 	/**
5300 	 * Send the pio constfill command
5301 	 */
5302 	DMUB_CMD__LSDMA_PIO_CONSTFILL = 6,
5303 };
5304 
5305 struct abm_ace_curve {
5306 	/**
5307 	 * @offsets: ACE curve offsets.
5308 	 */
5309 	uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];
5310 
5311 	/**
5312 	 * @thresholds: ACE curve thresholds.
5313 	 */
5314 	uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];
5315 
5316 	/**
5317 	 * @slopes: ACE curve slopes.
5318 	 */
5319 	uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];
5320 };
5321 
5322 struct fixed_pt_format {
5323 	/**
5324 	 * @sign_bit: Indicates whether one bit is reserved for the sign.
5325 	 */
5326 	bool sign_bit;
5327 
5328 	/**
5329 	 * @num_int_bits: Number of bits used for integer part.
5330 	 */
5331 	uint8_t num_int_bits;
5332 
5333 	/**
5334 	 * @num_frac_bits: Number of bits used for fractional part.
5335 	 */
5336 	uint8_t num_frac_bits;
5337 
5338 	/**
5339 	 * @pad: Explicit padding to 4 byte boundary.
5340 	 */
5341 	uint8_t pad;
5342 };
5343 
5344 struct abm_caps {
5345 	/**
5346 	 * @num_hg_bins: Number of histogram bins.
5347 	 */
5348 	uint8_t num_hg_bins;
5349 
5350 	/**
5351 	 * @num_ace_segments: Number of ACE curve segments.
5352 	 */
5353 	uint8_t num_ace_segments;
5354 
5355 	/**
5356 	 * @pad: Explicit padding to 4 byte boundary.
5357 	 */
5358 	uint8_t pad[2];
5359 
5360 	/**
5361 	 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.
5362 	 */
5363 	struct fixed_pt_format ace_thresholds_format;
5364 
5365 	/**
5366 	 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.
5367 	 */
5368 	struct fixed_pt_format ace_offsets_format;
5369 
5370 	/**
5371 	 * @ace_slopes_format: Format of the ACE slopes.
5372 	 */
5373 	struct fixed_pt_format ace_slopes_format;
5374 };
5375 
5376 /**
5377  * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
5378  * Requirements:
5379  *  - Padded explicitly to 32-bit boundary.
5380  *  - Must ensure this structure matches the one on driver-side,
5381  *    otherwise it won't be aligned.
5382  */
5383 struct abm_config_table {
5384 	/**
5385 	 * Gamma curve thresholds, used for crgb conversion.
5386 	 */
5387 	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                 // 0B
5388 	/**
5389 	 * Gamma curve offsets, used for crgb conversion.
5390 	 */
5391 	uint16_t crgb_offset[NUM_POWER_FN_SEGS];                 // 16B
5392 	/**
5393 	 * Gamma curve slopes, used for crgb conversion.
5394 	 */
5395 	uint16_t crgb_slope[NUM_POWER_FN_SEGS];                  // 32B
5396 	/**
5397 	 * Custom backlight curve thresholds.
5398 	 */
5399 	uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];        // 48B
5400 	/**
5401 	 * Custom backlight curve offsets.
5402 	 */
5403 	uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];           // 78B
5404 	/**
5405 	 * Ambient light thresholds.
5406 	 */
5407 	uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL];         // 112B
5408 	/**
5409 	 * Minimum programmable backlight.
5410 	 */
5411 	uint16_t min_abm_backlight;                              // 122B
5412 	/**
5413 	 * Minimum reduction values.
5414 	 */
5415 	uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 124B
5416 	/**
5417 	 * Maximum reduction values.
5418 	 */
5419 	uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 144B
5420 	/**
5421 	 * Bright positive gain.
5422 	 */
5423 	uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
5424 	/**
5425 	 * Dark negative gain.
5426 	 */
5427 	uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];   // 184B
5428 	/**
5429 	 * Hybrid factor.
5430 	 */
5431 	uint8_t hybrid_factor[NUM_AGGR_LEVEL];                   // 204B
5432 	/**
5433 	 * Contrast factor.
5434 	 */
5435 	uint8_t contrast_factor[NUM_AGGR_LEVEL];                 // 208B
5436 	/**
5437 	 * Deviation gain.
5438 	 */
5439 	uint8_t deviation_gain[NUM_AGGR_LEVEL];                  // 212B
5440 	/**
5441 	 * Minimum knee.
5442 	 */
5443 	uint8_t min_knee[NUM_AGGR_LEVEL];                        // 216B
5444 	/**
5445 	 * Maximum knee.
5446 	 */
5447 	uint8_t max_knee[NUM_AGGR_LEVEL];                        // 220B
5448 	/**
5449 	 * Unused.
5450 	 */
5451 	uint8_t iir_curve[NUM_AMBI_LEVEL];                       // 224B
5452 	/**
5453 	 * Explicit padding to 4 byte boundary.
5454 	 */
5455 	uint8_t pad3[3];                                         // 229B
5456 	/**
5457 	 * Backlight ramp reduction.
5458 	 */
5459 	uint16_t blRampReduction[NUM_AGGR_LEVEL];                // 232B
5460 	/**
5461 	 * Backlight ramp start.
5462 	 */
5463 	uint16_t blRampStart[NUM_AGGR_LEVEL];                    // 240B
5464 };
5465 
5466 /**
5467  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
5468  */
5469 struct dmub_cmd_abm_set_pipe_data {
5470 	/**
5471 	 * OTG HW instance.
5472 	 */
5473 	uint8_t otg_inst;
5474 
5475 	/**
5476 	 * Panel Control HW instance.
5477 	 */
5478 	uint8_t panel_inst;
5479 
5480 	/**
5481 	 * Controls how ABM will interpret a set pipe or set level command.
5482 	 */
5483 	uint8_t set_pipe_option;
5484 
5485 	/**
5486 	 * Unused.
5487 	 * TODO: Remove.
5488 	 */
5489 	uint8_t ramping_boundary;
5490 
5491 	/**
5492 	 * PwrSeq HW Instance.
5493 	 */
5494 	uint8_t pwrseq_inst;
5495 
5496 	/**
5497 	 * Explicit padding to 4 byte boundary.
5498 	 */
5499 	uint8_t pad[3];
5500 };
5501 
5502 /**
5503  * Definition of a DMUB_CMD__ABM_SET_PIPE command.
5504  */
5505 struct dmub_rb_cmd_abm_set_pipe {
5506 	/**
5507 	 * Command header.
5508 	 */
5509 	struct dmub_cmd_header header;
5510 
5511 	/**
5512 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
5513 	 */
5514 	struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
5515 };
5516 
5517 /**
5518  * Type of backlight control method to be used by ABM module
5519  */
5520 enum dmub_backlight_control_type {
5521 	/**
5522 	 * PWM Backlight control
5523 	 */
5524 	DMU_BACKLIGHT_CONTROL_PWM = 0,
5525 	/**
5526 	 * VESA Aux-based backlight control
5527 	 */
5528 	DMU_BACKLIGHT_CONTROL_VESA_AUX = 1,
5529 	/**
5530 	 * AMD DPCD Aux-based backlight control
5531 	 */
5532 	DMU_BACKLIGHT_CONTROL_AMD_AUX = 2,
5533 };
5534 
5535 /**
5536  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
5537  */
5538 struct dmub_cmd_abm_set_backlight_data {
5539 	/**
5540 	 * Number of frames to ramp to backlight user level.
5541 	 */
5542 	uint32_t frame_ramp;
5543 
5544 	/**
5545 	 * Requested backlight level from user.
5546 	 */
5547 	uint32_t backlight_user_level;
5548 
5549 	/**
5550 	 * ABM control version.
5551 	 */
5552 	uint8_t version;
5553 
5554 	/**
5555 	 * Panel Control HW instance mask.
5556 	 * Bit 0 is Panel Control HW instance 0.
5557 	 * Bit 1 is Panel Control HW instance 1.
5558 	 */
5559 	uint8_t panel_mask;
5560 
5561 	/**
5562 	 * AUX HW Instance.
5563 	 */
5564 	uint8_t aux_inst;
5565 
5566 	/**
5567 	 * Explicit padding to 4 byte boundary.
5568 	 */
5569 	uint8_t pad[1];
5570 
5571 	/**
5572 	 * Backlight control type.
5573 	 * Value 0 is PWM backlight control.
5574 	 * Value 1 is VAUX backlight control.
5575 	 * Value 2 is AMD DPCD AUX backlight control.
5576 	 */
5577 	enum dmub_backlight_control_type backlight_control_type;
5578 
5579 	/**
5580 	 * Minimum luminance in nits.
5581 	 */
5582 	uint32_t min_luminance;
5583 
5584 	/**
5585 	 * Maximum luminance in nits.
5586 	 */
5587 	uint32_t max_luminance;
5588 
5589 	/**
5590 	 * Minimum backlight in pwm.
5591 	 */
5592 	uint32_t min_backlight_pwm;
5593 
5594 	/**
5595 	 * Maximum backlight in pwm.
5596 	 */
5597 	uint32_t max_backlight_pwm;
5598 };
5599 
5600 /**
5601  * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
5602  */
5603 struct dmub_rb_cmd_abm_set_backlight {
5604 	/**
5605 	 * Command header.
5606 	 */
5607 	struct dmub_cmd_header header;
5608 
5609 	/**
5610 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
5611 	 */
5612 	struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
5613 };
5614 
5615 /**
5616  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
5617  */
5618 struct dmub_cmd_abm_set_level_data {
5619 	/**
5620 	 * Set current ABM operating/aggression level.
5621 	 */
5622 	uint32_t level;
5623 
5624 	/**
5625 	 * ABM control version.
5626 	 */
5627 	uint8_t version;
5628 
5629 	/**
5630 	 * Panel Control HW instance mask.
5631 	 * Bit 0 is Panel Control HW instance 0.
5632 	 * Bit 1 is Panel Control HW instance 1.
5633 	 */
5634 	uint8_t panel_mask;
5635 
5636 	/**
5637 	 * Explicit padding to 4 byte boundary.
5638 	 */
5639 	uint8_t pad[2];
5640 };
5641 
5642 /**
5643  * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
5644  */
5645 struct dmub_rb_cmd_abm_set_level {
5646 	/**
5647 	 * Command header.
5648 	 */
5649 	struct dmub_cmd_header header;
5650 
5651 	/**
5652 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
5653 	 */
5654 	struct dmub_cmd_abm_set_level_data abm_set_level_data;
5655 };
5656 
5657 /**
5658  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5659  */
5660 struct dmub_cmd_abm_set_ambient_level_data {
5661 	/**
5662 	 * Ambient light sensor reading from OS.
5663 	 */
5664 	uint32_t ambient_lux;
5665 
5666 	/**
5667 	 * ABM control version.
5668 	 */
5669 	uint8_t version;
5670 
5671 	/**
5672 	 * Panel Control HW instance mask.
5673 	 * Bit 0 is Panel Control HW instance 0.
5674 	 * Bit 1 is Panel Control HW instance 1.
5675 	 */
5676 	uint8_t panel_mask;
5677 
5678 	/**
5679 	 * Explicit padding to 4 byte boundary.
5680 	 */
5681 	uint8_t pad[2];
5682 };
5683 
5684 /**
5685  * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5686  */
5687 struct dmub_rb_cmd_abm_set_ambient_level {
5688 	/**
5689 	 * Command header.
5690 	 */
5691 	struct dmub_cmd_header header;
5692 
5693 	/**
5694 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5695 	 */
5696 	struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
5697 };
5698 
5699 /**
5700  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
5701  */
5702 struct dmub_cmd_abm_set_pwm_frac_data {
5703 	/**
5704 	 * Enable/disable fractional duty cycle for backlight PWM.
5705 	 * TODO: Convert to uint8_t.
5706 	 */
5707 	uint32_t fractional_pwm;
5708 
5709 	/**
5710 	 * ABM control version.
5711 	 */
5712 	uint8_t version;
5713 
5714 	/**
5715 	 * Panel Control HW instance mask.
5716 	 * Bit 0 is Panel Control HW instance 0.
5717 	 * Bit 1 is Panel Control HW instance 1.
5718 	 */
5719 	uint8_t panel_mask;
5720 
5721 	/**
5722 	 * Explicit padding to 4 byte boundary.
5723 	 */
5724 	uint8_t pad[2];
5725 };
5726 
5727 /**
5728  * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
5729  */
5730 struct dmub_rb_cmd_abm_set_pwm_frac {
5731 	/**
5732 	 * Command header.
5733 	 */
5734 	struct dmub_cmd_header header;
5735 
5736 	/**
5737 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
5738 	 */
5739 	struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
5740 };
5741 
5742 /**
5743  * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
5744  */
5745 struct dmub_cmd_abm_init_config_data {
5746 	/**
5747 	 * Location of indirect buffer used to pass init data to ABM.
5748 	 */
5749 	union dmub_addr src;
5750 
5751 	/**
5752 	 * Indirect buffer length.
5753 	 */
5754 	uint16_t bytes;
5755 
5756 
5757 	/**
5758 	 * ABM control version.
5759 	 */
5760 	uint8_t version;
5761 
5762 	/**
5763 	 * Panel Control HW instance mask.
5764 	 * Bit 0 is Panel Control HW instance 0.
5765 	 * Bit 1 is Panel Control HW instance 1.
5766 	 */
5767 	uint8_t panel_mask;
5768 
5769 	/**
5770 	 * Explicit padding to 4 byte boundary.
5771 	 */
5772 	uint8_t pad[2];
5773 };
5774 
5775 /**
5776  * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
5777  */
5778 struct dmub_rb_cmd_abm_init_config {
5779 	/**
5780 	 * Command header.
5781 	 */
5782 	struct dmub_cmd_header header;
5783 
5784 	/**
5785 	 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
5786 	 */
5787 	struct dmub_cmd_abm_init_config_data abm_init_config_data;
5788 };
5789 
5790 /**
5791  * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
5792  */
5793 
5794 struct dmub_cmd_abm_pause_data {
5795 
5796 	/**
5797 	 * Panel Control HW instance mask.
5798 	 * Bit 0 is Panel Control HW instance 0.
5799 	 * Bit 1 is Panel Control HW instance 1.
5800 	 */
5801 	uint8_t panel_mask;
5802 
5803 	/**
5804 	 * OTG hw instance
5805 	 */
5806 	uint8_t otg_inst;
5807 
5808 	/**
5809 	 * Enable or disable ABM pause
5810 	 */
5811 	uint8_t enable;
5812 
5813 	/**
5814 	 * Explicit padding to 4 byte boundary.
5815 	 */
5816 	uint8_t pad[1];
5817 };
5818 
5819 /**
5820  * Definition of a DMUB_CMD__ABM_PAUSE command.
5821  */
5822 struct dmub_rb_cmd_abm_pause {
5823 	/**
5824 	 * Command header.
5825 	 */
5826 	struct dmub_cmd_header header;
5827 
5828 	/**
5829 	 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
5830 	 */
5831 	struct dmub_cmd_abm_pause_data abm_pause_data;
5832 };
5833 
5834 /**
5835  * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.
5836  */
5837 struct dmub_cmd_abm_query_caps_in {
5838 	/**
5839 	 * Panel instance.
5840 	 */
5841 	uint8_t panel_inst;
5842 
5843 	/**
5844 	 * Explicit padding to 4 byte boundary.
5845 	 */
5846 	uint8_t pad[3];
5847 };
5848 
5849 /**
5850  * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.
5851  */
5852 struct dmub_cmd_abm_query_caps_out {
5853 	/**
5854 	 * SW Algorithm caps.
5855 	 */
5856 	struct abm_caps sw_caps;
5857 
5858 	/**
5859 	 * ABM HW caps.
5860 	 */
5861 	struct abm_caps hw_caps;
5862 };
5863 
5864 /**
5865  * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
5866  */
5867 struct dmub_rb_cmd_abm_query_caps {
5868 	/**
5869 	 * Command header.
5870 	 */
5871 	struct dmub_cmd_header header;
5872 
5873 	/**
5874 	 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.
5875 	 */
5876 	union {
5877 		struct dmub_cmd_abm_query_caps_in  abm_query_caps_in;
5878 		struct dmub_cmd_abm_query_caps_out abm_query_caps_out;
5879 	} data;
5880 };
5881 
5882 /**
5883  * enum dmub_abm_ace_curve_type - ACE curve type.
5884  */
5885 enum dmub_abm_ace_curve_type {
5886 	/**
5887 	 * ACE curve as defined by the SW layer.
5888 	 */
5889 	ABM_ACE_CURVE_TYPE__SW = 0,
5890 	/**
5891 	 * ACE curve as defined by the SW to HW translation interface layer.
5892 	 */
5893 	ABM_ACE_CURVE_TYPE__SW_IF = 1,
5894 };
5895 
5896 /**
5897  * enum dmub_abm_histogram_type - Histogram type.
5898  */
5899 enum dmub_abm_histogram_type {
5900 	/**
5901 	 * ACE curve as defined by the SW layer.
5902 	 */
5903 	ABM_HISTOGRAM_TYPE__SW = 0,
5904 	/**
5905 	 * ACE curve as defined by the SW to HW translation interface layer.
5906 	 */
5907 	ABM_HISTOGRAM_TYPE__SW_IF = 1,
5908 };
5909 
5910 /**
5911  * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
5912  */
5913 struct dmub_rb_cmd_abm_get_ace_curve {
5914 	/**
5915 	 * Command header.
5916 	 */
5917 	struct dmub_cmd_header header;
5918 
5919 	/**
5920 	 * Address where ACE curve should be copied.
5921 	 */
5922 	union dmub_addr dest;
5923 
5924 	/**
5925 	 * Type of ACE curve being queried.
5926 	 */
5927 	enum dmub_abm_ace_curve_type ace_type;
5928 
5929 	/**
5930 	 * Indirect buffer length.
5931 	 */
5932 	uint16_t bytes;
5933 
5934 	/**
5935 	 * eDP panel instance.
5936 	 */
5937 	uint8_t panel_inst;
5938 
5939 	/**
5940 	 * Explicit padding to 4 byte boundary.
5941 	 */
5942 	uint8_t pad;
5943 };
5944 
5945 /**
5946  * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command.
5947  */
5948 struct dmub_rb_cmd_abm_get_histogram {
5949 	/**
5950 	 * Command header.
5951 	 */
5952 	struct dmub_cmd_header header;
5953 
5954 	/**
5955 	 * Address where Histogram should be copied.
5956 	 */
5957 	union dmub_addr dest;
5958 
5959 	/**
5960 	 * Type of Histogram being queried.
5961 	 */
5962 	enum dmub_abm_histogram_type histogram_type;
5963 
5964 	/**
5965 	 * Indirect buffer length.
5966 	 */
5967 	uint16_t bytes;
5968 
5969 	/**
5970 	 * eDP panel instance.
5971 	 */
5972 	uint8_t panel_inst;
5973 
5974 	/**
5975 	 * Explicit padding to 4 byte boundary.
5976 	 */
5977 	uint8_t pad;
5978 };
5979 
5980 /**
5981  * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
5982  */
5983 struct dmub_rb_cmd_abm_save_restore {
5984 	/**
5985 	 * Command header.
5986 	 */
5987 	struct dmub_cmd_header header;
5988 
5989 	/**
5990 	 * OTG hw instance
5991 	 */
5992 	uint8_t otg_inst;
5993 
5994 	/**
5995 	 * Enable or disable ABM pause
5996 	 */
5997 	uint8_t freeze;
5998 
5999 	/**
6000 	 * Explicit padding to 4 byte boundary.
6001 	 */
6002 	uint8_t debug;
6003 
6004 	/**
6005 	 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
6006 	 */
6007 	struct dmub_cmd_abm_init_config_data abm_init_config_data;
6008 };
6009 
6010 /**
6011  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
6012  */
6013 
6014 struct dmub_cmd_abm_set_event_data {
6015 
6016 	/**
6017 	 * VB Scaling Init. Strength Mapping
6018 	 * Byte 0: 0~255 for VB level 0
6019 	 * Byte 1: 0~255 for VB level 1
6020 	 * Byte 2: 0~255 for VB level 2
6021 	 * Byte 3: 0~255 for VB level 3
6022 	 */
6023 	uint32_t vb_scaling_strength_mapping;
6024 	/**
6025 	 * VariBright Scaling Enable
6026 	 */
6027 	uint8_t vb_scaling_enable;
6028 	/**
6029 	 * Panel Control HW instance mask.
6030 	 * Bit 0 is Panel Control HW instance 0.
6031 	 * Bit 1 is Panel Control HW instance 1.
6032 	 */
6033 	uint8_t panel_mask;
6034 
6035 	/**
6036 	 * Explicit padding to 4 byte boundary.
6037 	 */
6038 	uint8_t pad[2];
6039 };
6040 
6041 /**
6042  * Definition of a DMUB_CMD__ABM_SET_EVENT command.
6043  */
6044 struct dmub_rb_cmd_abm_set_event {
6045 	/**
6046 	 * Command header.
6047 	 */
6048 	struct dmub_cmd_header header;
6049 
6050 	/**
6051 	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
6052 	 */
6053 	struct dmub_cmd_abm_set_event_data abm_set_event_data;
6054 };
6055 
6056 /**
6057  * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
6058  */
6059 struct dmub_cmd_query_feature_caps_data {
6060 	/**
6061 	 * DMUB feature capabilities.
6062 	 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
6063 	 */
6064 	struct dmub_feature_caps feature_caps;
6065 };
6066 
6067 /**
6068  * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
6069  */
6070 struct dmub_rb_cmd_query_feature_caps {
6071 	/**
6072 	 * Command header.
6073 	 */
6074 	struct dmub_cmd_header header;
6075 	/**
6076 	 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
6077 	 */
6078 	struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
6079 };
6080 
6081 /**
6082  * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6083  */
6084 struct dmub_cmd_visual_confirm_color_data {
6085 	/**
6086 	 * DMUB visual confirm color
6087 	 */
6088 	struct dmub_visual_confirm_color visual_confirm_color;
6089 };
6090 
6091 /**
6092  * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6093  */
6094 struct dmub_rb_cmd_get_visual_confirm_color {
6095 	/**
6096 	 * Command header.
6097 	 */
6098 	struct dmub_cmd_header header;
6099 	/**
6100 	 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6101 	 */
6102 	struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
6103 };
6104 
6105 /**
6106  * enum dmub_cmd_panel_cntl_type - Panel control command.
6107  */
6108 enum dmub_cmd_panel_cntl_type {
6109 	/**
6110 	 * Initializes embedded panel hardware blocks.
6111 	 */
6112 	DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
6113 	/**
6114 	 * Queries backlight info for the embedded panel.
6115 	 */
6116 	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
6117 	/**
6118 	 * Sets the PWM Freq as per user's requirement.
6119 	 */
6120 	DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
6121 };
6122 
6123 /**
6124  * struct dmub_cmd_panel_cntl_data - Panel control data.
6125  */
6126 struct dmub_cmd_panel_cntl_data {
6127 	uint32_t pwrseq_inst; /**< pwrseq instance */
6128 	uint32_t current_backlight; /* in/out */
6129 	uint32_t bl_pwm_cntl; /* in/out */
6130 	uint32_t bl_pwm_period_cntl; /* in/out */
6131 	uint32_t bl_pwm_ref_div1; /* in/out */
6132 	uint8_t is_backlight_on : 1; /* in/out */
6133 	uint8_t is_powered_on : 1; /* in/out */
6134 	uint8_t padding[3];
6135 	uint32_t bl_pwm_ref_div2; /* in/out */
6136 	uint8_t reserved[4];
6137 };
6138 
6139 /**
6140  * struct dmub_rb_cmd_panel_cntl - Panel control command.
6141  */
6142 struct dmub_rb_cmd_panel_cntl {
6143 	struct dmub_cmd_header header; /**< header */
6144 	struct dmub_cmd_panel_cntl_data data; /**< payload */
6145 };
6146 
6147 struct dmub_optc_state {
6148 	uint32_t v_total_max;
6149 	uint32_t v_total_min;
6150 	uint32_t tg_inst;
6151 };
6152 
6153 struct dmub_rb_cmd_drr_update {
6154 	struct dmub_cmd_header header;
6155 	struct dmub_optc_state dmub_optc_state_req;
6156 };
6157 
6158 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
6159 	uint32_t pix_clk_100hz;
6160 	uint8_t max_ramp_step;
6161 	uint8_t pipes;
6162 	uint8_t min_refresh_in_hz;
6163 	uint8_t pipe_count;
6164 	uint8_t pipe_index[4];
6165 };
6166 
6167 struct dmub_cmd_fw_assisted_mclk_switch_config {
6168 	uint8_t fams_enabled;
6169 	uint8_t visual_confirm_enabled;
6170 	uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
6171 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
6172 };
6173 
6174 struct dmub_rb_cmd_fw_assisted_mclk_switch {
6175 	struct dmub_cmd_header header;
6176 	struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
6177 };
6178 
6179 /**
6180  * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6181  */
6182 struct dmub_cmd_lvtma_control_data {
6183 	uint8_t uc_pwr_action; /**< LVTMA_ACTION */
6184 	uint8_t bypass_panel_control_wait;
6185 	uint8_t reserved_0[2]; /**< For future use */
6186 	uint8_t pwrseq_inst; /**< LVTMA control instance */
6187 	uint8_t reserved_1[3]; /**< For future use */
6188 };
6189 
6190 /**
6191  * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6192  */
6193 struct dmub_rb_cmd_lvtma_control {
6194 	/**
6195 	 * Command header.
6196 	 */
6197 	struct dmub_cmd_header header;
6198 	/**
6199 	 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6200 	 */
6201 	struct dmub_cmd_lvtma_control_data data;
6202 };
6203 
6204 /**
6205  * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
6206  */
6207 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
6208 	uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
6209 	uint8_t is_usb; /**< is phy is usb */
6210 	uint8_t is_dp_alt_disable; /**< is dp alt disable */
6211 	uint8_t is_dp4; /**< is dp in 4 lane */
6212 };
6213 
6214 /**
6215  * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
6216  */
6217 struct dmub_rb_cmd_transmitter_query_dp_alt {
6218 	struct dmub_cmd_header header; /**< header */
6219 	struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
6220 };
6221 
6222 struct phy_test_mode {
6223 	uint8_t mode;
6224 	uint8_t pat0;
6225 	uint8_t pad[2];
6226 };
6227 
6228 /**
6229  * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
6230  */
6231 struct dmub_rb_cmd_transmitter_set_phy_fsm_data {
6232 	uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
6233 	uint8_t mode; /**< HDMI/DP/DP2 etc */
6234 	uint8_t lane_num; /**< Number of lanes */
6235 	uint32_t symclk_100Hz; /**< PLL symclock in 100hz */
6236 	struct phy_test_mode test_mode;
6237 	enum dmub_phy_fsm_state state;
6238 	uint32_t status;
6239 	uint8_t pad;
6240 };
6241 
6242 /**
6243  * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
6244  */
6245 struct dmub_rb_cmd_transmitter_set_phy_fsm {
6246 	struct dmub_cmd_header header; /**< header */
6247 	struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */
6248 };
6249 
6250 /**
6251  * Maximum number of bytes a chunk sent to DMUB for parsing
6252  */
6253 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
6254 
6255 /**
6256  *  Represent a chunk of CEA blocks sent to DMUB for parsing
6257  */
6258 struct dmub_cmd_send_edid_cea {
6259 	uint16_t offset;	/**< offset into the CEA block */
6260 	uint8_t length;	/**< number of bytes in payload to copy as part of CEA block */
6261 	uint16_t cea_total_length;  /**< total length of the CEA block */
6262 	uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
6263 	uint8_t pad[3]; /**< padding and for future expansion */
6264 };
6265 
6266 /**
6267  * Result of VSDB parsing from CEA block
6268  */
6269 struct dmub_cmd_edid_cea_amd_vsdb {
6270 	uint8_t vsdb_found;		/**< 1 if parsing has found valid AMD VSDB */
6271 	uint8_t freesync_supported;	/**< 1 if Freesync is supported */
6272 	uint16_t amd_vsdb_version;	/**< AMD VSDB version */
6273 	uint16_t min_frame_rate;	/**< Maximum frame rate */
6274 	uint16_t max_frame_rate;	/**< Minimum frame rate */
6275 	uint8_t freesync_mccs_vcp_code; /**< Freesync MCCS VCP code */
6276 };
6277 
6278 /**
6279  * Result of sending a CEA chunk
6280  */
6281 struct dmub_cmd_edid_cea_ack {
6282 	uint16_t offset;	/**< offset of the chunk into the CEA block */
6283 	uint8_t success;	/**< 1 if this sending of chunk succeeded */
6284 	uint8_t pad;		/**< padding and for future expansion */
6285 };
6286 
6287 /**
6288  * Specify whether the result is an ACK/NACK or the parsing has finished
6289  */
6290 enum dmub_cmd_edid_cea_reply_type {
6291 	DMUB_CMD__EDID_CEA_AMD_VSDB	= 1, /**< VSDB parsing has finished */
6292 	DMUB_CMD__EDID_CEA_ACK		= 2, /**< acknowledges the CEA sending is OK or failing */
6293 };
6294 
6295 /**
6296  * Definition of a DMUB_CMD__EDID_CEA command.
6297  */
6298 struct dmub_rb_cmd_edid_cea {
6299 	struct dmub_cmd_header header;	/**< Command header */
6300 	union dmub_cmd_edid_cea_data {
6301 		struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
6302 		struct dmub_cmd_edid_cea_output { /**< output with results */
6303 			uint8_t type;	/**< dmub_cmd_edid_cea_reply_type */
6304 			union {
6305 				struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
6306 				struct dmub_cmd_edid_cea_ack ack;
6307 			};
6308 		} output;	/**< output to retrieve ACK/NACK or VSDB parsing results */
6309 	} data;	/**< Command data */
6310 
6311 };
6312 
6313 /**
6314  * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
6315  */
6316 struct dmub_cmd_cable_id_input {
6317 	uint8_t phy_inst;  /**< phy inst for cable id data */
6318 };
6319 
6320 /**
6321  * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
6322  */
6323 struct dmub_cmd_cable_id_output {
6324 	uint8_t UHBR10_20_CAPABILITY	:2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
6325 	uint8_t UHBR13_5_CAPABILITY	:1; /**< b'1 for UHBR13.5 support */
6326 	uint8_t CABLE_TYPE		:3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
6327 	uint8_t RESERVED		:2; /**< reserved means not defined */
6328 };
6329 
6330 /**
6331  * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
6332  */
6333 struct dmub_rb_cmd_get_usbc_cable_id {
6334 	struct dmub_cmd_header header; /**< Command header */
6335 	/**
6336 	 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
6337 	 */
6338 	union dmub_cmd_cable_id_data {
6339 		struct dmub_cmd_cable_id_input input; /**< Input */
6340 		struct dmub_cmd_cable_id_output output; /**< Output */
6341 		uint8_t output_raw; /**< Raw data output */
6342 	} data;
6343 };
6344 
6345 enum dmub_cmd_fused_io_sub_type {
6346 	DMUB_CMD__FUSED_IO_EXECUTE = 0,
6347 	DMUB_CMD__FUSED_IO_ABORT = 1,
6348 };
6349 
6350 enum dmub_cmd_fused_request_type {
6351 	FUSED_REQUEST_READ,
6352 	FUSED_REQUEST_WRITE,
6353 	FUSED_REQUEST_POLL,
6354 };
6355 
6356 enum dmub_cmd_fused_request_status {
6357 	FUSED_REQUEST_STATUS_SUCCESS,
6358 	FUSED_REQUEST_STATUS_BEGIN,
6359 	FUSED_REQUEST_STATUS_SUBMIT,
6360 	FUSED_REQUEST_STATUS_REPLY,
6361 	FUSED_REQUEST_STATUS_POLL,
6362 	FUSED_REQUEST_STATUS_ABORTED,
6363 	FUSED_REQUEST_STATUS_FAILED = 0x80,
6364 	FUSED_REQUEST_STATUS_INVALID,
6365 	FUSED_REQUEST_STATUS_BUSY,
6366 	FUSED_REQUEST_STATUS_TIMEOUT,
6367 	FUSED_REQUEST_STATUS_POLL_TIMEOUT,
6368 };
6369 
6370 struct dmub_cmd_fused_request {
6371 	uint8_t status;
6372 	uint8_t type : 2;
6373 	uint8_t _reserved0 : 3;
6374 	uint8_t poll_mask_msb : 3;  // Number of MSB to zero out from last byte before comparing
6375 	uint8_t identifier;
6376 	uint8_t _reserved1;
6377 	uint32_t timeout_us;
6378 	union dmub_cmd_fused_request_location {
6379 		struct dmub_cmd_fused_request_location_i2c {
6380 			uint8_t is_aux : 1;  // False
6381 			uint8_t ddc_line : 3;
6382 			uint8_t over_aux : 1;
6383 			uint8_t _reserved0 : 3;
6384 			uint8_t address;
6385 			uint8_t offset;
6386 			uint8_t length;
6387 		} i2c;
6388 		struct dmub_cmd_fused_request_location_aux {
6389 			uint32_t is_aux : 1;  // True
6390 			uint32_t ddc_line : 3;
6391 			uint32_t address : 20;
6392 			uint32_t length : 8;  // Automatically split into 16B transactions
6393 		} aux;
6394 	} u;
6395 	uint8_t buffer[0x30];  // Read: out, write: in, poll: expected
6396 };
6397 
6398 struct dmub_rb_cmd_fused_io {
6399 	struct dmub_cmd_header header;
6400 	struct dmub_cmd_fused_request request;
6401 };
6402 
6403 /**
6404  * Command type of a DMUB_CMD__SECURE_DISPLAY command
6405  */
6406 enum dmub_cmd_secure_display_type {
6407 	DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0,		/* test command to only check if inbox message works */
6408 	DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
6409 	DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY,
6410 	DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE,
6411 	DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY
6412 };
6413 
6414 #define MAX_ROI_NUM	2
6415 
6416 struct dmub_cmd_roi_info {
6417 	uint16_t x_start;
6418 	uint16_t x_end;
6419 	uint16_t y_start;
6420 	uint16_t y_end;
6421 	uint8_t otg_id;
6422 	uint8_t phy_id;
6423 };
6424 
6425 struct dmub_cmd_roi_window_ctl {
6426 	uint16_t x_start;
6427 	uint16_t x_end;
6428 	uint16_t y_start;
6429 	uint16_t y_end;
6430 	bool enable;
6431 };
6432 
6433 struct dmub_cmd_roi_ctl_info {
6434 	uint8_t otg_id;
6435 	uint8_t phy_id;
6436 	struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM];
6437 };
6438 
6439 /**
6440  * Definition of a DMUB_CMD__SECURE_DISPLAY command
6441  */
6442 struct dmub_rb_cmd_secure_display {
6443 	struct dmub_cmd_header header;
6444 	/**
6445 	 * Data passed from driver to dmub firmware.
6446 	 */
6447 	struct dmub_cmd_roi_info roi_info;
6448 	struct dmub_cmd_roi_ctl_info mul_roi_ctl;
6449 };
6450 
6451 /**
6452  * Command type of a DMUB_CMD__PSP command
6453  */
6454 enum dmub_cmd_psp_type {
6455 	DMUB_CMD__PSP_ASSR_ENABLE = 0
6456 };
6457 
6458 /**
6459  * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.
6460  */
6461 struct dmub_cmd_assr_enable_data {
6462 	/**
6463 	 * ASSR enable or disable.
6464 	 */
6465 	uint8_t enable;
6466 	/**
6467 	 * PHY port type.
6468 	 * Indicates eDP / non-eDP port type
6469 	 */
6470 	uint8_t phy_port_type;
6471 	/**
6472 	 * PHY port ID.
6473 	 */
6474 	uint8_t phy_port_id;
6475 	/**
6476 	 * Link encoder index.
6477 	 */
6478 	uint8_t link_enc_index;
6479 	/**
6480 	 * HPO mode.
6481 	 */
6482 	uint8_t hpo_mode;
6483 
6484 	/**
6485 	 * Reserved field.
6486 	 */
6487 	uint8_t reserved[7];
6488 };
6489 
6490 /**
6491  * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
6492  */
6493 struct dmub_rb_cmd_assr_enable {
6494 	/**
6495 	 * Command header.
6496 	 */
6497 	struct dmub_cmd_header header;
6498 
6499 	/**
6500 	 * Assr data.
6501 	 */
6502 	struct dmub_cmd_assr_enable_data assr_data;
6503 
6504 	/**
6505 	 * Reserved field.
6506 	 */
6507 	uint32_t reserved[3];
6508 };
6509 
6510 /**
6511  * Current definition of "ips_mode" from driver
6512  */
6513 enum ips_residency_mode {
6514 	IPS_RESIDENCY__IPS1_MAX,
6515 	IPS_RESIDENCY__IPS2,
6516 	IPS_RESIDENCY__IPS1_RCG,
6517 	IPS_RESIDENCY__IPS1_ONO2_ON,
6518 	IPS_RESIDENCY__IPS1_Z8_RETENTION,
6519 	IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS,
6520 	IPS_RESIDENCY__PG_ONO_CURRENT_STATE
6521 };
6522 
6523 #define NUM_IPS_HISTOGRAM_BUCKETS 16
6524 
6525 /**
6526  * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats
6527  */
6528 struct dmub_ips_residency_info {
6529 	uint32_t residency_millipercent;
6530 	uint32_t entry_counter;
6531 	uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS];
6532 	uint64_t total_time_us;
6533 	uint64_t total_inactive_time_us;
6534 	uint32_t ono_pg_state_at_collection;
6535 	uint32_t ono_pg_state_last_seen_in_ips;
6536 };
6537 
6538 /**
6539  * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command.
6540  */
6541 struct dmub_cmd_ips_residency_cntl_data {
6542 	uint8_t panel_inst;
6543 	uint8_t start_measurement;
6544 	uint8_t padding[2]; // align to 4-byte boundary
6545 };
6546 
6547 struct dmub_rb_cmd_ips_residency_cntl {
6548 	struct dmub_cmd_header header;
6549 	struct dmub_cmd_ips_residency_cntl_data cntl_data;
6550 };
6551 
6552 /**
6553  * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command.
6554  */
6555 struct dmub_cmd_ips_query_residency_info_data {
6556 	union dmub_addr dest;
6557 	uint32_t size;
6558 	uint32_t ips_mode;
6559 	uint8_t panel_inst;
6560 	uint8_t padding[3]; // align to 4-byte boundary
6561 };
6562 
6563 struct dmub_rb_cmd_ips_query_residency_info {
6564 	struct dmub_cmd_header header;
6565 	struct dmub_cmd_ips_query_residency_info_data info_data;
6566 };
6567 
6568 /**
6569  * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command.
6570  */
6571 struct dmub_cmd_cursor_offload_init_data {
6572 	union dmub_addr state_addr; /**< State address for dmub_cursor_offload */
6573 	uint32_t state_size; /**< State size for dmub_cursor_offload */
6574 };
6575 
6576 /**
6577  * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload.
6578  */
6579 struct dmub_rb_cmd_cursor_offload_init {
6580 	struct dmub_cmd_header header;
6581 	struct dmub_cmd_cursor_offload_init_data init_data;
6582 };
6583 
6584 /**
6585  * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command.
6586  */
6587 struct dmub_cmd_cursor_offload_stream_data {
6588 	uint32_t otg_inst: 4; /**< OTG instance to control  */
6589 	uint32_t reserved: 28; /**< Reserved for future use */
6590 	uint32_t line_time_in_ns; /**< Line time in ns for the OTG */
6591 	uint32_t v_total_max; /**< OTG v_total_max */
6592 };
6593 
6594 /**
6595  * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload.
6596  */
6597 struct dmub_rb_cmd_cursor_offload_stream_cntl {
6598 	struct dmub_cmd_header header;
6599 	struct dmub_cmd_cursor_offload_stream_data data;
6600 };
6601 
6602 /**
6603  * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command.
6604  */
6605 struct dmub_cmd_pr_enable_data {
6606 	/**
6607 	 * Panel Replay enable or disable.
6608 	 */
6609 	uint8_t enable;
6610 	/**
6611 	 * Panel Instance.
6612 	 * Panel isntance to identify which replay_state to use
6613 	 * Currently the support is only for 0 or 1
6614 	 */
6615 	uint8_t panel_inst;
6616 	/**
6617 	 * Phy state to enter.
6618 	 * Values to use are defined in dmub_phy_fsm_state
6619 	 */
6620 	uint8_t phy_fsm_state;
6621 	/**
6622 	 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
6623 	 * Set this using enum phy_link_rate.
6624 	 * This does not support HDMI/DP2 for now.
6625 	 */
6626 	uint8_t phy_rate;
6627 	/**
6628 	 * @hpo_stream_enc_inst: HPO stream encoder instance
6629 	 */
6630 	uint8_t hpo_stream_enc_inst;
6631 	/**
6632 	 * @hpo_link_enc_inst: HPO link encoder instance
6633 	 */
6634 	uint8_t hpo_link_enc_inst;
6635 	/**
6636 	 * @pad: Align structure to 4 byte boundary.
6637 	 */
6638 	uint8_t pad[2];
6639 };
6640 
6641 /**
6642  * Definition of a DMUB_CMD__PR_ENABLE command.
6643  * Panel Replay enable/disable is controlled using action in data.
6644  */
6645 struct dmub_rb_cmd_pr_enable {
6646 	/**
6647 	 * Command header.
6648 	 */
6649 	struct dmub_cmd_header header;
6650 
6651 	struct dmub_cmd_pr_enable_data data;
6652 };
6653 
6654 /**
6655  * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.
6656  */
6657 struct dmub_cmd_pr_copy_settings_data {
6658 	/**
6659 	 * Flags that can be set by driver to change some replay behaviour.
6660 	 */
6661 	union pr_debug_flags debug;
6662 
6663 	/**
6664 	 * @flags: Flags used to determine feature functionality.
6665 	 */
6666 	union pr_hw_flags flags;
6667 
6668 	/**
6669 	 * DPP HW instance.
6670 	 */
6671 	uint8_t dpp_inst;
6672 	/**
6673 	 * OTG HW instance.
6674 	 */
6675 	uint8_t otg_inst;
6676 	/**
6677 	 * DIG FE HW instance.
6678 	 */
6679 	uint8_t digfe_inst;
6680 	/**
6681 	 * DIG BE HW instance.
6682 	 */
6683 	uint8_t digbe_inst;
6684 	/**
6685 	 * AUX HW instance.
6686 	 */
6687 	uint8_t aux_inst;
6688 	/**
6689 	 * Panel Instance.
6690 	 * Panel isntance to identify which psr_state to use
6691 	 * Currently the support is only for 0 or 1
6692 	 */
6693 	uint8_t panel_inst;
6694 	/**
6695 	 * PHY instance.
6696 	 */
6697 	uint8_t dpphy_inst;
6698 	/**
6699 	 * Determines if SMU optimzations are enabled/disabled.
6700 	 */
6701 	uint8_t smu_optimizations_en;
6702 	/**
6703 	 * Length of each horizontal line in ns.
6704 	 */
6705 	uint32_t line_time_in_ns;
6706 	/*
6707 	 * Use FSFT afftet pixel clk
6708 	 */
6709 	uint32_t pix_clk_100hz;
6710 	/*
6711 	 * Use Original pixel clock
6712 	 */
6713 	uint32_t sink_pix_clk_100hz;
6714 	/**
6715 	 * Use for AUX-less ALPM LFPS wake operation
6716 	 */
6717 	struct dmub_alpm_auxless_data auxless_alpm_data;
6718 	/**
6719 	 * DSC Slice height.
6720 	 */
6721 	uint16_t dsc_slice_height;
6722 	/*
6723 	 * Use FSM state for Replay power up/down
6724 	 */
6725 	uint8_t use_phy_fsm;
6726 	/**
6727 	 * @hpo_stream_enc_inst: HPO stream encoder instance
6728 	 */
6729 	uint8_t hpo_stream_enc_inst;
6730 	/**
6731 	 * @hpo_link_enc_inst: HPO link encoder instance
6732 	 */
6733 	uint8_t hpo_link_enc_inst;
6734 	/*
6735 	 * Selective Update granularity needed.
6736 	 */
6737 	uint8_t su_granularity_needed;
6738 	/*
6739 	 * Horizontal granularity for Selective Update.
6740 	 */
6741 	uint16_t su_x_granularity;
6742 	/*
6743 	 * Extended caps of vertical granularity for Selective Update.
6744 	 */
6745 	uint16_t su_y_granularity_extended_caps;
6746 	/*
6747 	 * Vertical granularity for Selective Update.
6748 	 */
6749 	uint8_t su_y_granularity;
6750 	/**
6751 	 * @main_link_activity_option: Indicates main link activity option selected
6752 	 */
6753 	uint8_t main_link_activity_option;
6754 };
6755 
6756 /**
6757  * Definition of a DMUB_CMD__PR_COPY_SETTINGS command.
6758  */
6759 struct dmub_rb_cmd_pr_copy_settings {
6760 	/**
6761 	 * Command header.
6762 	 */
6763 	struct dmub_cmd_header header;
6764 	/**
6765 	 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.
6766 	 */
6767 	struct dmub_cmd_pr_copy_settings_data data;
6768 };
6769 
6770 union dmub_pr_runtime_flags {
6771 	struct {
6772 		uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR
6773 	} bitfields;
6774 	uint32_t u32All;
6775 };
6776 
6777 struct dmub_cmd_pr_update_state_data {
6778 	/**
6779 	 * Panel Instance.
6780 	 * Panel isntance to identify which psr_state to use
6781 	 * Currently the support is only for 0 or 1
6782 	 */
6783 	uint8_t panel_inst;
6784 
6785 	uint8_t pad[3]; // align to 4-byte boundary
6786 	/*
6787 	 * Update flags to control the update behavior.
6788 	 */
6789 	uint32_t update_flag;
6790 	/**
6791 	 * state/data to set.
6792 	 */
6793 	uint32_t coasting_vtotal;
6794 	uint32_t sync_mode;
6795 
6796 	union dmub_pr_runtime_flags pr_runtime_flags;
6797 };
6798 
6799 struct dmub_cmd_pr_general_cmd_data {
6800 	/**
6801 	 * Panel Instance.
6802 	 * Panel isntance to identify which psr_state to use
6803 	 * Currently the support is only for 0 or 1
6804 	 */
6805 	uint8_t panel_inst;
6806 	/**
6807 	 * subtype: PR general cmd sub type
6808 	 */
6809 	uint8_t subtype;
6810 
6811 	uint8_t pad[2];
6812 	/**
6813 	 * config data by different subtypes
6814 	 */
6815 	union {
6816 		uint32_t u32All;
6817 	} data;
6818 };
6819 
6820 /**
6821  * Definition of a DMUB_CMD__PR_UPDATE_STATE command.
6822  */
6823 struct dmub_rb_cmd_pr_update_state {
6824 	/**
6825 	 * Command header.
6826 	 */
6827 	struct dmub_cmd_header header;
6828 	/**
6829 	 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command.
6830 	 */
6831 	struct dmub_cmd_pr_update_state_data data;
6832 };
6833 
6834 /**
6835  * Definition of a DMUB_CMD__PR_GENERAL_CMD command.
6836  */
6837 struct dmub_rb_cmd_pr_general_cmd {
6838 	/**
6839 	 * Command header.
6840 	 */
6841 	struct dmub_cmd_header header;
6842 	/**
6843 	 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command.
6844 	 */
6845 	struct dmub_cmd_pr_general_cmd_data data;
6846 };
6847 
6848 /**
6849  * Command type of a DMUB_CMD__BOOT_TIME_CRC command
6850  */
6851 enum dmub_cmd_boot_time_crc_type {
6852 	DMUB_CMD__BOOT_TIME_CRC_INIT_MEM = 0
6853 };
6854 
6855 /**
6856  * Data passed from driver to FW in a DMUB_CMD__BOOT_TIME_CRC_INIT command.
6857  */
6858 struct dmub_cmd_boot_time_crc_init_data {
6859 	union dmub_addr buffer_addr;
6860 	uint32_t buffer_size;
6861 };
6862 
6863 /**
6864  * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command.
6865  */
6866 struct dmub_rb_cmd_boot_time_crc_init {
6867 	struct dmub_cmd_header header;
6868 	struct dmub_cmd_boot_time_crc_init_data data;
6869 };
6870 
6871 /**
6872  * union dmub_rb_cmd - DMUB inbox command.
6873  */
6874 union dmub_rb_cmd {
6875 	/**
6876 	 * Elements shared with all commands.
6877 	 */
6878 	struct dmub_rb_cmd_common cmd_common;
6879 	/**
6880 	 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
6881 	 */
6882 	struct dmub_rb_cmd_read_modify_write read_modify_write;
6883 	/**
6884 	 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
6885 	 */
6886 	struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
6887 	/**
6888 	 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
6889 	 */
6890 	struct dmub_rb_cmd_burst_write burst_write;
6891 	/**
6892 	 * Definition of a DMUB_CMD__REG_REG_WAIT command.
6893 	 */
6894 	struct dmub_rb_cmd_reg_wait reg_wait;
6895 	/**
6896 	 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
6897 	 */
6898 	struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
6899 	/**
6900 	 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
6901 	 */
6902 	struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
6903 	/**
6904 	 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
6905 	 */
6906 	struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
6907 	/**
6908 	 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
6909 	 */
6910 	struct dmub_rb_cmd_dpphy_init dpphy_init;
6911 	/**
6912 	 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
6913 	 */
6914 	struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
6915 	/**
6916 	 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
6917 	 */
6918 	struct dmub_rb_cmd_domain_control domain_control;
6919 	/**
6920 	 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
6921 	 */
6922 	struct dmub_rb_cmd_psr_set_version psr_set_version;
6923 	/**
6924 	 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
6925 	 */
6926 	struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
6927 	/**
6928 	 * Definition of a DMUB_CMD__PSR_ENABLE command.
6929 	 */
6930 	struct dmub_rb_cmd_psr_enable psr_enable;
6931 	/**
6932 	 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
6933 	 */
6934 	struct dmub_rb_cmd_psr_set_level psr_set_level;
6935 	/**
6936 	 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
6937 	 */
6938 	struct dmub_rb_cmd_psr_force_static psr_force_static;
6939 	/**
6940 	 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
6941 	 */
6942 	struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
6943 	/**
6944 	 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
6945 	 */
6946 	struct dmub_rb_cmd_update_cursor_info update_cursor_info;
6947 	/**
6948 	 * Definition of a DMUB_CMD__HW_LOCK command.
6949 	 * Command is used by driver and FW.
6950 	 */
6951 	struct dmub_rb_cmd_lock_hw lock_hw;
6952 	/**
6953 	 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
6954 	 */
6955 	struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
6956 	/**
6957 	 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
6958 	 */
6959 	struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
6960 	/**
6961 	 * Definition of a DMUB_CMD__PLAT_54186_WA command.
6962 	 */
6963 	struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
6964 	/**
6965 	 * Definition of a DMUB_CMD__MALL command.
6966 	 */
6967 	struct dmub_rb_cmd_mall mall;
6968 
6969 	/**
6970 	 * Definition of a DMUB_CMD__CAB command.
6971 	 */
6972 	struct dmub_rb_cmd_cab_for_ss cab;
6973 
6974 	struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
6975 
6976 	/**
6977 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
6978 	 */
6979 	struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
6980 
6981 	/**
6982 	 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
6983 	 */
6984 	struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
6985 
6986 	/**
6987 	 * Definition of DMUB_CMD__PANEL_CNTL commands.
6988 	 */
6989 	struct dmub_rb_cmd_panel_cntl panel_cntl;
6990 
6991 	/**
6992 	 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
6993 	 */
6994 	struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
6995 
6996 	/**
6997 	 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
6998 	 */
6999 	struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
7000 
7001 	/**
7002 	 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
7003 	 */
7004 	struct dmub_rb_cmd_abm_set_level abm_set_level;
7005 
7006 	/**
7007 	 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
7008 	 */
7009 	struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
7010 
7011 	/**
7012 	 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
7013 	 */
7014 	struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
7015 
7016 	/**
7017 	 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
7018 	 */
7019 	struct dmub_rb_cmd_abm_init_config abm_init_config;
7020 
7021 	/**
7022 	 * Definition of a DMUB_CMD__ABM_PAUSE command.
7023 	 */
7024 	struct dmub_rb_cmd_abm_pause abm_pause;
7025 
7026 	/**
7027 	 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
7028 	 */
7029 	struct dmub_rb_cmd_abm_save_restore abm_save_restore;
7030 
7031 	/**
7032 	 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
7033 	 */
7034 	struct dmub_rb_cmd_abm_query_caps abm_query_caps;
7035 
7036 	/**
7037 	 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
7038 	 */
7039 	struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;
7040 
7041 	/**
7042 	 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command.
7043 	 */
7044 	struct dmub_rb_cmd_abm_get_histogram abm_get_histogram;
7045 
7046 	/**
7047 	 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
7048 	 */
7049 	struct dmub_rb_cmd_abm_set_event abm_set_event;
7050 
7051 	/**
7052 	 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
7053 	 */
7054 	struct dmub_rb_cmd_dp_aux_access dp_aux_access;
7055 
7056 	/**
7057 	 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
7058 	 */
7059 	struct dmub_rb_cmd_outbox1_enable outbox1_enable;
7060 
7061 	/**
7062 	 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
7063 	 */
7064 	struct dmub_rb_cmd_query_feature_caps query_feature_caps;
7065 
7066 	/**
7067 	 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
7068 	 */
7069 	struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
7070 	struct dmub_rb_cmd_drr_update drr_update;
7071 	struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
7072 
7073 	/**
7074 	 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
7075 	 */
7076 	struct dmub_rb_cmd_lvtma_control lvtma_control;
7077 	/**
7078 	 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
7079 	 */
7080 	struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
7081 	/**
7082 	 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
7083 	 */
7084 	struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;
7085 	/**
7086 	 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
7087 	 */
7088 	struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
7089 	/**
7090 	 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
7091 	 */
7092 	struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated)
7093 	/**
7094 	 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
7095 	 */
7096 	struct dmub_rb_cmd_set_config_request set_config_request;
7097 	/**
7098 	 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
7099 	 */
7100 	struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
7101 	/**
7102 	 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command.
7103 	 */
7104 	struct dmub_rb_cmd_set_tps_notification set_tps_notification;
7105 	/**
7106 	 * Definition of a DMUB_CMD__EDID_CEA command.
7107 	 */
7108 	struct dmub_rb_cmd_edid_cea edid_cea;
7109 	/**
7110 	 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
7111 	 */
7112 	struct dmub_rb_cmd_get_usbc_cable_id cable_id;
7113 
7114 	/**
7115 	 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
7116 	 */
7117 	struct dmub_rb_cmd_query_hpd_state query_hpd;
7118 	/**
7119 	 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
7120 	 */
7121 	struct dmub_rb_cmd_secure_display secure_display;
7122 
7123 	/**
7124 	 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
7125 	 */
7126 	struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
7127 	/**
7128 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
7129 	 */
7130 	struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
7131 	/**
7132 	 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
7133 	 */
7134 	struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;
7135 	/*
7136 	 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
7137 	 */
7138 	struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
7139 	/**
7140 	 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
7141 	 */
7142 	struct dmub_rb_cmd_replay_enable replay_enable;
7143 	/**
7144 	 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
7145 	 */
7146 	struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
7147 	/**
7148 	 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
7149 	 */
7150 	struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
7151 	/**
7152 	 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
7153 	 */
7154 	struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;
7155 
7156 	struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;
7157 	/**
7158 	 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
7159 	 */
7160 	struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;
7161 	/**
7162 	 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
7163 	 */
7164 	struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
7165 	/**
7166 	 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
7167 	 */
7168 	struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
7169 	/**
7170 	 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
7171 	 */
7172 	struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;
7173 	/**
7174 	 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
7175 	 */
7176 	struct dmub_rb_cmd_assr_enable assr_enable;
7177 
7178 	struct dmub_rb_cmd_fams2 fams2_config;
7179 
7180 	struct dmub_rb_cmd_ib ib_fams2_config;
7181 
7182 	struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;
7183 
7184 	struct dmub_rb_cmd_fams2_flip fams2_flip;
7185 
7186 	struct dmub_rb_cmd_fused_io fused_io;
7187 
7188 	/**
7189 	 * Definition of a DMUB_CMD__LSDMA command.
7190 	 */
7191 	struct dmub_rb_cmd_lsdma lsdma;
7192 
7193 	struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl;
7194 
7195 	struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info;
7196 	/**
7197 	 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command.
7198 	 */
7199 	struct dmub_rb_cmd_cursor_offload_init cursor_offload_init;
7200 	/**
7201 	 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands.
7202 	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE
7203 	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE
7204 	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM
7205 	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR
7206 	 */
7207 	struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl;
7208 	/**
7209 	 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command.
7210 	 */
7211 	struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable;
7212 	/**
7213 	 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.
7214 	 */
7215 	struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll;
7216 	/*
7217 	 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
7218 	 */
7219 	struct dmub_rb_cmd_pr_copy_settings pr_copy_settings;
7220 	/**
7221 	 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
7222 	 */
7223 	struct dmub_rb_cmd_pr_enable pr_enable;
7224 
7225 	struct dmub_rb_cmd_pr_update_state pr_update_state;
7226 
7227 	struct dmub_rb_cmd_pr_general_cmd pr_general_cmd;
7228 	/**
7229 	 * Definition of a DMUB_CMD__IHC command.
7230 	 */
7231 	struct dmub_rb_cmd_ihc ihc;
7232 	/**
7233 	 * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command.
7234 	 */
7235 	struct dmub_rb_cmd_boot_time_crc_init boot_time_crc_init;
7236 };
7237 
7238 /**
7239  * union dmub_rb_out_cmd - Outbox command
7240  */
7241 union dmub_rb_out_cmd {
7242 	/**
7243 	 * Parameters common to every command.
7244 	 */
7245 	struct dmub_rb_cmd_common cmd_common;
7246 	/**
7247 	 * AUX reply command.
7248 	 */
7249 	struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
7250 	/**
7251 	 * HPD notify command.
7252 	 */
7253 	struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
7254 	/**
7255 	 * SET_CONFIG reply command.
7256 	 */
7257 	struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
7258 	/**
7259 	 * DPIA notification command.
7260 	 */
7261 	struct dmub_rb_cmd_dpia_notification dpia_notification;
7262 	/**
7263 	 * HPD sense notification command.
7264 	 */
7265 	struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;
7266 	struct dmub_rb_cmd_fused_io fused_io;
7267 };
7268 #pragma pack(pop)
7269 
7270 
7271 //==============================================================================
7272 //</DMUB_CMD>===================================================================
7273 //==============================================================================
7274 //< DMUB_RB>====================================================================
7275 //==============================================================================
7276 
7277 /**
7278  * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
7279  */
7280 struct dmub_rb_init_params {
7281 	void *ctx; /**< Caller provided context pointer */
7282 	void *base_address; /**< CPU base address for ring's data */
7283 	uint32_t capacity; /**< Ringbuffer capacity in bytes */
7284 	uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
7285 	uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
7286 };
7287 
7288 /**
7289  * struct dmub_rb - Inbox or outbox DMUB ringbuffer
7290  */
7291 struct dmub_rb {
7292 	void *base_address; /**< CPU address for the ring's data */
7293 	uint32_t rptr; /**< Read pointer for consumer in bytes */
7294 	uint32_t wrpt; /**< Write pointer for producer in bytes */
7295 	uint32_t capacity; /**< Ringbuffer capacity in bytes */
7296 
7297 	void *ctx; /**< Caller provided context pointer */
7298 	void *dmub; /**< Pointer to the DMUB interface */
7299 };
7300 
7301 /**
7302  * @brief Checks if the ringbuffer is empty.
7303  *
7304  * @param rb DMUB Ringbuffer
7305  * @return true if empty
7306  * @return false otherwise
7307  */
7308 static inline bool dmub_rb_empty(struct dmub_rb *rb)
7309 {
7310 	return (rb->wrpt == rb->rptr);
7311 }
7312 
7313 /**
7314  * @brief gets number of outstanding requests in the RB
7315  *
7316  * @param rb DMUB Ringbuffer
7317  * @return true if full
7318  */
7319 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb)
7320 {
7321 	uint32_t data_count;
7322 
7323 	if (rb->wrpt >= rb->rptr)
7324 		data_count = rb->wrpt - rb->rptr;
7325 	else
7326 		data_count = rb->capacity - (rb->rptr - rb->wrpt);
7327 
7328 	return data_count / DMUB_RB_CMD_SIZE;
7329 }
7330 
7331 /**
7332  * @brief gets number of free buffers in the RB
7333  *
7334  * @param rb DMUB Ringbuffer
7335  * @return true if full
7336  */
7337 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb)
7338 {
7339 	uint32_t data_count;
7340 
7341 	if (rb->wrpt >= rb->rptr)
7342 		data_count = rb->wrpt - rb->rptr;
7343 	else
7344 		data_count = rb->capacity - (rb->rptr - rb->wrpt);
7345 
7346 	/* +1 because 1 entry is always unusable */
7347 	data_count += DMUB_RB_CMD_SIZE;
7348 
7349 	return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE;
7350 }
7351 
7352 /**
7353  * @brief Checks if the ringbuffer is full
7354  *
7355  * @param rb DMUB Ringbuffer
7356  * @return true if full
7357  * @return false otherwise
7358  */
7359 static inline bool dmub_rb_full(struct dmub_rb *rb)
7360 {
7361 	uint32_t data_count;
7362 
7363 	if (rb->wrpt >= rb->rptr)
7364 		data_count = rb->wrpt - rb->rptr;
7365 	else
7366 		data_count = rb->capacity - (rb->rptr - rb->wrpt);
7367 
7368 	/* -1 because 1 entry is always unusable */
7369 	return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
7370 }
7371 
7372 /**
7373  * @brief Pushes a command into the ringbuffer
7374  *
7375  * @param rb DMUB ringbuffer
7376  * @param cmd The command to push
7377  * @return true if the ringbuffer was not full
7378  * @return false otherwise
7379  */
7380 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
7381 				      const union dmub_rb_cmd *cmd)
7382 {
7383 	uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
7384 	const uint8_t *src = (const uint8_t *)cmd;
7385 	uint8_t i;
7386 
7387 	if (rb->capacity == 0)
7388 		return false;
7389 
7390 	if (dmub_rb_full(rb))
7391 		return false;
7392 
7393 	// copying data
7394 	for (i = 0; i < DMUB_RB_CMD_SIZE; i++)
7395 		*dst++ = *src++;
7396 
7397 	rb->wrpt += DMUB_RB_CMD_SIZE;
7398 
7399 	if (rb->wrpt >= rb->capacity)
7400 		rb->wrpt %= rb->capacity;
7401 
7402 	return true;
7403 }
7404 
7405 /**
7406  * @brief Pushes a command into the DMUB outbox ringbuffer
7407  *
7408  * @param rb DMUB outbox ringbuffer
7409  * @param cmd Outbox command
7410  * @return true if not full
7411  * @return false otherwise
7412  */
7413 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
7414 				      const union dmub_rb_out_cmd *cmd)
7415 {
7416 	uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
7417 	const uint8_t *src = (const uint8_t *)cmd;
7418 
7419 	if (rb->capacity == 0)
7420 		return false;
7421 
7422 	if (dmub_rb_full(rb))
7423 		return false;
7424 
7425 	dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
7426 
7427 	rb->wrpt += DMUB_RB_CMD_SIZE;
7428 
7429 	if (rb->wrpt >= rb->capacity)
7430 		rb->wrpt %= rb->capacity;
7431 
7432 	return true;
7433 }
7434 
7435 /**
7436  * @brief Returns the next unprocessed command in the ringbuffer.
7437  *
7438  * @param rb DMUB ringbuffer
7439  * @param cmd The command to return
7440  * @return true if not empty
7441  * @return false otherwise
7442  */
7443 static inline bool dmub_rb_front(struct dmub_rb *rb,
7444 				 union dmub_rb_cmd  **cmd)
7445 {
7446 	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
7447 
7448 	if (dmub_rb_empty(rb))
7449 		return false;
7450 
7451 	*cmd = (union dmub_rb_cmd *)rb_cmd;
7452 
7453 	return true;
7454 }
7455 
7456 /**
7457  * @brief Determines the next ringbuffer offset.
7458  *
7459  * @param rb DMUB inbox ringbuffer
7460  * @param num_cmds Number of commands
7461  * @param next_rptr The next offset in the ringbuffer
7462  */
7463 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
7464 				  uint32_t num_cmds,
7465 				  uint32_t *next_rptr)
7466 {
7467 	if (rb->capacity == 0)
7468 		return;
7469 
7470 	*next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
7471 
7472 	if (*next_rptr >= rb->capacity)
7473 		*next_rptr %= rb->capacity;
7474 }
7475 
7476 /**
7477  * @brief Returns a pointer to a command in the inbox.
7478  *
7479  * @param rb DMUB inbox ringbuffer
7480  * @param cmd The inbox command to return
7481  * @param rptr The ringbuffer offset
7482  * @return true if not empty
7483  * @return false otherwise
7484  */
7485 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
7486 				 union dmub_rb_cmd  **cmd,
7487 				 uint32_t rptr)
7488 {
7489 	uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
7490 
7491 	if (dmub_rb_empty(rb))
7492 		return false;
7493 
7494 	*cmd = (union dmub_rb_cmd *)rb_cmd;
7495 
7496 	return true;
7497 }
7498 
7499 /**
7500  * @brief Returns the next unprocessed command in the outbox.
7501  *
7502  * @param rb DMUB outbox ringbuffer
7503  * @param cmd The outbox command to return
7504  * @return true if not empty
7505  * @return false otherwise
7506  */
7507 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
7508 				 union dmub_rb_out_cmd *cmd)
7509 {
7510 	const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
7511 	uint64_t *dst = (uint64_t *)cmd;
7512 	uint8_t i;
7513 
7514 	if (dmub_rb_empty(rb))
7515 		return false;
7516 
7517 	// copying data
7518 	for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
7519 		*dst++ = *src++;
7520 
7521 	return true;
7522 }
7523 
7524 /**
7525  * @brief Removes the front entry in the ringbuffer.
7526  *
7527  * @param rb DMUB ringbuffer
7528  * @return true if the command was removed
7529  * @return false if there were no commands
7530  */
7531 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
7532 {
7533 	if (rb->capacity == 0)
7534 		return false;
7535 
7536 	if (dmub_rb_empty(rb))
7537 		return false;
7538 
7539 	rb->rptr += DMUB_RB_CMD_SIZE;
7540 
7541 	if (rb->rptr >= rb->capacity)
7542 		rb->rptr %= rb->capacity;
7543 
7544 	return true;
7545 }
7546 
7547 /**
7548  * @brief Flushes commands in the ringbuffer to framebuffer memory.
7549  *
7550  * Avoids a race condition where DMCUB accesses memory while
7551  * there are still writes in flight to framebuffer.
7552  *
7553  * @param rb DMUB ringbuffer
7554  */
7555 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
7556 {
7557 	uint32_t rptr = rb->rptr;
7558 	uint32_t wptr = rb->wrpt;
7559 
7560 	if (rb->capacity == 0)
7561 		return;
7562 
7563 	while (rptr != wptr) {
7564 		uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
7565 		uint8_t i;
7566 
7567 		for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
7568 			(void)READ_ONCE(*data++);
7569 
7570 		rptr += DMUB_RB_CMD_SIZE;
7571 		if (rptr >= rb->capacity)
7572 			rptr %= rb->capacity;
7573 	}
7574 }
7575 
7576 /**
7577  * @brief Initializes a DMCUB ringbuffer
7578  *
7579  * @param rb DMUB ringbuffer
7580  * @param init_params initial configuration for the ringbuffer
7581  */
7582 static inline void dmub_rb_init(struct dmub_rb *rb,
7583 				struct dmub_rb_init_params *init_params)
7584 {
7585 	rb->base_address = init_params->base_address;
7586 	rb->capacity = init_params->capacity;
7587 	rb->rptr = init_params->read_ptr;
7588 	rb->wrpt = init_params->write_ptr;
7589 }
7590 
7591 /**
7592  * @brief Copies output data from in/out commands into the given command.
7593  *
7594  * @param rb DMUB ringbuffer
7595  * @param cmd Command to copy data into
7596  */
7597 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
7598 					   union dmub_rb_cmd *cmd)
7599 {
7600 	// Copy rb entry back into command
7601 	uint8_t *rd_ptr = (rb->rptr == 0) ?
7602 		(uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
7603 		(uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
7604 
7605 	dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
7606 }
7607 
7608 //==============================================================================
7609 //</DMUB_RB>====================================================================
7610 //==============================================================================
7611 #endif /* _DMUB_CMD_H_ */
7612