Searched refs:DML_MAX_CLK_TABLE_SIZE (Results 1 – 4 of 4) sorted by relevance
10 #define DML_MAX_CLK_TABLE_SIZE 20 macro66 struct dml2_dcn4_uclk_dpm_dependent_qos_params per_uclk_dpm_params[DML_MAX_CLK_TABLE_SIZE];104 double g6_temp_read_blackout_us[DML_MAX_CLK_TABLE_SIZE];110 unsigned long clk_values_khz[DML_MAX_CLK_TABLE_SIZE];
46 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()69 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()92 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()115 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()138 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()161 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()184 for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
515 for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { in dml2_core_utils_get_qos_param_index()
7113 for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { in get_qos_param_index()7201 } entries[DML_MAX_CLK_TABLE_SIZE];7257 for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { in get_g6_temp_read_blackout_us()