1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
5 developing this code.
6
7 This contains the functions to handle the dma.
8
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
10
11
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13 *******************************************************************************/
14
15 #include <linux/io.h>
16 #include "dwmac1000.h"
17 #include "dwmac_dma.h"
18
dwmac1000_dma_axi(void __iomem * ioaddr,struct stmmac_axi * axi)19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
20 {
21 u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
22
23 pr_info("dwmac1000: Master AXI performs %s burst length\n",
24 !(value & DMA_AXI_UNDEF) ? "fixed" : "any");
25
26 if (axi->axi_lpi_en)
27 value |= DMA_AXI_EN_LPI;
28 if (axi->axi_xit_frm)
29 value |= DMA_AXI_LPI_XIT_FRM;
30
31 value = u32_replace_bits(value, axi->axi_wr_osr_lmt,
32 DMA_AXI_WR_OSR_LMT);
33 value = u32_replace_bits(value, axi->axi_rd_osr_lmt,
34 DMA_AXI_RD_OSR_LMT);
35
36 /* Depending on the UNDEF bit the Master AXI will perform any burst
37 * length according to the BLEN programmed (by default all BLEN are
38 * set). Note that the UNDEF bit is readonly, and is the inverse of
39 * Bus Mode bit 16.
40 */
41 value = (value & ~DMA_AXI_BLEN_MASK) | axi->axi_blen_regval;
42
43 writel(value, ioaddr + DMA_AXI_BUS_MODE);
44 }
45
dwmac1000_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)46 static void dwmac1000_dma_init_channel(struct stmmac_priv *priv,
47 void __iomem *ioaddr,
48 struct stmmac_dma_cfg *dma_cfg, u32 chan)
49 {
50 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
51 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
52 u32 value;
53
54 value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
55
56 /* Set the DMA PBL (Programmable Burst Length) mode.
57 *
58 * Note: before stmmac core 3.50 this mode bit was 4xPBL, and
59 * post 3.5 mode bit acts as 8*PBL.
60 */
61 if (dma_cfg->pblx8)
62 value |= DMA_BUS_MODE_MAXPBL;
63 value |= DMA_BUS_MODE_USP;
64 value = u32_replace_bits(value, txpbl, DMA_BUS_MODE_PBL_MASK);
65 value = u32_replace_bits(value, rxpbl, DMA_BUS_MODE_RPBL_MASK);
66
67 /* Set the Fixed burst mode */
68 if (dma_cfg->fixed_burst)
69 value |= DMA_BUS_MODE_FB;
70
71 /* Mixed Burst has no effect when fb is set */
72 if (dma_cfg->mixed_burst)
73 value |= DMA_BUS_MODE_MB;
74
75 if (dma_cfg->atds)
76 value |= DMA_BUS_MODE_ATDS;
77
78 if (dma_cfg->aal)
79 value |= DMA_BUS_MODE_AAL;
80
81 writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
82
83 /* Mask interrupts by writing to CSR7 */
84 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
85 }
86
dwmac1000_dma_init_rx(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_rx_phy,u32 chan)87 static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,
88 void __iomem *ioaddr,
89 struct stmmac_dma_cfg *dma_cfg,
90 dma_addr_t dma_rx_phy, u32 chan)
91 {
92 /* RX descriptor base address list must be written into DMA CSR3 */
93 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
94 }
95
dwmac1000_dma_init_tx(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_tx_phy,u32 chan)96 static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,
97 void __iomem *ioaddr,
98 struct stmmac_dma_cfg *dma_cfg,
99 dma_addr_t dma_tx_phy, u32 chan)
100 {
101 /* TX descriptor base address list must be written into DMA CSR4 */
102 writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
103 }
104
dwmac1000_configure_fc(u32 csr6,int rxfifosz)105 static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
106 {
107 csr6 &= ~DMA_CONTROL_RFA_MASK;
108 csr6 &= ~DMA_CONTROL_RFD_MASK;
109
110 /* Leave flow control disabled if receive fifo size is less than
111 * 4K or 0. Otherwise, send XOFF when fifo is 1K less than full,
112 * and send XON when 2K less than full.
113 */
114 if (rxfifosz < 4096) {
115 csr6 &= ~DMA_CONTROL_EFC;
116 pr_debug("GMAC: disabling flow control, rxfifo too small(%d)\n",
117 rxfifosz);
118 } else {
119 csr6 |= DMA_CONTROL_EFC;
120 csr6 |= RFA_FULL_MINUS_1K;
121 csr6 |= RFD_FULL_MINUS_2K;
122 }
123 return csr6;
124 }
125
dwmac1000_dma_operation_mode_rx(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)126 static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,
127 void __iomem *ioaddr, int mode,
128 u32 channel, int fifosz, u8 qmode)
129 {
130 u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
131
132 if (mode == SF_DMA_MODE) {
133 pr_debug("GMAC: enable RX store and forward mode\n");
134 csr6 |= DMA_CONTROL_RSF | DMA_CONTROL_DFF;
135 } else {
136 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
137 csr6 &= ~(DMA_CONTROL_RSF | DMA_CONTROL_DFF);
138 csr6 &= DMA_CONTROL_TC_RX_MASK;
139 if (mode <= 32)
140 csr6 |= DMA_CONTROL_RTC_32;
141 else if (mode <= 64)
142 csr6 |= DMA_CONTROL_RTC_64;
143 else if (mode <= 96)
144 csr6 |= DMA_CONTROL_RTC_96;
145 else
146 csr6 |= DMA_CONTROL_RTC_128;
147 }
148
149 /* Configure flow control based on rx fifo size */
150 csr6 = dwmac1000_configure_fc(csr6, fifosz);
151
152 writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
153 }
154
dwmac1000_dma_operation_mode_tx(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)155 static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,
156 void __iomem *ioaddr, int mode,
157 u32 channel, int fifosz, u8 qmode)
158 {
159 u32 csr6 = readl(ioaddr + DMA_CHAN_CONTROL(channel));
160
161 if (mode == SF_DMA_MODE) {
162 pr_debug("GMAC: enable TX store and forward mode\n");
163 /* Transmit COE type 2 cannot be done in cut-through mode. */
164 csr6 |= DMA_CONTROL_TSF;
165 /* Operating on second frame increase the performance
166 * especially when transmit store-and-forward is used.
167 */
168 csr6 |= DMA_CONTROL_OSF;
169 } else {
170 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
171 csr6 &= ~DMA_CONTROL_TSF;
172 csr6 &= DMA_CONTROL_TC_TX_MASK;
173 /* Set the transmit threshold */
174 if (mode <= 32)
175 csr6 |= DMA_CONTROL_TTC_32;
176 else if (mode <= 64)
177 csr6 |= DMA_CONTROL_TTC_64;
178 else if (mode <= 128)
179 csr6 |= DMA_CONTROL_TTC_128;
180 else if (mode <= 192)
181 csr6 |= DMA_CONTROL_TTC_192;
182 else
183 csr6 |= DMA_CONTROL_TTC_256;
184 }
185
186 writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
187 }
188
dwmac1000_dump_dma_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 * reg_space)189 static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,
190 void __iomem *ioaddr, u32 *reg_space)
191 {
192 int i;
193
194 for (i = 0; i < NUM_DWMAC1000_DMA_REGS; i++)
195 if ((i < 12) || (i > 17))
196 reg_space[DMA_BUS_MODE / 4 + i] =
197 readl(ioaddr + DMA_BUS_MODE + i * 4);
198 }
199
dwmac1000_get_hw_feature(void __iomem * ioaddr,struct dma_features * dma_cap)200 static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
201 struct dma_features *dma_cap)
202 {
203 u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
204
205 if (!hw_cap) {
206 /* 0x00000000 is the value read on old hardware that does not
207 * implement this register
208 */
209 return -EOPNOTSUPP;
210 }
211
212 dma_cap->mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
213 dma_cap->mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
214 dma_cap->half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
215 dma_cap->hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
216 dma_cap->multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
217 dma_cap->pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
218 dma_cap->sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
219 dma_cap->pmt_remote_wake_up = (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
220 dma_cap->pmt_magic_frame = (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
221 /* MMC */
222 dma_cap->rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
223 /* IEEE 1588-2002 */
224 dma_cap->time_stamp =
225 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
226 /* IEEE 1588-2008 */
227 dma_cap->atime_stamp = (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
228 /* 802.3az - Energy-Efficient Ethernet (EEE) */
229 dma_cap->eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
230 dma_cap->av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
231 /* TX and RX csum */
232 dma_cap->tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
233 dma_cap->rx_coe_type1 = (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
234 dma_cap->rx_coe_type2 = (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
235 dma_cap->rxfifo_over_2048 = (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
236 /* TX and RX number of channels */
237 dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
238 dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
239 /* Alternate (enhanced) DESC mode */
240 dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
241
242 dma_cap->actphyif = FIELD_GET(DMA_HW_FEAT_ACTPHYIF, hw_cap);
243
244 return 0;
245 }
246
dwmac1000_rx_watchdog(struct stmmac_priv * priv,void __iomem * ioaddr,u32 riwt,u32 queue)247 static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,
248 void __iomem *ioaddr, u32 riwt, u32 queue)
249 {
250 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
251 }
252
253 const struct stmmac_dma_ops dwmac1000_dma_ops = {
254 .reset = dwmac_dma_reset,
255 .init_chan = dwmac1000_dma_init_channel,
256 .init_rx_chan = dwmac1000_dma_init_rx,
257 .init_tx_chan = dwmac1000_dma_init_tx,
258 .axi = dwmac1000_dma_axi,
259 .dump_regs = dwmac1000_dump_dma_regs,
260 .dma_rx_mode = dwmac1000_dma_operation_mode_rx,
261 .dma_tx_mode = dwmac1000_dma_operation_mode_tx,
262 .enable_dma_transmission = dwmac_enable_dma_transmission,
263 .enable_dma_reception = dwmac_enable_dma_reception,
264 .enable_dma_irq = dwmac_enable_dma_irq,
265 .disable_dma_irq = dwmac_disable_dma_irq,
266 .start_tx = dwmac_dma_start_tx,
267 .stop_tx = dwmac_dma_stop_tx,
268 .start_rx = dwmac_dma_start_rx,
269 .stop_rx = dwmac_dma_stop_rx,
270 .dma_interrupt = dwmac_dma_interrupt,
271 .get_hw_feature = dwmac1000_get_hw_feature,
272 .rx_watchdog = dwmac1000_rx_watchdog,
273 };
274 EXPORT_SYMBOL_GPL(dwmac1000_dma_ops);
275