1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3 DWMAC DMA Header file.
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10
11 #ifndef __DWMAC_DMA_H__
12 #define __DWMAC_DMA_H__
13
14 /* DMA CRS Control and Status Register Mapping */
15 #define DMA_BUS_MODE 0x00001000 /* Bus Mode */
16
17 #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
18
19 #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
20 #define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
21 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
22 #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
23
24 #define DMA_STATUS 0x00001014 /* Status Register */
25 #define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
26 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
27 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
28 #define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */
29 #define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */
30 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
31 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
32 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
33 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
34 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
35 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
36 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
37 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
38 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
39 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
40 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
41 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
42 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
43 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
44 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
45
46 #define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
47 DMA_STATUS_AIS | \
48 DMA_STATUS_FBI)
49
50 #define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
51 DMA_STATUS_RWT | \
52 DMA_STATUS_RPS | \
53 DMA_STATUS_RU | \
54 DMA_STATUS_RI | \
55 DMA_STATUS_OVF | \
56 DMA_STATUS_MSK_COMMON)
57
58 #define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \
59 DMA_STATUS_UNF | \
60 DMA_STATUS_TJT | \
61 DMA_STATUS_TU | \
62 DMA_STATUS_TPS | \
63 DMA_STATUS_TI | \
64 DMA_STATUS_MSK_COMMON)
65
66 #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
67
68 /* DMA Control register defines */
69 #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
70 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
71 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
72
73 #define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
74
75 /* DMA Normal interrupt */
76 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
77 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
78 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
79
80 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
81 DMA_INTR_ENA_TIE)
82
83 /* DMA Abnormal interrupt */
84 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
85 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
86 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
87
88 #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
89 DMA_INTR_ENA_UNE)
90
91 /* DMA default interrupt mask */
92 #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
93 #define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
94 #define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
95
96 #define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
97
98 /* Following DMA defines are channels oriented */
99 #define DMA_CHAN_BASE_OFFSET 0x100
100
dma_chan_base_addr(u32 base,u32 chan)101 static inline u32 dma_chan_base_addr(u32 base, u32 chan)
102 {
103 return base + chan * DMA_CHAN_BASE_OFFSET;
104 }
105
106 #define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
107 #define DMA_CHAN_XMT_POLL_DEMAND(chan) \
108 dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
109 #define DMA_CHAN_RCV_POLL_DEMAND(chan) \
110 dma_chan_base_addr(DMA_RCV_POLL_DEMAND, chan)
111 #define DMA_CHAN_RCV_BASE_ADDR(chan) \
112 dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
113 #define DMA_CHAN_TX_BASE_ADDR(chan) \
114 dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
115 #define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
116 #define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
117 #define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
118 #define DMA_CHAN_RX_WATCHDOG(chan) \
119 dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
120
121
122 /* Rx watchdog register */
123 #define DMA_RX_WATCHDOG 0x00001024
124
125 /* AXI Master Bus Mode */
126 #define DMA_AXI_BUS_MODE 0x00001028
127
128 #define DMA_AXI_EN_LPI BIT(31)
129 #define DMA_AXI_LPI_XIT_FRM BIT(30)
130 #define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
131 #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
132
133 #define DMA_AXI_1KBBE BIT(13)
134
135 #define DMA_AXI_UNDEF BIT(0)
136
137 #define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
138 #define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
139 #define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
140
141 #define NUM_DWMAC100_DMA_REGS 9
142 #define NUM_DWMAC1000_DMA_REGS 23
143 #define NUM_DWMAC4_DMA_REGS 27
144
145 void dwmac_enable_dma_transmission(void __iomem *ioaddr, u32 chan);
146 void dwmac_enable_dma_reception(void __iomem *ioaddr, u32 chan);
147 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
148 u32 chan, bool rx, bool tx);
149 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
150 u32 chan, bool rx, bool tx);
151 void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
152 u32 chan);
153 void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
154 u32 chan);
155 void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
156 u32 chan);
157 void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
158 u32 chan);
159 int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
160 struct stmmac_extra_stats *x, u32 chan, u32 dir);
161 int dwmac_dma_reset(void __iomem *ioaddr);
162
163 #endif /* __DWMAC_DMA_H__ */
164