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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 1171) sorted by relevance

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/linux/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/
H A Dia_css_eed1_8_param.h40 #define EED1_8_STATE_INPUT_BUFFER_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
44 #define EED1_8_STATE_LD_H_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
48 #define EED1_8_STATE_LD_V_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
52 #define EED1_8_STATE_D_HR_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
56 #define EED1_8_STATE_D_HB_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
60 #define EED1_8_STATE_D_VR_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
64 #define EED1_8_STATE_D_VB_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
68 #define EED1_8_STATE_RB_ZIPPED_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
77 #define EED1_8_STATE_CG_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
81 #define EED1_8_STATE_CO_WIDTH DIV_ROUND_UP(MAX_FRAME_SIMDWIDTH, 2)
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c248 DIV_ROUND_UP(priv->config.clk_trail, temp) | in phy_meson_axg_mipi_dphy_power_on()
249 (DIV_ROUND_UP(priv->config.clk_post + in phy_meson_axg_mipi_dphy_power_on()
251 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
252 (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24)); in phy_meson_axg_mipi_dphy_power_on()
254 DIV_ROUND_UP(priv->config.clk_pre, BITS_PER_BYTE)); in phy_meson_axg_mipi_dphy_power_on()
257 DIV_ROUND_UP(priv->config.hs_exit, temp) | in phy_meson_axg_mipi_dphy_power_on()
258 (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) | in phy_meson_axg_mipi_dphy_power_on()
259 (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
260 (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24)); in phy_meson_axg_mipi_dphy_power_on()
263 DIV_ROUND_UP(priv->config.lpx, temp) | in phy_meson_axg_mipi_dphy_power_on()
[all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_opr_v6.h20 #define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, 16)
21 #define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, 16)
24 #define S5P_MFC_LCU_WIDTH(x_size) DIV_ROUND_UP(x_size, 32)
25 #define S5P_MFC_LCU_HEIGHT(y_size) DIV_ROUND_UP(y_size, 32)
28 (DIV_ROUND_UP(x, 64) * DIV_ROUND_UP(y, 64) * 256 + 512)
H A Dregs-mfc-v10.h69 + ((y * 64) + 1280) * DIV_ROUND_UP(x, 8))
73 + (DIV_ROUND_UP(x * y, 64) * 32))
77 + (DIV_ROUND_UP(x * y, 128) * 16))
84 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
H A Dregs-mfc-v8.h114 ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \
115 + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16))
/linux/include/linux/
H A Drcu_node_tree.h64 # define NUM_RCU_LVL_1 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_1)
72 # define NUM_RCU_LVL_1 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_2)
73 # define NUM_RCU_LVL_2 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_1)
81 # define NUM_RCU_LVL_1 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_3)
82 # define NUM_RCU_LVL_2 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_2)
83 # define NUM_RCU_LVL_3 DIV_ROUND_UP(NR_CPUS, RCU_FANOUT_1)
/linux/drivers/gpu/drm/tests/
H A Ddrm_framebuffer_test.c218 .handles = { 1, 1, 1 }, .pitches = { MAX_WIDTH, DIV_ROUND_UP(MAX_WIDTH, 2),
219 DIV_ROUND_UP(MAX_WIDTH, 2) },
224 .handles = { 1, 1, 1 }, .pitches = { MAX_WIDTH, DIV_ROUND_UP(MAX_WIDTH, 2) - 1,
225 DIV_ROUND_UP(MAX_WIDTH, 2) },
230 .handles = { 1, 1, 1 }, .pitches = { MAX_WIDTH, DIV_ROUND_UP(MAX_WIDTH, 2) + 1,
231 DIV_ROUND_UP(MAX_WIDTH, 2) + 7 },
238 .pitches = { MAX_WIDTH, DIV_ROUND_UP(MAX_WIDTH, 2) + 1,
239 DIV_ROUND_UP(MAX_WIDTH, 2) + 7 },
246 .pitches = { MAX_WIDTH, DIV_ROUND_UP(MAX_WIDTH, 2), DIV_ROUND_UP(MAX_WIDTH, 2) },
254 .pitches = { MAX_WIDTH, DIV_ROUND_UP(MAX_WIDTH, 2), DIV_ROUND_UP(MAX_WIDTH, 2) },
[all …]
/linux/drivers/media/platform/allegro-dvt/
H A Dnal-h264.c39 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_h264_write_start_code_prefix()
42 if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) { in nal_h264_write_start_code_prefix()
57 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_h264_read_start_code_prefix()
60 if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) { in nal_h264_read_start_code_prefix()
75 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_h264_write_filler_data()
79 i = rbsp->size - DIV_ROUND_UP(rbsp->pos, 8) - 1; in nal_h264_write_filler_data()
86 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_h264_read_filler_data()
89 if (DIV_ROUND_UP(rbsp->pos, 8) > rbsp->size) { in nal_h264_read_filler_data()
379 return DIV_ROUND_UP(rbsp.pos, 8); in nal_h264_write_sps()
426 return DIV_ROUND_UP(rbsp.pos, 8); in nal_h264_read_sps()
[all …]
H A Dnal-hevc.c40 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_hevc_write_start_code_prefix()
43 if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) { in nal_hevc_write_start_code_prefix()
58 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_hevc_read_start_code_prefix()
61 if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) { in nal_hevc_read_start_code_prefix()
76 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_hevc_write_filler_data()
80 i = rbsp->size - DIV_ROUND_UP(rbsp->pos, 8) - 1; in nal_hevc_write_filler_data()
87 u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); in nal_hevc_read_filler_data()
90 if (DIV_ROUND_UP(rbsp->pos, 8) > rbsp->size) { in nal_hevc_read_filler_data()
548 return DIV_ROUND_UP(rbsp.pos, 8); in nal_hevc_write_vps()
596 return DIV_ROUND_UP(rbsp.pos, 8); in nal_hevc_read_vps()
[all …]
/linux/drivers/ssb/
H A Ddriver_extif.c94 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; in ssb_extif_timing_init()
95 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; in ssb_extif_timing_init()
96 tmp |= DIV_ROUND_UP(120, ns); in ssb_extif_timing_init()
100 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; in ssb_extif_timing_init()
101 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; in ssb_extif_timing_init()
102 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; in ssb_extif_timing_init()
103 tmp |= DIV_ROUND_UP(120, ns); in ssb_extif_timing_init()
H A Ddriver_chipcommon.c443 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ in ssb_chipco_timing_init()
444 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ in ssb_chipco_timing_init()
445 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ in ssb_chipco_timing_init()
449 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ in ssb_chipco_timing_init()
450 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ in ssb_chipco_timing_init()
451 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ in ssb_chipco_timing_init()
462 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ in ssb_chipco_timing_init()
463 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ in ssb_chipco_timing_init()
464 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ in ssb_chipco_timing_init()
465 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ in ssb_chipco_timing_init()
/linux/drivers/staging/media/atomisp/pci/
H A Dsh_css_param_dvs.h25 #define DVS_NUM_BLOCKS_X(X) round_up(DIV_ROUND_UP((X), DVS_BLOCKDIM_X), 2)
26 #define DVS_NUM_BLOCKS_X_CHROMA(X) DIV_ROUND_UP((X), DVS_BLOCKDIM_X)
30 #define DVS_NUM_BLOCKS_Y(X) DIV_ROUND_UP((X), DVS_BLOCKDIM_Y_LUMA)
31 #define DVS_NUM_BLOCKS_Y_CHROMA(X) DIV_ROUND_UP((X), DVS_BLOCKDIM_Y_CHROMA)
/linux/drivers/irqchip/
H A Dirq-gic.c77 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
78 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
79 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
80 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
565 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) in gic_dist_save()
569 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) in gic_dist_save()
573 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) in gic_dist_save()
577 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) in gic_dist_save()
606 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) in gic_dist_restore()
610 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) in gic_dist_restore()
[all …]
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c238 val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2; in dphy_timing_config()
246 val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1; in dphy_timing_config()
250 val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1; in dphy_timing_config()
256 val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff) in dphy_timing_config()
259 val[DATA] = DIV_ROUND_UP(range[L] * factor in dphy_timing_config()
267 val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck); in dphy_timing_config()
269 val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2; in dphy_timing_config()
275 val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2; in dphy_timing_config()
282 val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2; in dphy_timing_config()
/linux/arch/s390/include/asm/
H A Dftrace.lds.h2 #ifndef DIV_ROUND_UP
3 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
9 DIV_ROUND_UP(SIZEOF_FTRACE_HOTPATCH_TRAMPOLINE * (n), \
/linux/lib/dim/
H A Ddim.c72 curr_stats->ppms = DIV_ROUND_UP(npkts * USEC_PER_MSEC, delta_us); in dim_calc_stats()
73 curr_stats->bpms = DIV_ROUND_UP(nbytes * USEC_PER_MSEC, delta_us); in dim_calc_stats()
74 curr_stats->epms = DIV_ROUND_UP(DIM_NEVENTS * USEC_PER_MSEC, in dim_calc_stats()
76 curr_stats->cpms = DIV_ROUND_UP(ncomps * USEC_PER_MSEC, delta_us); in dim_calc_stats()
/linux/drivers/media/i2c/
H A Dccs-pll.c268 DIV_ROUND_UP(min_vt_div, in ccs_pll_find_vt_sys_div()
281 DIV_ROUND_UP(max_vt_div, in ccs_pll_find_vt_sys_div()
285 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, in ccs_pll_find_vt_sys_div()
312 more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz, in __ccs_pll_calculate_vt_tree()
316 more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul); in __ccs_pll_calculate_vt_tree()
409 DIV_ROUND_UP(pll->ext_clk_freq_hz, in ccs_pll_calculate_vt_tree()
509 DIV_ROUND_UP(pll->bits_per_pixel in ccs_pll_calculate_vt()
522 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, in ccs_pll_calculate_vt()
533 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, in ccs_pll_calculate_vt()
554 pix_div = DIV_ROUND_UP(vt_div, sys_div); in ccs_pll_calculate_vt()
[all …]
/linux/tools/include/linux/
H A Dbitops.h18 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(long))
19 #define BITS_TO_U64(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(u64))
20 #define BITS_TO_U32(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(u32))
21 #define BITS_TO_BYTES(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(char))
/linux/arch/arm/mach-omap2/
H A Dpmic-cpcap.c47 return DIV_ROUND_UP(uv - 600000, 12500); in omap_cpcap_uv_to_vsel()
111 return DIV_ROUND_UP(uv - 770000, 10000); in omap_max8952_uv_to_vsel()
179 vsel = DIV_ROUND_UP(uv - 750000, 12500); in omap_fan535503_uv_to_vsel()
198 vsel = DIV_ROUND_UP(uv - 750000, 12500); in omap_fan535508_uv_to_vsel()
/linux/drivers/i2c/busses/
H A Di2c-rk3x.c616 min_high_ns = max(min_high_ns, DIV_ROUND_UP( in rk3x_i2c_v0_calc_timings()
618 min_high_ns = max(min_high_ns, DIV_ROUND_UP( in rk3x_i2c_v0_calc_timings()
627 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); in rk3x_i2c_v0_calc_timings()
634 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); in rk3x_i2c_v0_calc_timings()
637 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); in rk3x_i2c_v0_calc_timings()
638 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); in rk3x_i2c_v0_calc_timings()
673 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, in rk3x_i2c_v0_calc_timings()
781 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); in rk3x_i2c_v1_calc_timings()
783 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); in rk3x_i2c_v1_calc_timings()
786 min_high_div = DIV_ROUND_UP(clk_rate_kh in rk3x_i2c_v1_calc_timings()
[all...]
/linux/drivers/net/ethernet/mscc/
H A Docelot_police.c53 cir = DIV_ROUND_UP(cir, 100); in qos_policer_conf_set()
55 cbs = DIV_ROUND_UP(cbs, 4096); in qos_policer_conf_set()
67 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
69 pbs = DIV_ROUND_UP(pbs, 4096); in qos_policer_conf_set()
77 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
/linux/kernel/module/
H A Dstats.c332 DIV_ROUND_UP(total_size, live_mod_count)); in read_file_mod_stats()
337 DIV_ROUND_UP(text_size, live_mod_count)); in read_file_mod_stats()
350 DIV_ROUND_UP(ikread_bytes, fkreads)); in read_file_mod_stats()
356 DIV_ROUND_UP(ibecoming_bytes, fbecoming)); in read_file_mod_stats()
362 DIV_ROUND_UP(idecompress_bytes, fdecompress)); in read_file_mod_stats()
368 DIV_ROUND_UP(imod_bytes, floads)); in read_file_mod_stats()
/linux/drivers/pwm/
H A Dpwm-img.c105 output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns); in img_pwm_config()
107 mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz); in img_pwm_config()
110 timebase = DIV_ROUND_UP(mul, 1); in img_pwm_config()
113 timebase = DIV_ROUND_UP(mul, 8); in img_pwm_config()
116 timebase = DIV_ROUND_UP(mul, 64); in img_pwm_config()
119 timebase = DIV_ROUND_UP(mul, 512); in img_pwm_config()
126 duty = DIV_ROUND_UP(timebase * duty_ns, period_ns); in img_pwm_config()
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Daso.h11 (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_BB))
13 (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe_data), MLX5_SEND_WQE_BB))
16 #define MLX5_MACSEC_ASO_DS_CNT (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_DS))
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c187 m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul); in dss_pll_hsdiv_calc_a()
221 n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul); in dss_pll_calc_a()
238 m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2), in dss_pll_calc_a()
284 n = DIV_ROUND_UP(clkin, hw->fint_max); in dss_pll_calc_b()
289 m2 = DIV_ROUND_UP(min_dco, target_clkout); in dss_pll_calc_b()
310 sd = DIV_ROUND_UP(fint * m, 250000000); in dss_pll_calc_b()
460 sleep_time = DIV_ROUND_UP(1000*1000*1000, cinfo->fint); in dss_pll_write_config_type_a()

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