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Searched refs:DCCEnable (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h338 bool DCCEnable[],
436 bool DCCEnable,
511 bool DCCEnable,
791 bool DCCEnable,
901 bool DCCEnable[],
952 bool DCCEnable[],
1039 bool DCCEnable[],
H A Ddisplay_mode_vba_util_32.c1774 bool DCCEnable[], in dml32_CalculateSurfaceSizeInMall() argument
1832 if (DCCEnable[k] == true) { in dml32_CalculateSurfaceSizeInMall()
1876 if (DCCEnable[k] == true) { in dml32_CalculateSurfaceSizeInMall()
2022 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2096 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2225 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2264 bool DCCEnable, in dml32_CalculateVMAndRowBytes() argument
2372 if (DCCEnable != true) { in dml32_CalculateVMAndRowBytes()
2402 dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable); in dml32_CalculateVMAndRowBytes()
2671 bool DCCEnable, in dml32_CalculateRowBandwidth() argument
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H A Ddisplay_mode_vba_32.c390 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
439 …ersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
574 if (mode_lib->vba.DCCEnable[k]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
779 …refetchParametersWatermarksAndPerformanceCalculation.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1056 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1298 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1349 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1392 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1556 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1620 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c104 bool DCCEnable,
172 bool DCCEnable,
235 bool DCCEnable,
267 bool DCCEnable,
311 bool DCCEnable[],
428 bool DCCEnable[],
657 bool DCCEnable, in CalculatePrefetchSchedule() argument
796 } else if (!DCCEnable) in CalculatePrefetchSchedule()
827 if ((GPUVMEnable == true || DCCEnable == true)) { in CalculatePrefetchSchedule()
923 if ((GPUVMEnable == true || DCCEnable == true)) { in CalculatePrefetchSchedule()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c58 unsigned int DCCEnable; member
154 bool DCCEnable,
198 bool DCCEnable,
231 bool DCCEnable,
378 bool DCCEnable[],
427 bool DCCEnable[],
470 bool DCCEnable[],
904 } else if (!myPipe->DCCEnable) in CalculatePrefetchSchedule()
925 if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) { in CalculatePrefetchSchedule()
1067 if ((v->GPUVMEnable || myPipe->DCCEnable)) { in CalculatePrefetchSchedule()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c78 unsigned int DCCEnable; member
209 bool DCCEnable,
249 bool DCCEnable,
419 bool DCCEnable[],
468 bool DCCEnable[],
527 bool DCCEnable[],
1047 if (!myPipe->DCCEnable) {
1064 } else if (!myPipe->DCCEnable) {
1102 if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
1271 if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c80 unsigned int DCCEnable; member
200 bool DCCEnable,
240 bool DCCEnable,
410 bool DCCEnable[],
459 bool DCCEnable[],
518 bool DCCEnable[],
1029 if (!myPipe->DCCEnable) {
1046 } else if (!myPipe->DCCEnable) {
1084 if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
1253 if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c83 bool DCCEnable,
134 bool DCCEnable,
183 bool DCCEnable,
212 bool DCCEnable,
466 bool DCCEnable, in CalculatePrefetchSchedule()
589 } else if (DCCEnable) in CalculatePrefetchSchedule()
618 if ((GPUVMEnable == true || DCCEnable == true)) { in CalculatePrefetchSchedule()
680 if ((GPUVMEnable == true || DCCEnable == true)) { in CalculatePrefetchSchedule()
710 || DCCEnable) ? in CalculatePrefetchSchedule()
858 bool DCCEnable, in CalculateVMAndRowBytes() argument
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H A Ddisplay_mode_vba_20v2.c108 bool DCCEnable,
158 bool DCCEnable,
207 bool DCCEnable,
236 bool DCCEnable,
558 bool DCCEnable, in CalculatePrefetchSchedule() argument
649 } else if (DCCEnable) in CalculatePrefetchSchedule()
678 if ((GPUVMEnable == true || DCCEnable == true)) { in CalculatePrefetchSchedule()
740 if ((GPUVMEnable == true || DCCEnable == true)) { in CalculatePrefetchSchedule()
770 || DCCEnable) ? in CalculatePrefetchSchedule()
918 bool DCCEnable, in CalculateVMAndRowBytes() argument
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core.c235 dml_bool_t DCCEnable,
296 dml_bool_t DCCEnable,
329 dml_bool_t DCCEnable,
505 dml_bool_t DCCEnable[],
556 dml_bool_t DCCEnable[],
670 dml_bool_t DCCEnable[],
1048 dml_print("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable); in CalculatePrefetchSchedule()
1161 } else if (p->GPUVMPageTableLevels == 1 && p->myPipe->DCCEnable != true) { in CalculatePrefetchSchedule()
1167 } else if (p->myPipe->DCCEnable == true) { in CalculatePrefetchSchedule()
1206 if ((p->GPUVMEnable == true || p->myPipe->DCCEnable == true)) { in CalculatePrefetchSchedule()
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H A Ddml2_utils.c106 dml_surface_array->DCCEnable[dst_index] = dml_surface_array->DCCEnable[src_index]; in dml2_util_copy_dml_surface()
H A Ddisplay_mode_core_structs.h469 dml_bool_t DCCEnable; member
591 dml_bool_t DCCEnable[__DML_NUM_PLANES__]; member
1568 dml_bool_t *DCCEnable; member
H A Ddml2_translation_helper.c903 out->DCCEnable[location] = false; in populate_dummy_dml_surface_cfg()
922 out->DCCEnable[location] = in->dcc.enable; in populate_dml_surface_cfg_from_plane_state()
H A Ddisplay_mode_util.c600 dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n", i, surface->DCCEnable[i]); in dml_print_dml_display_cfg_surface()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h117 bool DCCEnable; member
H A Ddisplay_mode_vba.h478 bool DCCEnable[DC__NUM_DPP__MAX]; member
H A Ddisplay_mode_vba.c609 mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c1642 if (!p->DCCEnable || !p->mrq_present) { in CalculateVMAndRowBytes()
1686 DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p->DCCEnable); in CalculateVMAndRowBytes()
1908 bool DCCEnable, in CalculateRowBandwidth() argument
1925 if (!DCCEnable || !mrq_present) { in CalculateRowBandwidth()
2892 scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable; in CalculateVMRowAndSwath()
2970 scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable; in CalculateVMRowAndSwath()
3148 p->myPipe[k].DCCEnable, in CalculateVMRowAndSwath()
5164 DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable); in CalculatePrefetchSchedule()
7456 myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_ms_prefetch_check()
8934 s->SurfParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_mode_support()
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