Searched refs:DBC (Results 1 – 6 of 6) sorted by relevance
5 Description: Represents the current state of DMA Bridge channel (DBC). Below are the possible9 IDLE (0) DBC is free and can be activated10 ASSIGNED (1) DBC is activated and a workload is running on device19 Users: Any userspace application or clients interested in DBC state.
244 (DBC for short) is solely for the use of that workload and is not shared with247 Each DBC is a pair of FIFOs that manage data in and out of the workload. One250 Each DBC contains 4 registers in hardware:265 DBC registers are exposed to the host via the second BAR. Each DBC consumes271 memory must be provided per DBC, which hosts both FIFOs. The request FIFO will411 response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation452 used by the DBC.490 channel. This notification identifies the workload by its assigned DBC. A492 DBC/NSPs into a working state.499 When SSR occurs for a specific NSP, the assigned DBC goes through the
53 interrupt handlers for every DBC and MHI wake up for every interrupt that54 arrives; however, the DBC threaded irq handlers only are started when work to be57 If the DBC is configured to force MSI interrupts, this can circumvent the124 DMA Bridge, and as such, locks the BO to a specific DBC.166 workload should be allowed to interface with the DBC.
226 if (PSP_FEATURE(psp, DBC) || in psp_init()
453 DBC = 0x38, enumerator
1072 AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - DBC SUPPORT