1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
3 #ifndef __CXL_MEM_H__
4 #define __CXL_MEM_H__
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/pci.h>
7 #include <linux/cdev.h>
8 #include <linux/uuid.h>
9 #include <linux/node.h>
10 #include <cxl/event.h>
11 #include <cxl/mailbox.h>
12 #include "cxl.h"
13
14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
15 #define CXLMDEV_STATUS_OFFSET 0x0
16 #define CXLMDEV_DEV_FATAL BIT(0)
17 #define CXLMDEV_FW_HALT BIT(1)
18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
19 #define CXLMDEV_MS_NOT_READY 0
20 #define CXLMDEV_MS_READY 1
21 #define CXLMDEV_MS_ERROR 2
22 #define CXLMDEV_MS_DISABLED 3
23 #define CXLMDEV_READY(status) \
24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
25 CXLMDEV_MS_READY)
26 #define CXLMDEV_MBOX_IF_READY BIT(4)
27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
28 #define CXLMDEV_RESET_NEEDED_NOT 0
29 #define CXLMDEV_RESET_NEEDED_COLD 1
30 #define CXLMDEV_RESET_NEEDED_WARM 2
31 #define CXLMDEV_RESET_NEEDED_HOT 3
32 #define CXLMDEV_RESET_NEEDED_CXL 4
33 #define CXLMDEV_RESET_NEEDED(status) \
34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
35 CXLMDEV_RESET_NEEDED_NOT)
36
37 struct cxl_memdev_attach {
38 int (*probe)(struct cxl_memdev *cxlmd);
39 };
40
41 /**
42 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
43 * @dev: driver core device object
44 * @cdev: char dev core object for ioctl operations
45 * @cxlds: The device state backing this device
46 * @detach_work: active memdev lost a port in its ancestry
47 * @cxl_nvb: coordinate removal of @cxl_nvd if present
48 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
49 * @endpoint: connection to the CXL port topology for this memory device
50 * @attach: creator of this memdev depends on CXL link attach to operate
51 * @id: id number of this memdev instance.
52 * @depth: endpoint port depth
53 * @scrub_cycle: current scrub cycle set for this device
54 * @scrub_region_id: id number of a backed region (if any) for which current scrub cycle set
55 * @err_rec_array: List of xarrarys to store the memdev error records to
56 * check attributes for a memory repair operation are from
57 * current boot.
58 */
59 struct cxl_memdev {
60 struct device dev;
61 struct cdev cdev;
62 struct cxl_dev_state *cxlds;
63 struct work_struct detach_work;
64 struct cxl_nvdimm_bridge *cxl_nvb;
65 struct cxl_nvdimm *cxl_nvd;
66 struct cxl_port *endpoint;
67 const struct cxl_memdev_attach *attach;
68 int id;
69 int depth;
70 u8 scrub_cycle;
71 int scrub_region_id;
72 struct cxl_mem_err_rec *err_rec_array;
73 };
74
to_cxl_memdev(struct device * dev)75 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
76 {
77 return container_of(dev, struct cxl_memdev, dev);
78 }
79
cxled_to_port(struct cxl_endpoint_decoder * cxled)80 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
81 {
82 return to_cxl_port(cxled->cxld.dev.parent);
83 }
84
cxlrd_to_port(struct cxl_root_decoder * cxlrd)85 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
86 {
87 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
88 }
89
90 static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder * cxled)91 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
92 {
93 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
94
95 return to_cxl_memdev(port->uport_dev);
96 }
97
98 bool is_cxl_memdev(const struct device *dev);
is_cxl_endpoint(struct cxl_port * port)99 static inline bool is_cxl_endpoint(struct cxl_port *port)
100 {
101 return is_cxl_memdev(port->uport_dev);
102 }
103
104 struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds,
105 const struct cxl_memdev_attach *attach);
106 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds,
107 const struct cxl_memdev_attach *attach);
108 int devm_cxl_sanitize_setup_notifier(struct device *host,
109 struct cxl_memdev *cxlmd);
110 struct cxl_memdev_state;
111 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds);
112 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
113 resource_size_t base, resource_size_t len,
114 resource_size_t skipped);
115
116 #define CXL_NR_PARTITIONS_MAX 2
117
118 struct cxl_dpa_info {
119 u64 size;
120 struct cxl_dpa_part_info {
121 struct range range;
122 enum cxl_partition_mode mode;
123 } part[CXL_NR_PARTITIONS_MAX];
124 int nr_partitions;
125 };
126
127 int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
128
cxl_ep_load(struct cxl_port * port,struct cxl_memdev * cxlmd)129 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
130 struct cxl_memdev *cxlmd)
131 {
132 if (!port)
133 return NULL;
134
135 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
136 }
137
138 /*
139 * Per CXL 3.0 Section 8.2.8.4.5.1
140 */
141 #define CMD_CMD_RC_TABLE \
142 C(SUCCESS, 0, NULL), \
143 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
144 C(INPUT, -ENXIO, "cmd input was invalid"), \
145 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
146 C(INTERNAL, -ENXIO, "internal device error"), \
147 C(RETRY, -ENXIO, "temporary error, retry once"), \
148 C(BUSY, -ENXIO, "ongoing background operation"), \
149 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
150 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
151 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
152 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
153 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
154 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
155 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
156 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
157 C(PADDR, -EFAULT, "physical address specified is invalid"), \
158 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \
159 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
160 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
161 C(SECURITY, -ENXIO, "not valid in the current security state"), \
162 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
163 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
164 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \
165 C(LOG, -ENXIO, "invalid or unsupported log page"), \
166 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \
167 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \
168 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \
169 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \
170 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \
171 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \
172 C(EXTLIST, -ENXIO, "invalid Extent List"), \
173
174 #undef C
175 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
176 enum { CMD_CMD_RC_TABLE };
177 #undef C
178 #define C(a, b, c) { b, c }
179 struct cxl_mbox_cmd_rc {
180 int err;
181 const char *desc;
182 };
183
184 static const
185 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
186 #undef C
187
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)188 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
189 {
190 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
191 }
192
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)193 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
194 {
195 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
196 }
197
198 /*
199 * CXL 2.0 - Memory capacity multiplier
200 * See Section 8.2.9.5
201 *
202 * Volatile, Persistent, and Partition capacities are specified to be in
203 * multiples of 256MB - define a multiplier to convert to/from bytes.
204 */
205 #define CXL_CAPACITY_MULTIPLIER SZ_256M
206
207 /*
208 * Event Interrupt Policy
209 *
210 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
211 */
212 enum cxl_event_int_mode {
213 CXL_INT_NONE = 0x00,
214 CXL_INT_MSI_MSIX = 0x01,
215 CXL_INT_FW = 0x02
216 };
217 struct cxl_event_interrupt_policy {
218 u8 info_settings;
219 u8 warn_settings;
220 u8 failure_settings;
221 u8 fatal_settings;
222 } __packed;
223
224 /**
225 * struct cxl_event_state - Event log driver state
226 *
227 * @buf: Buffer to receive event data
228 * @log_lock: Serialize event_buf and log use
229 */
230 struct cxl_event_state {
231 struct cxl_get_event_payload *buf;
232 struct mutex log_lock;
233 };
234
235 /* Device enabled poison commands */
236 enum poison_cmd_enabled_bits {
237 CXL_POISON_ENABLED_LIST,
238 CXL_POISON_ENABLED_INJECT,
239 CXL_POISON_ENABLED_CLEAR,
240 CXL_POISON_ENABLED_SCAN_CAPS,
241 CXL_POISON_ENABLED_SCAN_MEDIA,
242 CXL_POISON_ENABLED_SCAN_RESULTS,
243 CXL_POISON_ENABLED_MAX
244 };
245
246 /* Device enabled security commands */
247 enum security_cmd_enabled_bits {
248 CXL_SEC_ENABLED_SANITIZE,
249 CXL_SEC_ENABLED_SECURE_ERASE,
250 CXL_SEC_ENABLED_GET_SECURITY_STATE,
251 CXL_SEC_ENABLED_SET_PASSPHRASE,
252 CXL_SEC_ENABLED_DISABLE_PASSPHRASE,
253 CXL_SEC_ENABLED_UNLOCK,
254 CXL_SEC_ENABLED_FREEZE_SECURITY,
255 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE,
256 CXL_SEC_ENABLED_MAX
257 };
258
259 /**
260 * struct cxl_poison_state - Driver poison state info
261 *
262 * @max_errors: Maximum media error records held in device cache
263 * @enabled_cmds: All poison commands enabled in the CEL
264 * @list_out: The poison list payload returned by device
265 * @mutex: Protect reads of the poison list
266 *
267 * Reads of the poison list are synchronized to ensure that a reader
268 * does not get an incomplete list because their request overlapped
269 * (was interrupted or preceded by) another read request of the same
270 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1
271 */
272 struct cxl_poison_state {
273 u32 max_errors;
274 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX);
275 struct cxl_mbox_poison_out *list_out;
276 struct mutex mutex; /* Protect reads of poison list */
277 };
278
279 /*
280 * Get FW Info
281 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56
282 */
283 struct cxl_mbox_get_fw_info {
284 u8 num_slots;
285 u8 slot_info;
286 u8 activation_cap;
287 u8 reserved[13];
288 char slot_1_revision[16];
289 char slot_2_revision[16];
290 char slot_3_revision[16];
291 char slot_4_revision[16];
292 } __packed;
293
294 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)
295 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)
296 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3
297 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0)
298
299 /*
300 * Transfer FW Input Payload
301 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57
302 */
303 struct cxl_mbox_transfer_fw {
304 u8 action;
305 u8 slot;
306 u8 reserved[2];
307 __le32 offset;
308 u8 reserved2[0x78];
309 u8 data[];
310 } __packed;
311
312 #define CXL_FW_TRANSFER_ACTION_FULL 0x0
313 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1
314 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2
315 #define CXL_FW_TRANSFER_ACTION_END 0x3
316 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4
317
318 /*
319 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages
320 * and for each part transferred in a Transfer FW command.
321 */
322 #define CXL_FW_TRANSFER_ALIGNMENT 128
323
324 /*
325 * Activate FW Input Payload
326 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58
327 */
328 struct cxl_mbox_activate_fw {
329 u8 action;
330 u8 slot;
331 } __packed;
332
333 #define CXL_FW_ACTIVATE_ONLINE 0x0
334 #define CXL_FW_ACTIVATE_OFFLINE 0x1
335
336 /* FW state bits */
337 #define CXL_FW_STATE_BITS 32
338 #define CXL_FW_CANCEL 0
339
340 /**
341 * struct cxl_fw_state - Firmware upload / activation state
342 *
343 * @state: fw_uploader state bitmask
344 * @oneshot: whether the fw upload fits in a single transfer
345 * @num_slots: Number of FW slots available
346 * @cur_slot: Slot number currently active
347 * @next_slot: Slot number for the new firmware
348 */
349 struct cxl_fw_state {
350 DECLARE_BITMAP(state, CXL_FW_STATE_BITS);
351 bool oneshot;
352 int num_slots;
353 int cur_slot;
354 int next_slot;
355 };
356
357 /**
358 * struct cxl_security_state - Device security state
359 *
360 * @state: state of last security operation
361 * @enabled_cmds: All security commands enabled in the CEL
362 * @poll_tmo_secs: polling timeout
363 * @sanitize_active: sanitize completion pending
364 * @poll_dwork: polling work item
365 * @sanitize_node: sanitation sysfs file to notify
366 */
367 struct cxl_security_state {
368 unsigned long state;
369 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX);
370 int poll_tmo_secs;
371 bool sanitize_active;
372 struct delayed_work poll_dwork;
373 struct kernfs_node *sanitize_node;
374 };
375
376 /*
377 * enum cxl_devtype - delineate type-2 from a generic type-3 device
378 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
379 * HDM-DB, no requirement that this device implements a
380 * mailbox, or other memory-device-standard manageability
381 * flows.
382 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
383 * HDM-H and class-mandatory memory device registers
384 */
385 enum cxl_devtype {
386 CXL_DEVTYPE_DEVMEM,
387 CXL_DEVTYPE_CLASSMEM,
388 };
389
390 /**
391 * struct cxl_dpa_perf - DPA performance property entry
392 * @dpa_range: range for DPA address
393 * @coord: QoS performance data (i.e. latency, bandwidth)
394 * @cdat_coord: raw QoS performance data from CDAT
395 * @qos_class: QoS Class cookies
396 */
397 struct cxl_dpa_perf {
398 struct range dpa_range;
399 struct access_coordinate coord[ACCESS_COORDINATE_MAX];
400 struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
401 int qos_class;
402 };
403
404 /**
405 * struct cxl_dpa_partition - DPA partition descriptor
406 * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
407 * @perf: performance attributes of the partition from CDAT
408 * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
409 */
410 struct cxl_dpa_partition {
411 struct resource res;
412 struct cxl_dpa_perf perf;
413 enum cxl_partition_mode mode;
414 };
415
416 /**
417 * struct cxl_dev_state - The driver device state
418 *
419 * cxl_dev_state represents the CXL driver/device state. It provides an
420 * interface to mailbox commands as well as some cached data about the device.
421 * Currently only memory devices are represented.
422 *
423 * @dev: The device associated with this CXL state
424 * @cxlmd: The device representing the CXL.mem capabilities of @dev
425 * @reg_map: component and ras register mapping parameters
426 * @regs: Class device "Device" registers
427 * @cxl_dvsec: Offset to the PCIe device DVSEC
428 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
429 * @media_ready: Indicate whether the device media is usable
430 * @dpa_res: Overall DPA resource tree for the device
431 * @part: DPA partition array
432 * @nr_partitions: Number of DPA partitions
433 * @serial: PCIe Device Serial Number
434 * @type: Generic Memory Class device or Vendor Specific Memory device
435 * @cxl_mbox: CXL mailbox context
436 * @cxlfs: CXL features context
437 */
438 struct cxl_dev_state {
439 struct device *dev;
440 struct cxl_memdev *cxlmd;
441 struct cxl_register_map reg_map;
442 struct cxl_device_regs regs;
443 int cxl_dvsec;
444 bool rcd;
445 bool media_ready;
446 struct resource dpa_res;
447 struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
448 unsigned int nr_partitions;
449 u64 serial;
450 enum cxl_devtype type;
451 struct cxl_mailbox cxl_mbox;
452 #ifdef CONFIG_CXL_FEATURES
453 struct cxl_features_state *cxlfs;
454 #endif
455 };
456
cxl_pmem_size(struct cxl_dev_state * cxlds)457 static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
458 {
459 /*
460 * Static PMEM may be at partition index 0 when there is no static RAM
461 * capacity.
462 */
463 for (int i = 0; i < cxlds->nr_partitions; i++)
464 if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
465 return resource_size(&cxlds->part[i].res);
466 return 0;
467 }
468
mbox_to_cxlds(struct cxl_mailbox * cxl_mbox)469 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)
470 {
471 return dev_get_drvdata(cxl_mbox->host);
472 }
473
474 /**
475 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data
476 *
477 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines
478 * common memory device functionality like the presence of a mailbox and
479 * the functionality related to that like Identify Memory Device and Get
480 * Partition Info
481 * @cxlds: Core driver state common across Type-2 and Type-3 devices
482 * @lsa_size: Size of Label Storage Area
483 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
484 * @firmware_version: Firmware version for the memory device.
485 * @total_bytes: sum of all possible capacities
486 * @volatile_only_bytes: hard volatile capacity
487 * @persistent_only_bytes: hard persistent capacity
488 * @partition_align_bytes: alignment size for partition-able capacity
489 * @active_volatile_bytes: sum of hard + soft volatile
490 * @active_persistent_bytes: sum of hard + soft persistent
491 * @event: event log driver state
492 * @poison: poison driver state info
493 * @security: security driver state info
494 * @fw: firmware upload / activation state
495 * @mce_notifier: MCE notifier
496 *
497 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
498 * details on capacity parameters.
499 */
500 struct cxl_memdev_state {
501 struct cxl_dev_state cxlds;
502 size_t lsa_size;
503 char firmware_version[0x10];
504 u64 total_bytes;
505 u64 volatile_only_bytes;
506 u64 persistent_only_bytes;
507 u64 partition_align_bytes;
508 u64 active_volatile_bytes;
509 u64 active_persistent_bytes;
510
511 struct cxl_event_state event;
512 struct cxl_poison_state poison;
513 struct cxl_security_state security;
514 struct cxl_fw_state fw;
515 struct notifier_block mce_notifier;
516 };
517
518 static inline struct cxl_memdev_state *
to_cxl_memdev_state(struct cxl_dev_state * cxlds)519 to_cxl_memdev_state(struct cxl_dev_state *cxlds)
520 {
521 if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
522 return NULL;
523 return container_of(cxlds, struct cxl_memdev_state, cxlds);
524 }
525
526 enum cxl_opcode {
527 CXL_MBOX_OP_INVALID = 0x0000,
528 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
529 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
530 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
531 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
532 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
533 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
534 CXL_MBOX_OP_TRANSFER_FW = 0x0201,
535 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
536 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300,
537 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
538 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
539 CXL_MBOX_OP_GET_LOG = 0x0401,
540 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402,
541 CXL_MBOX_OP_CLEAR_LOG = 0x0403,
542 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405,
543 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500,
544 CXL_MBOX_OP_GET_FEATURE = 0x0501,
545 CXL_MBOX_OP_SET_FEATURE = 0x0502,
546 CXL_MBOX_OP_DO_MAINTENANCE = 0x0600,
547 CXL_MBOX_OP_IDENTIFY = 0x4000,
548 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
549 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
550 CXL_MBOX_OP_GET_LSA = 0x4102,
551 CXL_MBOX_OP_SET_LSA = 0x4103,
552 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
553 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
554 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
555 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
556 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
557 CXL_MBOX_OP_GET_POISON = 0x4300,
558 CXL_MBOX_OP_INJECT_POISON = 0x4301,
559 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
560 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
561 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
562 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
563 CXL_MBOX_OP_SANITIZE = 0x4400,
564 CXL_MBOX_OP_SECURE_ERASE = 0x4401,
565 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
566 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
567 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
568 CXL_MBOX_OP_UNLOCK = 0x4503,
569 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
570 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
571 CXL_MBOX_OP_MAX = 0x10000
572 };
573
574 #define DEFINE_CXL_CEL_UUID \
575 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
576 0x3b, 0x3f, 0x17)
577
578 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
579 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
580 0x40, 0x3d, 0x86)
581
582 struct cxl_mbox_get_supported_logs {
583 __le16 entries;
584 u8 rsvd[6];
585 struct cxl_gsl_entry {
586 uuid_t uuid;
587 __le32 size;
588 } __packed entry[];
589 } __packed;
590
591 struct cxl_cel_entry {
592 __le16 opcode;
593 __le16 effect;
594 } __packed;
595
596 struct cxl_mbox_get_log {
597 uuid_t uuid;
598 __le32 offset;
599 __le32 length;
600 } __packed;
601
602 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
603 struct cxl_mbox_identify {
604 char fw_revision[0x10];
605 __le64 total_capacity;
606 __le64 volatile_capacity;
607 __le64 persistent_capacity;
608 __le64 partition_align;
609 __le16 info_event_log_size;
610 __le16 warning_event_log_size;
611 __le16 failure_event_log_size;
612 __le16 fatal_event_log_size;
613 __le32 lsa_size;
614 u8 poison_list_max_mer[3];
615 __le16 inject_poison_limit;
616 u8 poison_caps;
617 u8 qos_telemetry_caps;
618 } __packed;
619
620 /*
621 * General Media Event Record UUID
622 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
623 */
624 #define CXL_EVENT_GEN_MEDIA_UUID \
625 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \
626 0x21, 0xeb, 0xa6)
627
628 /*
629 * DRAM Event Record UUID
630 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
631 */
632 #define CXL_EVENT_DRAM_UUID \
633 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \
634 0x5c, 0x96, 0x24)
635
636 /*
637 * Memory Module Event Record UUID
638 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
639 */
640 #define CXL_EVENT_MEM_MODULE_UUID \
641 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \
642 0x13, 0xb7, 0x74)
643
644 /*
645 * Memory Sparing Event Record UUID
646 * CXL rev 3.2 section 8.2.10.2.1.4: Table 8-60
647 */
648 #define CXL_EVENT_MEM_SPARING_UUID \
649 UUID_INIT(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39, 0x4d, 0x1c, 0x96, \
650 0x6c, 0x7c, 0x65)
651
652 /*
653 * Get Event Records output payload
654 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
655 */
656 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
657 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
658 struct cxl_get_event_payload {
659 u8 flags;
660 u8 reserved1;
661 __le16 overflow_err_count;
662 __le64 first_overflow_timestamp;
663 __le64 last_overflow_timestamp;
664 __le16 record_count;
665 u8 reserved2[10];
666 struct cxl_event_record_raw records[];
667 } __packed;
668
669 /*
670 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
671 */
672 enum cxl_event_log_type {
673 CXL_EVENT_TYPE_INFO = 0x00,
674 CXL_EVENT_TYPE_WARN,
675 CXL_EVENT_TYPE_FAIL,
676 CXL_EVENT_TYPE_FATAL,
677 CXL_EVENT_TYPE_MAX
678 };
679
680 /*
681 * Clear Event Records input payload
682 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
683 */
684 struct cxl_mbox_clear_event_payload {
685 u8 event_log; /* enum cxl_event_log_type */
686 u8 clear_flags;
687 u8 nr_recs;
688 u8 reserved[3];
689 __le16 handles[];
690 } __packed;
691 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
692
693 struct cxl_mbox_get_partition_info {
694 __le64 active_volatile_cap;
695 __le64 active_persistent_cap;
696 __le64 next_volatile_cap;
697 __le64 next_persistent_cap;
698 } __packed;
699
700 struct cxl_mbox_get_lsa {
701 __le32 offset;
702 __le32 length;
703 } __packed;
704
705 struct cxl_mbox_set_lsa {
706 __le32 offset;
707 __le32 reserved;
708 u8 data[];
709 } __packed;
710
711 struct cxl_mbox_set_partition_info {
712 __le64 volatile_capacity;
713 u8 flags;
714 } __packed;
715
716 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
717
718 /* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */
719 struct cxl_mbox_get_health_info_out {
720 u8 health_status;
721 u8 media_status;
722 u8 additional_status;
723 u8 life_used;
724 __le16 device_temperature;
725 __le32 dirty_shutdown_cnt;
726 __le32 corrected_volatile_error_cnt;
727 __le32 corrected_persistent_error_cnt;
728 } __packed;
729
730 /* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */
731 struct cxl_mbox_set_shutdown_state_in {
732 u8 state;
733 } __packed;
734
735 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
736 struct cxl_mbox_set_timestamp_in {
737 __le64 timestamp;
738
739 } __packed;
740
741 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
742 struct cxl_mbox_poison_in {
743 __le64 offset;
744 __le64 length;
745 } __packed;
746
747 struct cxl_mbox_poison_out {
748 u8 flags;
749 u8 rsvd1;
750 __le64 overflow_ts;
751 __le16 count;
752 u8 rsvd2[20];
753 struct cxl_poison_record {
754 __le64 address;
755 __le32 length;
756 __le32 rsvd;
757 } __packed record[];
758 } __packed;
759
760 /*
761 * Get Poison List address field encodes the starting
762 * address of poison, and the source of the poison.
763 */
764 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6)
765 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0)
766
767 /* Get Poison List record length is in units of 64 bytes */
768 #define CXL_POISON_LEN_MULT 64
769
770 /* Kernel defined maximum for a list of poison errors */
771 #define CXL_POISON_LIST_MAX 1024
772
773 /* Get Poison List: Payload out flags */
774 #define CXL_POISON_FLAG_MORE BIT(0)
775 #define CXL_POISON_FLAG_OVERFLOW BIT(1)
776 #define CXL_POISON_FLAG_SCANNING BIT(2)
777
778 /* Get Poison List: Poison Source */
779 #define CXL_POISON_SOURCE_UNKNOWN 0
780 #define CXL_POISON_SOURCE_EXTERNAL 1
781 #define CXL_POISON_SOURCE_INTERNAL 2
782 #define CXL_POISON_SOURCE_INJECTED 3
783 #define CXL_POISON_SOURCE_VENDOR 7
784
785 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */
786 struct cxl_mbox_inject_poison {
787 __le64 address;
788 };
789
790 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */
791 struct cxl_mbox_clear_poison {
792 __le64 address;
793 u8 write_data[CXL_POISON_LEN_MULT];
794 } __packed;
795
796 /**
797 * struct cxl_mem_command - Driver representation of a memory device command
798 * @info: Command information as it exists for the UAPI
799 * @opcode: The actual bits used for the mailbox protocol
800 * @flags: Set of flags effecting driver behavior.
801 *
802 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
803 * will be enabled by the driver regardless of what hardware may have
804 * advertised.
805 *
806 * The cxl_mem_command is the driver's internal representation of commands that
807 * are supported by the driver. Some of these commands may not be supported by
808 * the hardware. The driver will use @info to validate the fields passed in by
809 * the user then submit the @opcode to the hardware.
810 *
811 * See struct cxl_command_info.
812 */
813 struct cxl_mem_command {
814 struct cxl_command_info info;
815 enum cxl_opcode opcode;
816 u32 flags;
817 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
818 };
819
820 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
821 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
822 #define CXL_PMEM_SEC_STATE_LOCKED 0x04
823 #define CXL_PMEM_SEC_STATE_FROZEN 0x08
824 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
825 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
826
827 /* set passphrase input payload */
828 struct cxl_set_pass {
829 u8 type;
830 u8 reserved[31];
831 /* CXL field using NVDIMM define, same length */
832 u8 old_pass[NVDIMM_PASSPHRASE_LEN];
833 u8 new_pass[NVDIMM_PASSPHRASE_LEN];
834 } __packed;
835
836 /* disable passphrase input payload */
837 struct cxl_disable_pass {
838 u8 type;
839 u8 reserved[31];
840 u8 pass[NVDIMM_PASSPHRASE_LEN];
841 } __packed;
842
843 /* passphrase secure erase payload */
844 struct cxl_pass_erase {
845 u8 type;
846 u8 reserved[31];
847 u8 pass[NVDIMM_PASSPHRASE_LEN];
848 } __packed;
849
850 enum {
851 CXL_PMEM_SEC_PASS_MASTER = 0,
852 CXL_PMEM_SEC_PASS_USER,
853 };
854
855 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
856 struct cxl_mbox_cmd *cmd);
857 int cxl_dev_state_identify(struct cxl_memdev_state *mds);
858 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
859 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
860 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
861 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
862 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
863 unsigned long *cmds);
864 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
865 unsigned long *cmds);
866 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
867 void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
868 enum cxl_event_log_type type,
869 enum cxl_event_type event_type,
870 const uuid_t *uuid, union cxl_event *evt);
871 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
872 int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
873 int cxl_set_timestamp(struct cxl_memdev_state *mds);
874 int cxl_poison_state_init(struct cxl_memdev_state *mds);
875 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
876 struct cxl_region *cxlr);
877 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
878 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
879 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
880 int cxl_inject_poison_locked(struct cxl_memdev *cxlmd, u64 dpa);
881 int cxl_clear_poison_locked(struct cxl_memdev *cxlmd, u64 dpa);
882
883 #ifdef CONFIG_CXL_EDAC_MEM_FEATURES
884 int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd);
885 int devm_cxl_region_edac_register(struct cxl_region *cxlr);
886 int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, union cxl_event *evt);
887 int cxl_store_rec_dram(struct cxl_memdev *cxlmd, union cxl_event *evt);
888 #else
devm_cxl_memdev_edac_register(struct cxl_memdev * cxlmd)889 static inline int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd)
890 { return 0; }
devm_cxl_region_edac_register(struct cxl_region * cxlr)891 static inline int devm_cxl_region_edac_register(struct cxl_region *cxlr)
892 { return 0; }
cxl_store_rec_gen_media(struct cxl_memdev * cxlmd,union cxl_event * evt)893 static inline int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd,
894 union cxl_event *evt)
895 { return 0; }
cxl_store_rec_dram(struct cxl_memdev * cxlmd,union cxl_event * evt)896 static inline int cxl_store_rec_dram(struct cxl_memdev *cxlmd,
897 union cxl_event *evt)
898 { return 0; }
899 #endif
900
901 #ifdef CONFIG_CXL_SUSPEND
902 void cxl_mem_active_inc(void);
903 void cxl_mem_active_dec(void);
904 #else
cxl_mem_active_inc(void)905 static inline void cxl_mem_active_inc(void)
906 {
907 }
cxl_mem_active_dec(void)908 static inline void cxl_mem_active_dec(void)
909 {
910 }
911 #endif
912
913 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
914
915 /**
916 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities
917 * @regs: mapped registers, see devm_cxl_setup_hdm()
918 * @decoder_count: number of decoders for this port
919 * @target_count: for switch decoders, max downstream port targets
920 * @interleave_mask: interleave granularity capability, see check_interleave_cap()
921 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()
922 * @port: mapped cxl_port, see devm_cxl_setup_hdm()
923 */
924 struct cxl_hdm {
925 struct cxl_component_regs regs;
926 unsigned int decoder_count;
927 unsigned int target_count;
928 unsigned int interleave_mask;
929 unsigned long iw_cap_mask;
930 struct cxl_port *port;
931 };
932
933 struct seq_file;
934 struct dentry *cxl_debugfs_create_dir(const char *dir);
935 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
936 #endif /* __CXL_MEM_H__ */
937