Searched refs:CRTC5_REGISTER_OFFSET (Results 1 – 6 of 6) sorted by relevance
38 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) macro
44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) macro
600 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 macro
63 CRTC5_REGISTER_OFFSET81 CRTC5_REGISTER_OFFSET,2931 reg_block = CRTC5_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()2982 reg_block = CRTC5_REGISTER_OFFSET; in dce_v8_0_set_crtc_vline_interrupt_state()
74 CRTC5_REGISTER_OFFSET93 CRTC5_REGISTER_OFFSET,2959 reg_block = CRTC5_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
63 CRTC5_REGISTER_OFFSET,2735 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v10_0_crtc_init()