Searched refs:CRTC0_REGISTER_OFFSET (Results 1 – 6 of 6) sorted by relevance
33 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) macro
39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) macro
595 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 macro
58 CRTC0_REGISTER_OFFSET,76 CRTC0_REGISTER_OFFSET,2916 reg_block = CRTC0_REGISTER_OFFSET; in dce_v8_0_set_crtc_vblank_interrupt_state()2967 reg_block = CRTC0_REGISTER_OFFSET; in dce_v8_0_set_crtc_vline_interrupt_state()
69 CRTC0_REGISTER_OFFSET,88 CRTC0_REGISTER_OFFSET,2944 reg_block = CRTC0_REGISTER_OFFSET; in dce_v6_0_set_crtc_vblank_interrupt_state()
58 CRTC0_REGISTER_OFFSET,2720 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v10_0_crtc_init()