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Searched refs:CP_RB0_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dnid.h484 #define CP_RB0_CNTL 0xC104 macro
H A Dsid.h1246 #define CP_RB0_CNTL 0xC104 macro
H A Dcikd.h1302 #define CP_RB0_CNTL 0xC104 macro
H A Dsi.c3654 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3657 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3673 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
H A Dni.c1606 CP_RB0_CNTL, in cayman_cp_resume()
H A Dcik.c4074 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4077 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4092 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c2735 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2736 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
H A Dgfx_v11_0.c3746 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3747 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
H A Dgfx_v10_0.c6520 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6521 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6523 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); in gfx_v10_0_cp_gfx_resume()