Searched refs:CLK_SLOW_SYS_DIV_INT (Results 1 – 1 of 1) sorted by relevance
52 #define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) macro 1364 regmap_reg_range(CLK_SLOW_SYS_CTRL, CLK_SLOW_SYS_DIV_INT),