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Searched refs:CLK_DIVIDER_ONE_BASED (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/clk/sophgo/
H A Dclk-sg2044.c463 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
470 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
477 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
484 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
491 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
498 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
505 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
512 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
519 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
526 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
[all …]
H A Dclk-cv18xx-ip.h91 (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c135 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
137 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
139 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
141 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
146 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
148 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
150 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
152 CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
H A Dclk-mpfs.c217 CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
219 CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
221 CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
223 CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
327 .cfg.flags = CLK_DIVIDER_ONE_BASED,
/linux/drivers/clk/zynq/
H A Dclkc.c139 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_register_fclk()
144 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
195 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
282 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
326 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
332 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
339 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
343 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
391 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | in zynq_clk_setup()
395 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
[all …]
/linux/drivers/clk/ti/
H A Ddivider.c47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
62 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
84 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_val()
493 div->flags |= CLK_DIVIDER_ONE_BASED; in ti_clk_divider_populate()
H A Dadpll.c655 CLK_DIVIDER_ONE_BASED); in ti_adpll_init_children_adpll_s()
698 CLK_DIVIDER_ONE_BASED); in ti_adpll_init_children_adpll_s()
728 CLK_DIVIDER_ONE_BASED); in ti_adpll_init_children_adpll_lj()
/linux/drivers/clk/mmp/
H A Dclk-audio.c272 priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
293 priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
324 priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED; in register_clocks()
H A Dclk-mix.c30 if (mix->div_flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
47 if (mix->div_flags & CLK_DIVIDER_ONE_BASED) in _get_div()
84 if (mix->div_flags & CLK_DIVIDER_ONE_BASED) in _get_div_val()
H A Dclk-of-mmp2.c349 …{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0…
351 …{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1…
H A Dclk-of-pxa1928.c155 {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1019 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in clk_wzrd_register_output_clocks()
1052 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in clk_wzrd_register_output_clocks()
1101 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | in clk_wzrd_register_output_clocks()
1123 CLK_DIVIDER_ONE_BASED | in clk_wzrd_register_output_clocks()
1133 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in clk_wzrd_register_output_clocks()
1141 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in clk_wzrd_register_output_clocks()
H A Dxlnx_vcu.c447 u8 divider_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | in xvcu_clk_hw_register_leaf()
/linux/drivers/clk/
H A Dclk-divider.c71 if (flags & CLK_DIVIDER_ONE_BASED) in _get_maxdiv()
96 if (flags & CLK_DIVIDER_ONE_BASED) in _get_div()
123 if (flags & CLK_DIVIDER_ONE_BASED) in _get_val()
H A Dclk-asm9260.c306 base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, in asm9260_acc_init()
H A Dclk-bm1880.c676 div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; in bm1880_clk_register_div()
815 div_hws->div.flags = CLK_DIVIDER_ONE_BASED | in bm1880_clk_register_composite()
H A Dclk-nomadik.c542 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in of_nomadik_hclk_setup()
H A Dclk-loongson2.c410 CLK_DIVIDER_ONE_BASED | in loongson2_clk_probe()
/linux/drivers/clk/mxs/
H A Dclk-div.c93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c759 CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
763 9, 7, CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
769 CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
/linux/drivers/clk/sunxi/
H A Dclk-a10-pll2.c66 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in sun4i_pll2_setup()
/linux/drivers/clk/imx/
H A Dclk-divider-gate.c207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
/linux/drivers/clk/zynqmp/
H A Ddivider.c248 ccf_flag |= CLK_DIVIDER_ONE_BASED; in zynqmp_clk_map_divider_ccf_flags()
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c605 0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); in pll_10nm_register()
661 4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock); in pll_10nm_register()
/linux/drivers/clk/meson/
H A Dc3-pll.c479 .flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,

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