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Searched refs:CLK_DIV (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/clk/
H A Dclk-loongson2.c59 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ macro
148 CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
149 CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
150 CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7),
159 CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
160 CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
161 CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
167 CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7),
168 CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
174 CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
[all …]
H A Dclk-bm1880.c183 #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ macro
372 CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw,
374 CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw,
376 CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw,
378 CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw,
381 CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw,
384 CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw,
387 CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw,
390 CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw,
/linux/drivers/misc/cardreader/
H A Drtsx_usb.c451 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in rtsx_usb_switch_clock()
452 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, in rtsx_usb_switch_clock()
478 ret = rtsx_usb_write_register(ucr, CLK_DIV, CLK_CHANGE, 0); in rtsx_usb_switch_clock()
585 ret = rtsx_usb_write_register(ucr, CLK_DIV, CLK_CHANGE, 0x00); in rtsx_usb_init_chip()
H A Drts5228.c656 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5228_pci_switch_clock()
H A Drts5261.c729 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5261_pci_switch_clock()
H A Drtsx_pcr.c771 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rtsx_pci_switch_clock()
1220 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
H A Drts5264.c883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rts5264_pci_switch_clock()
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,flexgen.txt33 | | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
/linux/include/linux/
H A Drtsx_usb.h238 #define CLK_DIV 0xFC03 macro
H A Drtsx_pci.h454 #define CLK_DIV 0xFC03 macro
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c99 #define CLK_DIV(x) (x) macro
833 writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp), in cdns_dsi_bridge_atomic_pre_enable()
/linux/drivers/mmc/host/
H A Drtsx_usb_sdmmc.c585 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in sd_change_phase()
597 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0); in sd_change_phase()