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Searched refs:CGU_CLK_MUX (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c329 "sclk_a", CGU_CLK_MUX,
336 "cpumux", CGU_CLK_MUX,
365 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
373 "ahb2_apb_mux", CGU_CLK_MUX,
392 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
404 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
413 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
420 "i2s", CGU_CLK_MUX,
426 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
434 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
H A Djz4770-cgu.c209 "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
216 "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
223 "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
230 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
237 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
244 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
251 "bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
258 "lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
265 "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
275 "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
[all …]
H A Djz4760-cgu.c215 "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
222 "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
229 "lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
235 "tve", CGU_CLK_GATE | CGU_CLK_MUX,
241 "lpclk", CGU_CLK_GATE | CGU_CLK_MUX,
247 "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
257 "pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
265 "i2s", CGU_CLK_DIV | CGU_CLK_MUX,
272 "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
282 "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
H A Dx1000-cgu.c275 "sclk_a", CGU_CLK_MUX,
281 "cpu_mux", CGU_CLK_MUX,
310 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
317 "ahb2_apb_mux", CGU_CLK_MUX,
336 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
349 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
357 "i2s_pll_mux", CGU_CLK_MUX,
378 "i2s", CGU_CLK_MUX,
388 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
396 "msc_mux", CGU_CLK_MUX,
[all …]
H A Dx1830-cgu.c215 "sclk_a", CGU_CLK_MUX,
221 "cpu_mux", CGU_CLK_MUX,
246 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
253 "ahb2_apb_mux", CGU_CLK_MUX,
272 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
285 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
294 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
303 "msc_mux", CGU_CLK_MUX,
324 "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
338 "ssi_mux", CGU_CLK_MUX,
[all …]
H A Djz4725b-cgu.c152 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
159 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
173 "udc", CGU_CLK_MUX | CGU_CLK_DIV,
244 "rtc", CGU_CLK_MUX,
H A Djz4755-cgu.c140 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
161 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
175 "tve", CGU_CLK_MUX | CGU_CLK_GATE,
182 "rtc", CGU_CLK_MUX | CGU_CLK_GATE,
H A Djz4740-cgu.c166 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
174 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
196 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
H A Dcgu.c342 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
369 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
702 if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) { in ingenic_register_clock()
705 if (caps & CGU_CLK_MUX) in ingenic_register_clock()
756 if (caps & CGU_CLK_MUX) { in ingenic_register_clock()
760 caps &= ~(CGU_CLK_MUX | CGU_CLK_MUX_GLITCHFREE); in ingenic_register_clock()
H A Dcgu.h165 CGU_CLK_MUX = BIT(3), enumerator