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Searched refs:CCI_REG8 (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/media/i2c/
H A Dov64a40.c39 #define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301)
40 #define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303)
42 #define OV64A40_PLL1_M_DIV CCI_REG8(0x0307)
43 #define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320)
44 #define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323)
46 #define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326)
47 #define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329)
48 #define OV64A40_PLL2_DIVSP CCI_REG8(0x032d)
49 #define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e)
79 #define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814)
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H A Dgc2145.c38 #define GC2145_REG_ANALOG_MODE1 CCI_REG8(0x17)
39 #define GC2145_REG_OUTPUT_FMT CCI_REG8(0x84)
40 #define GC2145_REG_SYNC_MODE CCI_REG8(0x86)
43 #define GC2145_REG_BYPASS_MODE CCI_REG8(0x89)
45 #define GC2145_REG_DEBUG_MODE2 CCI_REG8(0x8c)
46 #define GC2145_REG_DEBUG_MODE3 CCI_REG8(0x8d)
47 #define GC2145_REG_CROP_ENABLE CCI_REG8(0x90)
52 #define GC2145_REG_GLOBAL_GAIN CCI_REG8(0xb0)
54 #define GC2145_REG_PAD_IO CCI_REG8(0xf2)
55 #define GC2145_REG_PAGE_SELECT CCI_REG8(0xfe)
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H A Dgc05a2.c30 #define GC05A2_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
31 #define GC05A2_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
34 #define GC05A2_STREAMING_REG CCI_REG8(0x0100)
36 #define GC05A2_FLIP_REG CCI_REG8(0x0101)
116 { CCI_REG8(0x0135), 0x01 },
117 { CCI_REG8(0x0084), 0x21 },
118 { CCI_REG8(0x0d05), 0xcc },
119 { CCI_REG8(0x0218), 0x00 },
120 { CCI_REG8(0x005e), 0x48 },
121 { CCI_REG8(0x0d06), 0x01 },
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H A Dgc08a3.c30 #define GC08A3_REG_TEST_PATTERN_EN CCI_REG8(0x008c)
31 #define GC08A3_REG_TEST_PATTERN_IDX CCI_REG8(0x008d)
34 #define GC08A3_STREAMING_REG CCI_REG8(0x0100)
36 #define GC08A3_FLIP_REG CCI_REG8(0x0101)
113 { CCI_REG8(0x0336), 0x70 },
114 { CCI_REG8(0x0383), 0xbb },
115 { CCI_REG8(0x0344), 0x00 },
116 { CCI_REG8(0x0345), 0x06 },
117 { CCI_REG8(0x0346), 0x00 },
118 { CCI_REG8(0x0347), 0x04 },
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H A Dimx111.c29 #define IMX111_REVISION CCI_REG8(0x0002)
30 #define IMX111_MANUFACTURER_ID CCI_REG8(0x0003)
31 #define IMX111_FRAME_COUNTER CCI_REG8(0x0005)
32 #define IMX111_PIXEL_ORDER CCI_REG8(0x0006)
35 #define IMX111_STREAMING_MODE CCI_REG8(0x0100)
38 #define IMX111_IMAGE_ORIENTATION CCI_REG8(0x0101)
41 #define IMX111_SOFTWARE_RESET CCI_REG8(0x0103)
43 #define IMX111_GROUP_WRITE CCI_REG8(0x0104)
45 #define IMX111_FRAME_DROP CCI_REG8(0x0105)
47 #define IMX111_CHANNEL_ID CCI_REG8(0x0110)
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H A Dgc0308.c25 #define GC0308_CHIP_ID CCI_REG8(0x000)
26 #define GC0308_HBLANK CCI_REG8(0x001)
27 #define GC0308_VBLANK CCI_REG8(0x002)
33 #define GC0308_VS_START_TIME CCI_REG8(0x00d) /* in rows */
34 #define GC0308_VS_END_TIME CCI_REG8(0x00e) /* in rows */
35 #define GC0308_VB_HB CCI_REG8(0x00f)
36 #define GC0308_RSH_WIDTH CCI_REG8(0x010)
37 #define GC0308_TSP_WIDTH CCI_REG8(0x011)
38 #define GC0308_SAMPLE_HOLD_DELAY CCI_REG8(0x012)
39 #define GC0308_ROW_TAIL_WIDTH CCI_REG8(0x013)
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H A Dimx335.c22 #define IMX335_REG_MODE_SELECT CCI_REG8(0x3000)
27 #define IMX335_REG_HOLD CCI_REG8(0x3001)
29 #define IMX335_REG_MASTER_MODE CCI_REG8(0x3002)
30 #define IMX335_REG_BCWAIT_TIME CCI_REG8(0x300c)
31 #define IMX335_REG_CPWAIT_TIME CCI_REG8(0x300d)
32 #define IMX335_REG_WINMODE CCI_REG8(0x3018)
40 #define IMX335_REG_OPB_SIZE_V CCI_REG8(0x304c)
41 #define IMX335_REG_ADBIT CCI_REG8(0x3050)
57 #define IMX335_REG_GAIN CCI_REG8(0x30e8)
64 #define IMX335_REG_VREVERSE CCI_REG8(0x304f)
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H A Dov5693.c32 #define OV5693_SW_RESET_REG CCI_REG8(0x0103)
33 #define OV5693_SW_STREAM_REG CCI_REG8(0x0100)
85 #define OV5693_SUB_INC_X_REG CCI_REG8(0x3814)
86 #define OV5693_SUB_INC_Y_REG CCI_REG8(0x3815)
88 #define OV5693_FORMAT1_REG CCI_REG8(0x3820)
92 #define OV5693_FORMAT2_REG CCI_REG8(0x3821)
98 #define OV5693_ISP_CTRL2_REG CCI_REG8(0x5002)
114 #define OV5693_TEST_PATTERN_REG CCI_REG8(0x5e00)
176 {CCI_REG8(0x3016), 0xf0},
177 {CCI_REG8(0x3017), 0xf0},
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H A Dimx334.c21 #define IMX334_REG_MODE_SELECT CCI_REG8(0x3000)
30 #define IMX334_REG_OPB_SIZE_V CCI_REG8(0x304c)
31 #define IMX334_REG_ADBIT CCI_REG8(0x3050)
32 #define IMX334_REG_MDBIT CCI_REG8(0x319d)
35 #define IMX334_REG_XVS_XHS_OUTSEL CCI_REG8(0x31a0)
36 #define IMX334_REG_XVS_XHS_DRV CCI_REG8(0x31a1)
39 #define IMX334_REG_ID CCI_REG8(0x3044)
49 #define IMX334_REG_LANEMODE CCI_REG8(0x3a01)
64 #define IMX334_REG_VREVERSE CCI_REG8(0x304f)
65 #define IMX334_REG_HREVERSE CCI_REG8(0x304e)
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H A Dimx214.c29 #define IMX214_REG_MODE_SELECT CCI_REG8(0x0100)
33 #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106)
55 #define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222)
76 #define IMX214_REG_ORIENTATION CCI_REG8(0x0101)
78 #define IMX214_REG_MASK_CORR_FRAMES CCI_REG8(0x0105)
89 #define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114)
96 #define IMX214_REG_TEMP_SENSOR_CONTROL CCI_REG8(0x0138)
98 #define IMX214_REG_HDR_MODE CCI_REG8(0x0220)
102 #define IMX214_REG_HDR_RES_REDUCTION CCI_REG8(0x0221)
107 #define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301)
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H A Dimx290.c30 #define IMX290_STANDBY CCI_REG8(0x3000)
31 #define IMX290_REGHOLD CCI_REG8(0x3001)
32 #define IMX290_XMSTA CCI_REG8(0x3002)
33 #define IMX290_ADBIT CCI_REG8(0x3005)
36 #define IMX290_CTRL_07 CCI_REG8(0x3007)
42 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009)
44 #define IMX290_GAIN CCI_REG8(0x3014)
50 #define IMX290_WINWV_OB CCI_REG8(0x303a)
55 #define IMX290_OUT_CTRL CCI_REG8(0x3046)
62 #define IMX290_XSOUTSEL CCI_REG8(0x304b)
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H A Dov4689.c23 #define OV4689_REG_CTRL_MODE CCI_REG8(0x0100)
61 #define OV4689_REG_TIMING_FORMAT1 CCI_REG8(0x3820) /* Vertical */
62 #define OV4689_REG_TIMING_FORMAT2 CCI_REG8(0x3821) /* Horizontal */
78 #define OV4689_REG_VFIFO_CTRL_01 CCI_REG8(0x4601)
87 #define OV4689_REG_TEST_PATTERN CCI_REG8(0x5040)
160 { CCI_REG8(0x0103), 0x01 }, /* SC_CTRL0103 software_reset = 1 */
161 { CCI_REG8(0x3000), 0x20 }, /* SC_CMMN_PAD_OEN0 FSIN_output_enable = 1 */
162 { CCI_REG8(0x3021), 0x03 }, /*
168 { CCI_REG8(0x3503), 0x04 }, /* AEC_MANUAL gain_input_as_sensor_gain_format = 1 */
171 { CCI_REG8(0x3603), 0x40 },
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H A Dimx415.c36 #define IMX415_MODE CCI_REG8(0x3000)
39 #define IMX415_REGHOLD CCI_REG8(0x3001)
42 #define IMX415_XMSTA CCI_REG8(0x3002)
47 #define IMX415_WINMODE CCI_REG8(0x301c)
48 #define IMX415_ADDMODE CCI_REG8(0x3022)
49 #define IMX415_REVERSE CCI_REG8(0x3030)
52 #define IMX415_ADBIT CCI_REG8(0x3031)
53 #define IMX415_MDBIT CCI_REG8(0x3032)
54 #define IMX415_SYS_MODE CCI_REG8(0x3033)
55 #define IMX415_OUTSEL CCI_REG8(0x30c0)
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H A Dimx258.c18 #define IMX258_REG_MODE_SELECT CCI_REG8(0x0100)
22 #define IMX258_REG_RESET CCI_REG8(0x0103)
63 #define IMX258_REG_HDR CCI_REG8(0x0220)
65 #define IMX258_REG_HDR_RATIO CCI_REG8(0x0222)
74 #define IMX258_CLK_BLANK_STOP CCI_REG8(0x4040)
77 #define REG_MIRROR_FLIP_CONTROL CCI_REG8(0x0101)
90 #define IMX258_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
91 #define IMX258_REG_IVTPXCK_DIV CCI_REG8(0x0301)
92 #define IMX258_REG_IVTSYCK_DIV CCI_REG8(0x0303)
93 #define IMX258_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305)
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H A Dimx283.c39 #define IMX283_REG_CHIP_ID CCI_REG8(0x3000)
42 #define IMX283_REG_STANDBY CCI_REG8(0x3000)
50 #define IMX283_REG_CLAMP CCI_REG8(0x3001)
53 #define IMX283_REG_PLSTMG08 CCI_REG8(0x3003)
56 #define IMX283_REG_MDSEL1 CCI_REG8(0x3004)
57 #define IMX283_REG_MDSEL2 CCI_REG8(0x3005)
58 #define IMX283_REG_MDSEL3 CCI_REG8(0x3006)
60 #define IMX283_REG_MDSEL4 CCI_REG8(0x3007)
65 #define IMX283_REG_HTRIMMING CCI_REG8(0x300b)
75 #define IMX283_REG_TCLKPOST CCI_REG8(0x3018)
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H A Dmax96717.c33 #define MAX96717_REG3 CCI_REG8(0x3)
35 #define RCLKSEL_REF_PLL CCI_REG8(0x3)
36 #define MAX96717_REG6 CCI_REG8(0x6)
38 #define MAX96717_DEV_ID CCI_REG8(0xd)
39 #define MAX96717_DEV_REV CCI_REG8(0xe)
43 #define MAX96717_VIDEO_TX0 CCI_REG8(0x110)
45 #define MAX96717_VIDEO_TX2 CCI_REG8(0x112)
49 #define MAX96717_VTX0 CCI_REG8(0x24e)
50 #define MAX96717_VTX1 CCI_REG8(0x24f)
63 #define MAX96717_VTX29 CCI_REG8(0x26b)
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H A Dthp7312.c37 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000)
38 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001)
39 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005)
40 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008)
43 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009)
46 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c)
49 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d)
58 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f)
62 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010)
63 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011)
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H A Dmax96714.c31 #define MAX96714_REG13 CCI_REG8(0x0d)
32 #define MAX96714_DEV_REV CCI_REG8(0x0e)
34 #define MAX96714_LINK_LOCK CCI_REG8(0x13)
36 #define MAX96714_IO_CHK0 CCI_REG8(0x38)
39 #define MAX96714_VIDEO_RX8 CCI_REG8(0x11a)
43 #define MAX96714_PATGEN_0 CCI_REG8(0x240)
44 #define MAX96714_PATGEN_1 CCI_REG8(0x241)
57 #define MAX96714_PATGEN_GRAD_INC CCI_REG8(0x25d)
60 #define MAX96714_PATGEN_CHKB_RPT_CNT_A CCI_REG8(0x264)
61 #define MAX96714_PATGEN_CHKB_RPT_CNT_B CCI_REG8(0x265)
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H A Ddw9719.c26 #define DW9718S_PD CCI_REG8(0)
28 #define DW9718S_CONTROL CCI_REG8(1)
38 #define DW9718S_SW CCI_REG8(4)
42 #define DW9718S_SACT CCI_REG8(5)
45 #define DW9719_INFO CCI_REG8(0)
49 #define DW9719_CONTROL CCI_REG8(2)
59 #define DW9719_MODE CCI_REG8(6)
64 #define DW9719_VCM_FREQ CCI_REG8(7)
68 #define DW9761_VCM_PRELOAD CCI_REG8(8)
H A Dst-mipid02.c28 #define MIPID02_CLK_LANE_WR_REG1 CCI_REG8(0x01)
29 #define MIPID02_CLK_LANE_REG1 CCI_REG8(0x02)
30 #define MIPID02_CLK_LANE_REG3 CCI_REG8(0x04)
31 #define MIPID02_DATA_LANE0_REG1 CCI_REG8(0x05)
32 #define MIPID02_DATA_LANE0_REG2 CCI_REG8(0x06)
33 #define MIPID02_DATA_LANE1_REG1 CCI_REG8(0x09)
34 #define MIPID02_DATA_LANE1_REG2 CCI_REG8(0x0a)
35 #define MIPID02_MODE_REG1 CCI_REG8(0x14)
36 #define MIPID02_MODE_REG2 CCI_REG8(0x15)
37 #define MIPID02_DATA_ID_RREG CCI_REG8(0x17)
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H A Dvd56g3.c32 #define VD56G3_REG_OPTICAL_REVISION CCI_REG8(0x001a)
35 #define VD56G3_REG_SYSTEM_FSM CCI_REG8(0x0028)
40 #define VD56G3_REG_APPLIED_ANALOG_GAIN CCI_REG8(0x0068)
42 #define VD56G3_REG_BOOT CCI_REG8(0x0200)
45 #define VD56G3_REG_STBY CCI_REG8(0x0201)
47 #define VD56G3_REG_STREAMING CCI_REG8(0x0202)
50 #define VD56G3_REG_CLK_PLL_PREDIV CCI_REG8(0x0224)
51 #define VD56G3_REG_CLK_SYS_PLL_MULT CCI_REG8(0x0226)
52 #define VD56G3_REG_ORIENTATION CCI_REG8(0x0302)
53 #define VD56G3_REG_FORMAT_CTRL CCI_REG8(0x030a)
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H A Dvgxy61.c35 #define VGXY61_REG_FWPATCH_START_ADDR CCI_REG8(0x2000)
36 #define VGXY61_REG_SYSTEM_FSM CCI_REG8(0x0020)
39 #define VGXY61_REG_NVM CCI_REG8(0x0023)
41 #define VGXY61_REG_STBY CCI_REG8(0x0201)
44 #define VGXY61_REG_STREAMING CCI_REG8(0x0202)
49 #define VGXY61_REG_CLK_PLL_PREDIV CCI_REG8(0x0224)
50 #define VGXY61_REG_CLK_SYS_PLL_MULT CCI_REG8(0x0225)
51 #define VGXY61_REG_GPIO_0_CTRL CCI_REG8(0x0236)
52 #define VGXY61_REG_GPIO_1_CTRL CCI_REG8(0x0237)
53 #define VGXY61_REG_GPIO_2_CTRL CCI_REG8(0x0238)
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H A Dvd55g1.c38 #define VD55G1_REG_FWPATCH_START_ADDR CCI_REG8(0x2000)
39 #define VD55G1_REG_SYSTEM_FSM CCI_REG8(0x001c)
43 #define VD55G1_REG_BOOT CCI_REG8(0x0200)
46 #define VD55G1_REG_STBY CCI_REG8(0x0201)
48 #define VD55G1_REG_STREAMING CCI_REG8(0x0202)
52 #define VD55G1_REG_ORIENTATION CCI_REG8(0x0302)
53 #define VD55G1_REG_FORMAT_CTRL CCI_REG8(0x030a)
56 #define VD55G1_REG_OIF_IMG_CTRL CCI_REG8(0x030f)
61 #define VD55G1_REG_MANUAL_ANALOG_GAIN CCI_REG8(0x0501)
67 #define VD55G1_REG_AE_FORCE_COLDSTART CCI_REG8(0x0308)
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/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
29 #define SMIAPP_REG_U8_MODULE_DATE_YEAR CCI_REG8(0x0012)
30 #define SMIAPP_REG_U8_MODULE_DATE_MONTH CCI_REG8(0x0013)
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H A Dccs-regs.h21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
37 #define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
38 #define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012)
39 #define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013)
40 #define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014)
41 #define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015)
49 #define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018)
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