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Searched refs:CAN1 (Results 1 – 25 of 38) sorted by relevance

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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044c2-smarc.dts14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
H A Dr9a07g043u11-smarc.dts14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
H A Drenesas-smarc2.dtsi32 * 1 - Connect to CAN1 transceiver STB pin
H A Dr9a09g087m44-rzn2h-evk.dts326 * CAN1 Pin Configuration:
328 * DSW5[1] ON; DSW5[2] OFF - Use P12_0 and P12_1 for CAN1 interface.
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-apalis-eval-v1.1.dtsi8 /* Apalis CAN1 */
H A Dimx8-apalis-ixora-v1.1.dtsi82 /* Apalis CAN1 */
H A Dimx8-apalis-eval-v1.2.dtsi90 /* Apalis CAN1 */
H A Dimx8mp-toradex-smarc-dev.dts84 /* SMARC CAN1 */
H A Dimx95-toradex-smarc-dev.dts72 /* SMARC CAN1 */
H A Dimx8-apalis-ixora-v1.2.dtsi114 /* Apalis CAN1 */
H A Dimx8mp-evk.dts668 "CAN1/I2C5_SEL",
692 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
693 * LOW: CAN1 (default, pull-down)
H A Dimx95-toradex-smarc.dtsi184 /* SMARC CAN1 */
841 /* SMARC CAN1 */
H A Dimx95-phycore-fpsc.dtsi79 &flexcan1 { /* FPSC CAN1 */
H A Dimx8mp-toradex-smarc.dtsi268 /* SMARC CAN1 */
896 /* SMARC CAN1 */
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f01-smarc.dts14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h78 #define CAN1 66 macro
/linux/drivers/net/can/sja1000/
H A DKconfig107 tristate "TS-CAN1 PC104 boards"
111 https://www.embeddedts.com/products/TS-CAN1
/linux/arch/powerpc/boot/dts/
H A Dpcm030.dts31 /* PSC2 port is used by CAN1/2 */
H A Dpcm032.dts33 /* PSC2 port is used by CAN1/2 */
/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c259 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
260 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
294 LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
295 LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
386 LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
387 LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
H A Dpinctrl-ocelot.c1047 LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
1048 LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
1232 LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, …
1233 LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, …
1240 LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, …
1241 LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, …
/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi399 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
400 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
409 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
H A Dstm32f429.dtsi370 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032-rzn1d400-db.dts157 /* Assuming CN10/CN11 are wired for CAN1 */
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-apalis-v1.1.dtsi106 /* Apalis CAN1 on SPI6 */
1073 /* SPI6: CAN1 */

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