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Searched refs:CACHELINE_BYTES (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ring_types.h19 #define CACHELINE_BYTES 64 macro
20 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
H A Dintel_ring.h110 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid()
138 return (head - tail - CACHELINE_BYTES) & (size - 1); in __intel_ring_space()
H A Dintel_engine.h32 #define CACHELINE_BYTES 64 macro
33 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
H A Dintel_ring.c170 ring->effective_size -= 2 * CACHELINE_BYTES; in intel_engine_create_ring()
/linux/arch/powerpc/lib/
H A Dstring_32.S16 CACHELINE_BYTES = L1_CACHE_BYTES define
51 addi r6, r6, CACHELINE_BYTES
H A Dchecksum_32.S120 CACHELINE_BYTES = L1_CACHE_BYTES define
180 addi r3,r3,CACHELINE_BYTES
184 addi r3,r3,CACHELINE_BYTES
H A Dcopy_32.S61 CACHELINE_BYTES = L1_CACHE_BYTES define
124 addi r6,r6,CACHELINE_BYTES
374 addi r3,r3,CACHELINE_BYTES
378 addi r3,r3,CACHELINE_BYTES
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dsb.c24 #define CACHELINE_BYTES 64 macro
200 !IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES)); in assert_dsb_tail_is_aligned()
521 aligned_tail = ALIGN(tail, CACHELINE_BYTES); in intel_dsb_align_tail()
537 aligned_tail = ALIGN(tail, CACHELINE_BYTES); in intel_dsb_gosub_align()
984 size = ALIGN(max_cmds * 8, CACHELINE_BYTES); in intel_dsb_prepare()
/linux/drivers/gpu/drm/i915/gvt/
H A Dcmd_parser.c2900 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, in scan_wa_ctx()
3018 roundup(ctx_size + CACHELINE_BYTES, in shadow_indirect_ctx()
3073 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); in combine_wa_ctx()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_submission.c431 u8 unused[CACHELINE_BYTES - sizeof(u32)];
467 BUILD_BUG_ON(sizeof(struct sync_semaphore) != CACHELINE_BYTES); in __get_parent_scratch()