Searched refs:C45 (Results 1 – 7 of 7) sorted by relevance
| /linux/drivers/net/phy/ |
| H A D | qt2025.rs | 17 reg::{Mmd, C45},
46 let hw_rev = dev.read(C45::new(Mmd::PMAPMD, 0xd001))?; in probe()
52 dev.write(C45::new(Mmd::PMAPMD, 0xc300), 0x0000)?; in probe()
54 dev.write(C45::new(Mmd::PMAPMD, 0xc302), 0x0004)?; in probe()
56 dev.write(C45::new(Mmd::PMAPMD, 0xc319), 0x0038)?; in probe()
58 dev.write(C45::new(Mmd::PMAPMD, 0xc31a), 0x0098)?; in probe()
62 dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?; in probe()
63 dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?; in probe()
64 dev.write(C45::new(Mmd::PCS, 0x0028), 0xa528)?; in probe()
65 dev.write(C45::new(Mmd::PCS, 0x0029), 0x0003)?; in probe()
[all …]
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| H A D | Kconfig | 92 These are C45 PHYs 10G that require all a generic firmware.
359 tristate "NXP C45 TJA11XX PHYs"
363 Enable support for NXP C45 TJA11XX PHYs.
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| /linux/rust/kernel/net/phy/ |
| H A D | reg.rs | 182 pub struct C45 { struct
187 impl C45 { argument
194 impl private::Sealed for C45 {} implementation
196 impl Register for C45 { implementation
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| /linux/drivers/net/mdio/ |
| H A D | mdio-cavium.c | 22 smi_clk.s.mode = (m == C45) ? 1 : 0; in cavium_mdiobus_set_mode()
35 cavium_mdiobus_set_mode(p, C45); in cavium_mdiobus_c45_addr()
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| H A D | mdio-cavium.h | 9 C45 enumerator
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-net-phydev | 36 These C45 IDs are used to match the device with the appropriate
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| /linux/ |
| H A D | MAINTAINERS | 19008 NXP C45 TJA11XX PHY DRIVER
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