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/linux/Documentation/driver-api/cxl/platform/
H A Dcdat.rst24 The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
39 DPA Base : 0000000040000000 <- 1GiB base
59 Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
69 Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
90 Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
109 Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
/linux/drivers/net/dsa/lantiq/
H A DKconfig22 GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X
23 GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
24 GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X
26 GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
/linux/Documentation/hwmon/
H A Dsmsc47b397.rst40 pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The
41 HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
42 and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and
170 Obtaining the HWM Base Address
173 The following is an example of how to read the HWM Base Address located in
191 OUT DX,AL ; Point to HWM Base Addr MSB
193 IN AL,DX ; Get MSB of HWM Base Addr
/linux/Documentation/ABI/testing/
H A Ddebugfs-intel-iommu13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
131 Base: 0x10022e000 Head: 20 Tail: 20
145 Base: 0x10026e000 Head: 32 Tail: 32
191 IOMMU: dmar0 Register Base Address: 26be37000
200 IOMMU: dmar2 Register Base Address: fed91000
213 IOMMU: dmar0 Register Base Address: 26be37000
/linux/Documentation/driver-api/cxl/platform/example-configurations/
H A Dflexible.rst146 Base Address : 0000001000000000
158 Base Address : 0000002000000000
170 Base Address : 0000002200000000
182 Base Address : 0000003000000000
194 Base Address : 0000003100000000
206 Base Address : 0000003200000000
218 Base Address : 0000003300000000
H A Done-dev-per-hb.rst71 Base Address : 0000001000000000
83 Base Address : 0000001100000000
/linux/arch/arm/boot/dts/st/
H A Dspear300.dtsi35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
H A Dspear310.dtsi30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
H A Dspear320.dtsi37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
H A Dspear600.dtsi77 0xd2000000 0x0010 /* NAND Base DATA */
78 0xd2020000 0x0010 /* NAND Base ADDR */
79 0xd2010000 0x0010>; /* NAND Base CMD */
H A Dspear13xx.dtsi140 0xb0800000 0x0010 /* NAND Base DATA */
141 0xb0820000 0x0010 /* NAND Base ADDR */
142 0xb0810000 0x0010>; /* NAND Base CMD */
/linux/Documentation/networking/
H A Darcnet-hardware.rst597 | Offs|Base |I/O Addr |
622 S1 1-3: I/O Base Address Select
623 4-6: Memory Base Address Select
646 Setting the I/O Base Address
650 of eight possible I/O Base addresses using the following table::
666 Setting the Base Memory (RAM) buffer Address
671 Switches 4-6 of switch group S1 select the Base of the 16K block.
830 SW1 1-6: I/O Base Address Select
887 Setting the I/O Base Address
891 of 32 possible I/O Base addresses using the following table::
[all …]
/linux/arch/arm/boot/dts/actions/
H A Dowl-s500-labrador-base-m.dts3 * Caninos Labrador Base Board
13 model = "Caninos Labrador Core v2 on Labrador Base-M v1";
/linux/Documentation/PCI/endpoint/
H A Dpci-vntb-function.rst66 +--------------------------------------------------+ Base
74 +-----------------------+--------------------------+ Base + span_offset
79 +-----------------------+--------------------------+ Base + span_offset
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-openrd-base.dts3 * Marvell OpenRD Base Board Description
16 model = "OpenRD Base";
H A Darmada-388-clearfog-base.dts3 * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
12 model = "SolidRun Clearfog Base A1";
/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
/linux/Documentation/scsi/
H A Dhptiop.rst89 0x4000 Inbound List Base Address Low
90 0x4004 Inbound List Base Address High
93 0x4050 Outbound List Base Address Low
94 0x4054 Outbound List Base Address High
95 0x4058 Outbound List Copy Pointer Shadow Base Address Low
96 0x405C Outbound List Copy Pointer Shadow Base Address High
/linux/arch/arm/boot/compressed/
H A Dhead-sharpsl.S29 mov r1, #0x10000000 @ Base address of TC6393 chip
43 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
129 mov r1, #0x0c000000 @ Base address of NAND chip
/linux/Documentation/virt/kvm/arm/
H A Dhypercalls.rst84 | Arguments: | (uint64) | R1 | Base IPA of memory region to share |
109 | Arguments: | (uint64) | R1 | Base IPA of memory region to unshare |
135 | Arguments: | (uint64) | R1 | Base IPA of MMIO memory region |
/linux/arch/arm/
H A DKconfig-nommu14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
22 hex 'FLASH Base Address' if SET_MEM_PARAM
/linux/Documentation/driver-api/cxl/conventions/
H A Dcxl-lmh.rst56 | Window | CFMWS Base | CFMWS Size | HDM Decoder Base | HDM Decoder Size | Ways |
66 3GB. Instead, the CFMWS Base and CFMWS Size are used to configure the Root
130 Hole for PCIe MMIO on x86, an instance of CFMWS whose Base HPA range is 0 might
/linux/arch/powerpc/boot/dts/fsl/
H A De500v2_power_isa.dtsi38 power-isa-b; // Base
40 power-isa-atb; // Alternate Time Base
H A De500v1_power_isa.dtsi38 power-isa-b; // Base
40 power-isa-atb; // Alternate Time Base
/linux/tools/testing/selftests/rcutorture/bin/
H A Dconfig_override.sh19 echo Base file $base unreadable!!!

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