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Searched refs:BLT_RING_BASE (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c647 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
680 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
687 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
688 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
689 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
690 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
691 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
692 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
693 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
694 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE,
[all...]
H A Dintel_gvt_mmio_table.c52 MMIO_F(prefix(BLT_RING_BASE), s); \
615 MMIO_D(ECOSKPD(BLT_RING_BASE)); in iterate_generic_mmio()
1258 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40); in iterate_bxt_mmio()
H A Di915_reg.h265 #define BLT_RING_BASE 0x22000 macro
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c81 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
82 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
83 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
84 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
85 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
135 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
136 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
137 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
138 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
139 {BCS0, RING_EXCC(BLT_RING_BASE),
[all...]
H A Dhandlers.c2183 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
2812 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_regs.h41 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
42 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
43 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
H A Dintel_rc6.c462 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h35 #define BLT_RING_BASE 0x22000 macro
/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine.c72 .mmio_base = BLT_RING_BASE,