1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v14_0.h"
35 #include "smu14_driver_if_v14_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v14_0_2_ppt.h"
39 #include "smu_v14_0_2_pptable.h"
40 #include "smu_v14_0_2_ppsmc.h"
41 #include "mp/mp_14_0_2_offset.h"
42 #include "mp/mp_14_0_2_sh_mask.h"
43
44 #include "smu_cmn.h"
45 #include "amdgpu_ras.h"
46
47 /*
48 * DO NOT use these for err/warn/info/debug messages.
49 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
50 * They are more MGPU friendly.
51 */
52 #undef pr_err
53 #undef pr_warn
54 #undef pr_info
55 #undef pr_debug
56
57 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
58
59 static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu,
60 int od_feature_bit,
61 int32_t *min, int32_t *max);
62
63 static const struct smu_feature_bits smu_v14_0_2_dpm_features = {
64 .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),
65 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),
66 SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),
67 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),
68 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT) }
69 };
70
71 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x2E
72
73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
74 #define DEBUGSMC_MSG_Mode1Reset 2
75 #define LINK_SPEED_MAX 3
76
77 #define PP_OD_FEATURE_GFXCLK_FMIN 0
78 #define PP_OD_FEATURE_GFXCLK_FMAX 1
79 #define PP_OD_FEATURE_UCLK_FMIN 2
80 #define PP_OD_FEATURE_UCLK_FMAX 3
81 #define PP_OD_FEATURE_GFX_VF_CURVE 4
82 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
83 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
84 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
85 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
86 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
87 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
88 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
89
90 static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {
91 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
92 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
93 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
94 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
95 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
96 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
97 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
98 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
99 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
100 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
101 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
102 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
103 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
104 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
105 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
106 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
107 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
108 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
109 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
110 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
111 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
112 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
113 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
114 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
115 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
123 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
124 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
125 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
126 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
127 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
128 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
129 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
130 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
131 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
135 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
136 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
137 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
138 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
139 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
140 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
141 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
142 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
143 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
144 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
145 };
146
147 static struct cmn2asic_mapping smu_v14_0_2_clk_map[SMU_CLK_COUNT] = {
148 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
149 CLK_MAP(SCLK, PPCLK_GFXCLK),
150 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
151 CLK_MAP(FCLK, PPCLK_FCLK),
152 CLK_MAP(UCLK, PPCLK_UCLK),
153 CLK_MAP(MCLK, PPCLK_UCLK),
154 CLK_MAP(VCLK, PPCLK_VCLK_0),
155 CLK_MAP(DCLK, PPCLK_DCLK_0),
156 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
157 };
158
159 static struct cmn2asic_mapping smu_v14_0_2_feature_mask_map[SMU_FEATURE_COUNT] = {
160 FEA_MAP(FW_DATA_READ),
161 FEA_MAP(DPM_GFXCLK),
162 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
163 FEA_MAP(DPM_UCLK),
164 FEA_MAP(DPM_FCLK),
165 FEA_MAP(DPM_SOCCLK),
166 FEA_MAP(DPM_LINK),
167 FEA_MAP(DPM_DCN),
168 FEA_MAP(VMEMP_SCALING),
169 FEA_MAP(VDDIO_MEM_SCALING),
170 FEA_MAP(DS_GFXCLK),
171 FEA_MAP(DS_SOCCLK),
172 FEA_MAP(DS_FCLK),
173 FEA_MAP(DS_LCLK),
174 FEA_MAP(DS_DCFCLK),
175 FEA_MAP(DS_UCLK),
176 FEA_MAP(GFX_ULV),
177 FEA_MAP(FW_DSTATE),
178 FEA_MAP(GFXOFF),
179 FEA_MAP(BACO),
180 FEA_MAP(MM_DPM),
181 FEA_MAP(SOC_MPCLK_DS),
182 FEA_MAP(BACO_MPCLK_DS),
183 FEA_MAP(THROTTLERS),
184 FEA_MAP(SMARTSHIFT),
185 FEA_MAP(GTHR),
186 FEA_MAP(ACDC),
187 FEA_MAP(VR0HOT),
188 FEA_MAP(FW_CTF),
189 FEA_MAP(FAN_CONTROL),
190 FEA_MAP(GFX_DCS),
191 FEA_MAP(GFX_READ_MARGIN),
192 FEA_MAP(LED_DISPLAY),
193 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
194 FEA_MAP(OUT_OF_BAND_MONITOR),
195 FEA_MAP(OPTIMIZED_VMIN),
196 FEA_MAP(GFX_IMU),
197 FEA_MAP(BOOT_TIME_CAL),
198 FEA_MAP(GFX_PCC_DFLL),
199 FEA_MAP(SOC_CG),
200 FEA_MAP(DF_CSTATE),
201 FEA_MAP(GFX_EDC),
202 FEA_MAP(BOOT_POWER_OPT),
203 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
204 FEA_MAP(DS_VCN),
205 FEA_MAP(BACO_CG),
206 FEA_MAP(MEM_TEMP_READ),
207 FEA_MAP(ATHUB_MMHUB_PG),
208 FEA_MAP(SOC_PCC),
209 FEA_MAP(EDC_PWRBRK),
210 FEA_MAP(SOC_EDC_XVMIN),
211 FEA_MAP(GFX_PSM_DIDT),
212 FEA_MAP(APT_ALL_ENABLE),
213 FEA_MAP(APT_SQ_THROTTLE),
214 FEA_MAP(APT_PF_DCS),
215 FEA_MAP(GFX_EDC_XVMIN),
216 FEA_MAP(GFX_DIDT_XVMIN),
217 FEA_MAP(FAN_ABNORMAL),
218 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
219 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
220 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
221 };
222
223 static struct cmn2asic_mapping smu_v14_0_2_table_map[SMU_TABLE_COUNT] = {
224 TAB_MAP(PPTABLE),
225 TAB_MAP(WATERMARKS),
226 TAB_MAP(AVFS_PSM_DEBUG),
227 TAB_MAP(PMSTATUSLOG),
228 TAB_MAP(SMU_METRICS),
229 TAB_MAP(DRIVER_SMU_CONFIG),
230 TAB_MAP(ACTIVITY_MONITOR_COEFF),
231 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
232 TAB_MAP(I2C_COMMANDS),
233 TAB_MAP(ECCINFO),
234 TAB_MAP(OVERDRIVE),
235 };
236
237 static struct cmn2asic_mapping smu_v14_0_2_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
238 PWR_MAP(AC),
239 PWR_MAP(DC),
240 };
241
242 static struct cmn2asic_mapping smu_v14_0_2_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
243 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
251 };
252
253 static const uint8_t smu_v14_0_2_throttler_map[] = {
254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
258 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
259 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
260 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
261 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
262 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
263 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
265 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
266 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
267 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
268 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
269 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
270 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
271 };
272
smu_v14_0_2_init_allowed_features(struct smu_context * smu)273 static int smu_v14_0_2_init_allowed_features(struct smu_context *smu)
274 {
275 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
276
277 return 0;
278 }
279
smu_v14_0_2_check_powerplay_table(struct smu_context * smu)280 static int smu_v14_0_2_check_powerplay_table(struct smu_context *smu)
281 {
282 struct smu_table_context *table_context = &smu->smu_table;
283 struct smu_14_0_2_powerplay_table *powerplay_table =
284 table_context->power_play_table;
285 struct smu_baco_context *smu_baco = &smu->smu_baco;
286 PPTable_t *pptable = smu->smu_table.driver_pptable;
287 const OverDriveLimits_t * const overdrive_upperlimits =
288 &pptable->SkuTable.OverDriveLimitsBasicMax;
289 const OverDriveLimits_t * const overdrive_lowerlimits =
290 &pptable->SkuTable.OverDriveLimitsBasicMin;
291
292 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_HARDWAREDC)
293 smu->dc_controlled_by_gpio = true;
294
295 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_BACO) {
296 smu_baco->platform_support = true;
297
298 if (powerplay_table->platform_caps & SMU_14_0_2_PP_PLATFORM_CAP_MACO)
299 smu_baco->maco_support = true;
300 }
301
302 if (!overdrive_lowerlimits->FeatureCtrlMask ||
303 !overdrive_upperlimits->FeatureCtrlMask)
304 smu->od_enabled = false;
305
306 table_context->thermal_controller_type =
307 powerplay_table->thermal_controller_type;
308
309 /*
310 * Instead of having its own buffer space and get overdrive_table copied,
311 * smu->od_settings just points to the actual overdrive_table
312 */
313 smu->od_settings = &powerplay_table->overdrive_table;
314
315 smu->adev->pm.no_fan =
316 !(pptable->PFE_Settings.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
317
318 return 0;
319 }
320
smu_v14_0_2_store_powerplay_table(struct smu_context * smu)321 static int smu_v14_0_2_store_powerplay_table(struct smu_context *smu)
322 {
323 struct smu_table_context *table_context = &smu->smu_table;
324 struct smu_14_0_2_powerplay_table *powerplay_table =
325 table_context->power_play_table;
326
327 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
328 sizeof(PPTable_t));
329
330 return 0;
331 }
332
smu_v14_0_2_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)333 static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
334 void **table,
335 uint32_t *size)
336 {
337 struct smu_table_context *smu_table = &smu->smu_table;
338 void *combo_pptable = smu_table->combo_pptable;
339 int ret = 0;
340
341 ret = smu_cmn_get_combo_pptable(smu);
342 if (ret)
343 return ret;
344
345 *table = combo_pptable;
346 *size = sizeof(struct smu_14_0_2_powerplay_table);
347
348 return 0;
349 }
350
smu_v14_0_2_setup_pptable(struct smu_context * smu)351 static int smu_v14_0_2_setup_pptable(struct smu_context *smu)
352 {
353 struct smu_table_context *smu_table = &smu->smu_table;
354 int ret = 0;
355
356 if (amdgpu_sriov_vf(smu->adev))
357 return 0;
358
359 ret = smu_v14_0_2_get_pptable_from_pmfw(smu,
360 &smu_table->power_play_table,
361 &smu_table->power_play_table_size);
362 if (ret)
363 return ret;
364
365 ret = smu_v14_0_2_store_powerplay_table(smu);
366 if (ret)
367 return ret;
368
369 ret = smu_v14_0_2_check_powerplay_table(smu);
370 if (ret)
371 return ret;
372
373 return ret;
374 }
375
smu_v14_0_2_tables_init(struct smu_context * smu)376 static int smu_v14_0_2_tables_init(struct smu_context *smu)
377 {
378 struct smu_table_context *smu_table = &smu->smu_table;
379 struct smu_table *tables = smu_table->tables;
380 int ret;
381
382 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
383 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
384 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
385 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
386 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
387 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
388 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
389 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
390 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
391 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
392 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU14_TOOL_SIZE,
393 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
394 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
395 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
396 AMDGPU_GEM_DOMAIN_VRAM);
397 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
398 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
399 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
400 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
401
402 smu_table->metrics_table = kzalloc_obj(SmuMetricsExternal_t);
403 if (!smu_table->metrics_table)
404 goto err0_out;
405 smu_table->metrics_time = 0;
406
407 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
408 sizeof(struct gpu_metrics_v1_3),
409 SMU_GPU_METRICS_CACHE_INTERVAL);
410 if (ret)
411 goto err1_out;
412
413 smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
414 if (!smu_table->watermarks_table)
415 goto err2_out;
416
417 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
418 if (!smu_table->ecc_table)
419 goto err3_out;
420
421 return 0;
422
423 err3_out:
424 kfree(smu_table->watermarks_table);
425 err2_out:
426 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
427 err1_out:
428 kfree(smu_table->metrics_table);
429 err0_out:
430 return -ENOMEM;
431 }
432
smu_v14_0_2_allocate_dpm_context(struct smu_context * smu)433 static int smu_v14_0_2_allocate_dpm_context(struct smu_context *smu)
434 {
435 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
436
437 smu_dpm->dpm_context = kzalloc_obj(struct smu_14_0_dpm_context);
438 if (!smu_dpm->dpm_context)
439 return -ENOMEM;
440
441 smu_dpm->dpm_context_size = sizeof(struct smu_14_0_dpm_context);
442
443 return 0;
444 }
445
smu_v14_0_2_init_smc_tables(struct smu_context * smu)446 static int smu_v14_0_2_init_smc_tables(struct smu_context *smu)
447 {
448 int ret = 0;
449
450 ret = smu_v14_0_2_tables_init(smu);
451 if (ret)
452 return ret;
453
454 ret = smu_v14_0_2_allocate_dpm_context(smu);
455 if (ret)
456 return ret;
457
458 return smu_v14_0_init_smc_tables(smu);
459 }
460
smu_v14_0_2_set_default_dpm_table(struct smu_context * smu)461 static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
462 {
463 struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
464 struct smu_table_context *table_context = &smu->smu_table;
465 PPTable_t *pptable = table_context->driver_pptable;
466 SkuTable_t *skutable = &pptable->SkuTable;
467 struct smu_dpm_table *dpm_table;
468 int ret = 0;
469
470 /* socclk dpm table setup */
471 dpm_table = &dpm_context->dpm_tables.soc_table;
472 dpm_table->clk_type = SMU_SOCCLK;
473 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
474 ret = smu_v14_0_set_single_dpm_table(smu,
475 SMU_SOCCLK,
476 dpm_table);
477 if (ret)
478 return ret;
479 } else {
480 dpm_table->count = 1;
481 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
482 dpm_table->dpm_levels[0].enabled = true;
483 }
484
485 /* gfxclk dpm table setup */
486 dpm_table = &dpm_context->dpm_tables.gfx_table;
487 dpm_table->clk_type = SMU_GFXCLK;
488 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
489 ret = smu_v14_0_set_single_dpm_table(smu,
490 SMU_GFXCLK,
491 dpm_table);
492 if (ret)
493 return ret;
494
495 /*
496 * Update the reported maximum shader clock to the value
497 * which can be guarded to be achieved on all cards. This
498 * is aligned with Window setting. And considering that value
499 * might be not the peak frequency the card can achieve, it
500 * is normal some real-time clock frequency can overtake this
501 * labelled maximum clock frequency(for example in pp_dpm_sclk
502 * sysfs output).
503 */
504 if (skutable->DriverReportedClocks.GameClockAc &&
505 (dpm_table->dpm_levels[dpm_table->count - 1].value >
506 skutable->DriverReportedClocks.GameClockAc)) {
507 dpm_table->dpm_levels[dpm_table->count - 1].value =
508 skutable->DriverReportedClocks.GameClockAc;
509 }
510 } else {
511 dpm_table->count = 1;
512 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
513 dpm_table->dpm_levels[0].enabled = true;
514 }
515
516 /* uclk dpm table setup */
517 dpm_table = &dpm_context->dpm_tables.uclk_table;
518 dpm_table->clk_type = SMU_UCLK;
519 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
520 ret = smu_v14_0_set_single_dpm_table(smu,
521 SMU_UCLK,
522 dpm_table);
523 if (ret)
524 return ret;
525 } else {
526 dpm_table->count = 1;
527 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
528 dpm_table->dpm_levels[0].enabled = true;
529 }
530
531 /* fclk dpm table setup */
532 dpm_table = &dpm_context->dpm_tables.fclk_table;
533 dpm_table->clk_type = SMU_FCLK;
534 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
535 ret = smu_v14_0_set_single_dpm_table(smu,
536 SMU_FCLK,
537 dpm_table);
538 if (ret)
539 return ret;
540 } else {
541 dpm_table->count = 1;
542 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
543 dpm_table->dpm_levels[0].enabled = true;
544 }
545
546 /* vclk dpm table setup */
547 dpm_table = &dpm_context->dpm_tables.vclk_table;
548 dpm_table->clk_type = SMU_VCLK;
549 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
550 ret = smu_v14_0_set_single_dpm_table(smu,
551 SMU_VCLK,
552 dpm_table);
553 if (ret)
554 return ret;
555 } else {
556 dpm_table->count = 1;
557 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
558 dpm_table->dpm_levels[0].enabled = true;
559 }
560
561 /* dclk dpm table setup */
562 dpm_table = &dpm_context->dpm_tables.dclk_table;
563 dpm_table->clk_type = SMU_DCLK;
564 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
565 ret = smu_v14_0_set_single_dpm_table(smu,
566 SMU_DCLK,
567 dpm_table);
568 if (ret)
569 return ret;
570 } else {
571 dpm_table->count = 1;
572 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
573 dpm_table->dpm_levels[0].enabled = true;
574 }
575
576 /* dcefclk dpm table setup */
577 dpm_table = &dpm_context->dpm_tables.dcef_table;
578 dpm_table->clk_type = SMU_DCEFCLK;
579 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
580 ret = smu_v14_0_set_single_dpm_table(smu,
581 SMU_DCEFCLK,
582 dpm_table);
583 if (ret)
584 return ret;
585 } else {
586 dpm_table->count = 1;
587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
588 dpm_table->dpm_levels[0].enabled = true;
589 }
590
591 return 0;
592 }
593
smu_v14_0_2_is_dpm_running(struct smu_context * smu)594 static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
595 {
596 int ret = 0;
597 struct smu_feature_bits feature_enabled;
598
599 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
600 if (ret)
601 return false;
602
603 return smu_feature_bits_test_mask(&feature_enabled,
604 smu_v14_0_2_dpm_features.bits);
605 }
606
smu_v14_0_2_get_throttler_status(SmuMetrics_t * metrics)607 static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)
608 {
609 uint32_t throttler_status = 0;
610 int i;
611
612 for (i = 0; i < THROTTLER_COUNT; i++)
613 throttler_status |=
614 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
615
616 return throttler_status;
617 }
618
619 #define SMU_14_0_2_BUSY_THRESHOLD 5
smu_v14_0_2_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)620 static int smu_v14_0_2_get_smu_metrics_data(struct smu_context *smu,
621 MetricsMember_t member,
622 uint32_t *value)
623 {
624 struct smu_table_context *smu_table = &smu->smu_table;
625 SmuMetrics_t *metrics =
626 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
627 int ret = 0;
628
629 ret = smu_cmn_get_metrics_table(smu,
630 NULL,
631 false);
632 if (ret)
633 return ret;
634
635 switch (member) {
636 case METRICS_CURR_GFXCLK:
637 *value = metrics->CurrClock[PPCLK_GFXCLK];
638 break;
639 case METRICS_CURR_SOCCLK:
640 *value = metrics->CurrClock[PPCLK_SOCCLK];
641 break;
642 case METRICS_CURR_UCLK:
643 *value = metrics->CurrClock[PPCLK_UCLK];
644 break;
645 case METRICS_CURR_VCLK:
646 *value = metrics->CurrClock[PPCLK_VCLK_0];
647 break;
648 case METRICS_CURR_DCLK:
649 *value = metrics->CurrClock[PPCLK_DCLK_0];
650 break;
651 case METRICS_CURR_FCLK:
652 *value = metrics->CurrClock[PPCLK_FCLK];
653 break;
654 case METRICS_CURR_DCEFCLK:
655 *value = metrics->CurrClock[PPCLK_DCFCLK];
656 break;
657 case METRICS_AVERAGE_GFXCLK:
658 if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
659 *value = metrics->AverageGfxclkFrequencyPostDs;
660 else
661 *value = metrics->AverageGfxclkFrequencyPreDs;
662 break;
663 case METRICS_AVERAGE_FCLK:
664 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
665 *value = metrics->AverageFclkFrequencyPostDs;
666 else
667 *value = metrics->AverageFclkFrequencyPreDs;
668 break;
669 case METRICS_AVERAGE_UCLK:
670 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
671 *value = metrics->AverageMemclkFrequencyPostDs;
672 else
673 *value = metrics->AverageMemclkFrequencyPreDs;
674 break;
675 case METRICS_AVERAGE_VCLK:
676 *value = metrics->AverageVclk0Frequency;
677 break;
678 case METRICS_AVERAGE_DCLK:
679 *value = metrics->AverageDclk0Frequency;
680 break;
681 case METRICS_AVERAGE_VCLK1:
682 *value = metrics->AverageVclk1Frequency;
683 break;
684 case METRICS_AVERAGE_DCLK1:
685 *value = metrics->AverageDclk1Frequency;
686 break;
687 case METRICS_AVERAGE_GFXACTIVITY:
688 *value = metrics->AverageGfxActivity;
689 break;
690 case METRICS_AVERAGE_MEMACTIVITY:
691 *value = metrics->AverageUclkActivity;
692 break;
693 case METRICS_AVERAGE_VCNACTIVITY:
694 *value = max(metrics->AverageVcn0ActivityPercentage,
695 metrics->Vcn1ActivityPercentage);
696 break;
697 case METRICS_AVERAGE_SOCKETPOWER:
698 *value = metrics->AverageSocketPower << 8;
699 break;
700 case METRICS_TEMPERATURE_EDGE:
701 *value = metrics->AvgTemperature[TEMP_EDGE] *
702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
703 break;
704 case METRICS_TEMPERATURE_HOTSPOT:
705 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
707 break;
708 case METRICS_TEMPERATURE_MEM:
709 *value = metrics->AvgTemperature[TEMP_MEM] *
710 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
711 break;
712 case METRICS_TEMPERATURE_VRGFX:
713 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
714 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
715 break;
716 case METRICS_TEMPERATURE_VRSOC:
717 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
718 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
719 break;
720 case METRICS_THROTTLER_STATUS:
721 *value = smu_v14_0_2_get_throttler_status(metrics);
722 break;
723 case METRICS_CURR_FANSPEED:
724 *value = metrics->AvgFanRpm;
725 break;
726 case METRICS_CURR_FANPWM:
727 *value = metrics->AvgFanPwm;
728 break;
729 case METRICS_VOLTAGE_VDDGFX:
730 *value = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
731 break;
732 case METRICS_PCIE_RATE:
733 *value = metrics->PcieRate;
734 break;
735 case METRICS_PCIE_WIDTH:
736 *value = metrics->PcieWidth;
737 break;
738 default:
739 *value = UINT_MAX;
740 break;
741 }
742
743 return ret;
744 }
745
smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)746 static int smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context *smu,
747 enum smu_clk_type clk_type,
748 uint32_t *min,
749 uint32_t *max)
750 {
751 struct smu_14_0_dpm_context *dpm_context =
752 smu->smu_dpm.dpm_context;
753 struct smu_dpm_table *dpm_table;
754
755 switch (clk_type) {
756 case SMU_MCLK:
757 case SMU_UCLK:
758 /* uclk dpm table */
759 dpm_table = &dpm_context->dpm_tables.uclk_table;
760 break;
761 case SMU_GFXCLK:
762 case SMU_SCLK:
763 /* gfxclk dpm table */
764 dpm_table = &dpm_context->dpm_tables.gfx_table;
765 break;
766 case SMU_SOCCLK:
767 /* socclk dpm table */
768 dpm_table = &dpm_context->dpm_tables.soc_table;
769 break;
770 case SMU_FCLK:
771 /* fclk dpm table */
772 dpm_table = &dpm_context->dpm_tables.fclk_table;
773 break;
774 case SMU_VCLK:
775 case SMU_VCLK1:
776 /* vclk dpm table */
777 dpm_table = &dpm_context->dpm_tables.vclk_table;
778 break;
779 case SMU_DCLK:
780 case SMU_DCLK1:
781 /* dclk dpm table */
782 dpm_table = &dpm_context->dpm_tables.dclk_table;
783 break;
784 default:
785 dev_err(smu->adev->dev, "Unsupported clock type!\n");
786 return -EINVAL;
787 }
788
789 if (min)
790 *min = SMU_DPM_TABLE_MIN(dpm_table);
791 if (max)
792 *max = SMU_DPM_TABLE_MAX(dpm_table);
793
794 return 0;
795 }
796
smu_v14_0_2_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)797 static int smu_v14_0_2_read_sensor(struct smu_context *smu,
798 enum amd_pp_sensors sensor,
799 void *data,
800 uint32_t *size)
801 {
802 struct smu_table_context *table_context = &smu->smu_table;
803 PPTable_t *smc_pptable = table_context->driver_pptable;
804 int ret = 0;
805
806 switch (sensor) {
807 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
808 *(uint16_t *)data = smc_pptable->CustomSkuTable.FanMaximumRpm;
809 *size = 4;
810 break;
811 case AMDGPU_PP_SENSOR_MEM_LOAD:
812 ret = smu_v14_0_2_get_smu_metrics_data(smu,
813 METRICS_AVERAGE_MEMACTIVITY,
814 (uint32_t *)data);
815 *size = 4;
816 break;
817 case AMDGPU_PP_SENSOR_GPU_LOAD:
818 ret = smu_v14_0_2_get_smu_metrics_data(smu,
819 METRICS_AVERAGE_GFXACTIVITY,
820 (uint32_t *)data);
821 *size = 4;
822 break;
823 case AMDGPU_PP_SENSOR_VCN_LOAD:
824 ret = smu_v14_0_2_get_smu_metrics_data(smu,
825 METRICS_AVERAGE_VCNACTIVITY,
826 (uint32_t *)data);
827 *size = 4;
828 break;
829 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
830 ret = smu_v14_0_2_get_smu_metrics_data(smu,
831 METRICS_AVERAGE_SOCKETPOWER,
832 (uint32_t *)data);
833 *size = 4;
834 break;
835 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
836 ret = smu_v14_0_2_get_smu_metrics_data(smu,
837 METRICS_TEMPERATURE_HOTSPOT,
838 (uint32_t *)data);
839 *size = 4;
840 break;
841 case AMDGPU_PP_SENSOR_EDGE_TEMP:
842 ret = smu_v14_0_2_get_smu_metrics_data(smu,
843 METRICS_TEMPERATURE_EDGE,
844 (uint32_t *)data);
845 *size = 4;
846 break;
847 case AMDGPU_PP_SENSOR_MEM_TEMP:
848 ret = smu_v14_0_2_get_smu_metrics_data(smu,
849 METRICS_TEMPERATURE_MEM,
850 (uint32_t *)data);
851 *size = 4;
852 break;
853 case AMDGPU_PP_SENSOR_GFX_MCLK:
854 ret = smu_v14_0_2_get_smu_metrics_data(smu,
855 METRICS_CURR_UCLK,
856 (uint32_t *)data);
857 *(uint32_t *)data *= 100;
858 *size = 4;
859 break;
860 case AMDGPU_PP_SENSOR_GFX_SCLK:
861 ret = smu_v14_0_2_get_smu_metrics_data(smu,
862 METRICS_AVERAGE_GFXCLK,
863 (uint32_t *)data);
864 *(uint32_t *)data *= 100;
865 *size = 4;
866 break;
867 case AMDGPU_PP_SENSOR_VDDGFX:
868 ret = smu_v14_0_2_get_smu_metrics_data(smu,
869 METRICS_VOLTAGE_VDDGFX,
870 (uint32_t *)data);
871 *size = 4;
872 break;
873 default:
874 ret = -EOPNOTSUPP;
875 break;
876 }
877
878 return ret;
879 }
880
smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)881 static int smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context *smu,
882 enum smu_clk_type clk_type,
883 uint32_t *value)
884 {
885 MetricsMember_t member_type;
886 int clk_id = 0;
887
888 clk_id = smu_cmn_to_asic_specific_index(smu,
889 CMN2ASIC_MAPPING_CLK,
890 clk_type);
891 if (clk_id < 0)
892 return -EINVAL;
893
894 switch (clk_id) {
895 case PPCLK_GFXCLK:
896 member_type = METRICS_AVERAGE_GFXCLK;
897 break;
898 case PPCLK_UCLK:
899 member_type = METRICS_CURR_UCLK;
900 break;
901 case PPCLK_FCLK:
902 member_type = METRICS_CURR_FCLK;
903 break;
904 case PPCLK_SOCCLK:
905 member_type = METRICS_CURR_SOCCLK;
906 break;
907 case PPCLK_VCLK_0:
908 member_type = METRICS_AVERAGE_VCLK;
909 break;
910 case PPCLK_DCLK_0:
911 member_type = METRICS_AVERAGE_DCLK;
912 break;
913 case PPCLK_DCFCLK:
914 member_type = METRICS_CURR_DCEFCLK;
915 break;
916 default:
917 return -EINVAL;
918 }
919
920 return smu_v14_0_2_get_smu_metrics_data(smu,
921 member_type,
922 value);
923 }
924
smu_v14_0_2_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)925 static bool smu_v14_0_2_is_od_feature_supported(struct smu_context *smu,
926 int od_feature_bit)
927 {
928 PPTable_t *pptable = smu->smu_table.driver_pptable;
929 const OverDriveLimits_t * const overdrive_upperlimits =
930 &pptable->SkuTable.OverDriveLimitsBasicMax;
931 int32_t min_value, max_value;
932 bool feature_enabled;
933
934 switch (od_feature_bit) {
935 case PP_OD_FEATURE_FAN_CURVE_BIT:
936 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
937 if (feature_enabled) {
938 smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP,
939 &min_value, &max_value);
940 if (!min_value && !max_value) {
941 feature_enabled = false;
942 goto out;
943 }
944
945 smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM,
946 &min_value, &max_value);
947 if (!min_value && !max_value) {
948 feature_enabled = false;
949 goto out;
950 }
951 }
952 break;
953 default:
954 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit));
955 break;
956 }
957
958 out:
959 return feature_enabled;
960 }
961
smu_v14_0_2_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)962 static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu,
963 int od_feature_bit,
964 int32_t *min,
965 int32_t *max)
966 {
967 PPTable_t *pptable = smu->smu_table.driver_pptable;
968 const OverDriveLimits_t * const overdrive_upperlimits =
969 &pptable->SkuTable.OverDriveLimitsBasicMax;
970 const OverDriveLimits_t * const overdrive_lowerlimits =
971 &pptable->SkuTable.OverDriveLimitsBasicMin;
972 int32_t od_min_setting, od_max_setting;
973
974 switch (od_feature_bit) {
975 case PP_OD_FEATURE_GFXCLK_FMIN:
976 case PP_OD_FEATURE_GFXCLK_FMAX:
977 od_min_setting = overdrive_lowerlimits->GfxclkFoffset;
978 od_max_setting = overdrive_upperlimits->GfxclkFoffset;
979 break;
980 case PP_OD_FEATURE_UCLK_FMIN:
981 od_min_setting = overdrive_lowerlimits->UclkFmin;
982 od_max_setting = overdrive_upperlimits->UclkFmin;
983 break;
984 case PP_OD_FEATURE_UCLK_FMAX:
985 od_min_setting = overdrive_lowerlimits->UclkFmax;
986 od_max_setting = overdrive_upperlimits->UclkFmax;
987 break;
988 case PP_OD_FEATURE_GFX_VF_CURVE:
989 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary[0];
990 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary[0];
991 break;
992 case PP_OD_FEATURE_FAN_CURVE_TEMP:
993 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints[0];
994 od_max_setting = overdrive_upperlimits->FanLinearTempPoints[0];
995 break;
996 case PP_OD_FEATURE_FAN_CURVE_PWM:
997 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints[0];
998 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints[0];
999 break;
1000 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1001 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1002 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1003 break;
1004 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1005 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1006 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1007 break;
1008 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1009 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1010 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1011 break;
1012 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1013 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1014 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1015 break;
1016 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1017 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1018 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1019 break;
1020 default:
1021 od_min_setting = od_max_setting = INT_MAX;
1022 break;
1023 }
1024
1025 if (min)
1026 *min = od_min_setting;
1027 if (max)
1028 *max = od_max_setting;
1029 }
1030
smu_v14_0_2_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)1031 static int smu_v14_0_2_emit_clk_levels(struct smu_context *smu,
1032 enum smu_clk_type clk_type, char *buf,
1033 int *offset)
1034 {
1035 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1036 struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1037 OverDriveTableExternal_t *od_table =
1038 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1039 struct smu_dpm_table *single_dpm_table = NULL;
1040 struct smu_pcie_table *pcie_table;
1041 uint32_t gen_speed, lane_width;
1042 int i, curr_freq, size = *offset, start_offset = *offset;
1043 int32_t min_value, max_value;
1044 int ret = 0;
1045
1046 if (amdgpu_ras_intr_triggered()) {
1047 sysfs_emit_at(buf, size, "unavailable\n");
1048 return -EBUSY;
1049 }
1050
1051 switch (clk_type) {
1052 case SMU_SCLK:
1053 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1054 break;
1055 case SMU_MCLK:
1056 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1057 break;
1058 case SMU_SOCCLK:
1059 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1060 break;
1061 case SMU_FCLK:
1062 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1063 break;
1064 case SMU_VCLK:
1065 case SMU_VCLK1:
1066 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1067 break;
1068 case SMU_DCLK:
1069 case SMU_DCLK1:
1070 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1071 break;
1072 case SMU_DCEFCLK:
1073 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1074 break;
1075 case SMU_PCIE:
1076 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1077 METRICS_PCIE_RATE,
1078 &gen_speed);
1079 if (ret)
1080 return ret;
1081
1082 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1083 METRICS_PCIE_WIDTH,
1084 &lane_width);
1085 if (ret)
1086 return ret;
1087
1088 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1089 return smu_cmn_print_pcie_levels(smu, pcie_table,
1090 SMU_DPM_PCIE_GEN_IDX(gen_speed),
1091 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
1092 buf, offset);
1093
1094 case SMU_OD_SCLK:
1095 if (!smu_v14_0_2_is_od_feature_supported(smu,
1096 PP_OD_FEATURE_GFXCLK_BIT))
1097 break;
1098
1099 size += sysfs_emit_at(buf, size, "OD_SCLK_OFFSET:\n");
1100 size += sysfs_emit_at(buf, size, "%dMhz\n",
1101 od_table->OverDriveTable.GfxclkFoffset);
1102 break;
1103
1104 case SMU_OD_MCLK:
1105 if (!smu_v14_0_2_is_od_feature_supported(smu,
1106 PP_OD_FEATURE_UCLK_BIT))
1107 break;
1108
1109 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1110 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1111 od_table->OverDriveTable.UclkFmin,
1112 od_table->OverDriveTable.UclkFmax);
1113 break;
1114
1115 case SMU_OD_VDDGFX_OFFSET:
1116 if (!smu_v14_0_2_is_od_feature_supported(smu,
1117 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1118 break;
1119
1120 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1121 size += sysfs_emit_at(buf, size, "%dmV\n",
1122 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1123 break;
1124
1125 case SMU_OD_FAN_CURVE:
1126 if (!smu_v14_0_2_is_od_feature_supported(smu,
1127 PP_OD_FEATURE_FAN_CURVE_BIT))
1128 break;
1129
1130 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1131 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1132 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1133 i,
1134 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1135 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1136
1137 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1138 smu_v14_0_2_get_od_setting_limits(smu,
1139 PP_OD_FEATURE_FAN_CURVE_TEMP,
1140 &min_value,
1141 &max_value);
1142 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1143 min_value, max_value);
1144
1145 smu_v14_0_2_get_od_setting_limits(smu,
1146 PP_OD_FEATURE_FAN_CURVE_PWM,
1147 &min_value,
1148 &max_value);
1149 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1150 min_value, max_value);
1151
1152 break;
1153
1154 case SMU_OD_ACOUSTIC_LIMIT:
1155 if (!smu_v14_0_2_is_od_feature_supported(smu,
1156 PP_OD_FEATURE_FAN_CURVE_BIT))
1157 break;
1158
1159 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1160 size += sysfs_emit_at(buf, size, "%d\n",
1161 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1162
1163 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1164 smu_v14_0_2_get_od_setting_limits(smu,
1165 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1166 &min_value,
1167 &max_value);
1168 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1169 min_value, max_value);
1170 break;
1171
1172 case SMU_OD_ACOUSTIC_TARGET:
1173 if (!smu_v14_0_2_is_od_feature_supported(smu,
1174 PP_OD_FEATURE_FAN_CURVE_BIT))
1175 break;
1176
1177 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1178 size += sysfs_emit_at(buf, size, "%d\n",
1179 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1180
1181 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1182 smu_v14_0_2_get_od_setting_limits(smu,
1183 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1184 &min_value,
1185 &max_value);
1186 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1187 min_value, max_value);
1188 break;
1189
1190 case SMU_OD_FAN_TARGET_TEMPERATURE:
1191 if (!smu_v14_0_2_is_od_feature_supported(smu,
1192 PP_OD_FEATURE_FAN_CURVE_BIT))
1193 break;
1194
1195 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1196 size += sysfs_emit_at(buf, size, "%d\n",
1197 (int)od_table->OverDriveTable.FanTargetTemperature);
1198
1199 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1200 smu_v14_0_2_get_od_setting_limits(smu,
1201 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1202 &min_value,
1203 &max_value);
1204 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1205 min_value, max_value);
1206 break;
1207
1208 case SMU_OD_FAN_MINIMUM_PWM:
1209 if (!smu_v14_0_2_is_od_feature_supported(smu,
1210 PP_OD_FEATURE_FAN_CURVE_BIT))
1211 break;
1212
1213 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1214 size += sysfs_emit_at(buf, size, "%d\n",
1215 (int)od_table->OverDriveTable.FanMinimumPwm);
1216
1217 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1218 smu_v14_0_2_get_od_setting_limits(smu,
1219 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1220 &min_value,
1221 &max_value);
1222 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1223 min_value, max_value);
1224 break;
1225
1226 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1227 if (!smu_v14_0_2_is_od_feature_supported(smu,
1228 PP_OD_FEATURE_ZERO_FAN_BIT))
1229 break;
1230
1231 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1232 size += sysfs_emit_at(buf, size, "%d\n",
1233 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1234
1235 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1236 smu_v14_0_2_get_od_setting_limits(smu,
1237 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1238 &min_value,
1239 &max_value);
1240 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1241 min_value, max_value);
1242 break;
1243
1244 case SMU_OD_RANGE:
1245 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1246 !smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1247 !smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1248 break;
1249
1250 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1251
1252 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1253 smu_v14_0_2_get_od_setting_limits(smu,
1254 PP_OD_FEATURE_GFXCLK_FMAX,
1255 &min_value,
1256 &max_value);
1257 size += sysfs_emit_at(buf, size, "SCLK_OFFSET: %7dMhz %10uMhz\n",
1258 min_value, max_value);
1259 }
1260
1261 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1262 smu_v14_0_2_get_od_setting_limits(smu,
1263 PP_OD_FEATURE_UCLK_FMIN,
1264 &min_value,
1265 NULL);
1266 smu_v14_0_2_get_od_setting_limits(smu,
1267 PP_OD_FEATURE_UCLK_FMAX,
1268 NULL,
1269 &max_value);
1270 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1271 min_value, max_value);
1272 }
1273
1274 if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1275 smu_v14_0_2_get_od_setting_limits(smu,
1276 PP_OD_FEATURE_GFX_VF_CURVE,
1277 &min_value,
1278 &max_value);
1279 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1280 min_value, max_value);
1281 }
1282 break;
1283
1284 default:
1285 break;
1286 }
1287
1288 if (single_dpm_table) {
1289 ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type,
1290 &curr_freq);
1291 if (ret) {
1292 dev_err(smu->adev->dev,
1293 "Failed to get current clock freq!");
1294 return ret;
1295 }
1296 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table,
1297 curr_freq, buf, offset);
1298 }
1299
1300 *offset += size - start_offset;
1301
1302 return 0;
1303 }
1304
smu_v14_0_2_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1305 static int smu_v14_0_2_force_clk_levels(struct smu_context *smu,
1306 enum smu_clk_type clk_type,
1307 uint32_t mask)
1308 {
1309 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1310 struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1311 struct smu_dpm_table *single_dpm_table;
1312 uint32_t soft_min_level, soft_max_level;
1313 uint32_t min_freq, max_freq;
1314 int ret = 0;
1315
1316 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1317 soft_max_level = mask ? (fls(mask) - 1) : 0;
1318
1319 switch (clk_type) {
1320 case SMU_GFXCLK:
1321 case SMU_SCLK:
1322 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1323 break;
1324 case SMU_MCLK:
1325 case SMU_UCLK:
1326 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1327 break;
1328 case SMU_SOCCLK:
1329 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1330 break;
1331 case SMU_FCLK:
1332 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1333 break;
1334 case SMU_VCLK:
1335 case SMU_VCLK1:
1336 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1337 break;
1338 case SMU_DCLK:
1339 case SMU_DCLK1:
1340 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1341 break;
1342 default:
1343 break;
1344 }
1345
1346 switch (clk_type) {
1347 case SMU_GFXCLK:
1348 case SMU_SCLK:
1349 case SMU_MCLK:
1350 case SMU_UCLK:
1351 case SMU_SOCCLK:
1352 case SMU_FCLK:
1353 case SMU_VCLK:
1354 case SMU_VCLK1:
1355 case SMU_DCLK:
1356 case SMU_DCLK1:
1357 if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) {
1358 /* There is only 2 levels for fine grained DPM */
1359 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1360 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1361 } else {
1362 if ((soft_max_level >= single_dpm_table->count) ||
1363 (soft_min_level >= single_dpm_table->count))
1364 return -EINVAL;
1365 }
1366
1367 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1368 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1369
1370 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1371 clk_type,
1372 min_freq,
1373 max_freq,
1374 false);
1375 break;
1376 case SMU_DCEFCLK:
1377 case SMU_PCIE:
1378 default:
1379 break;
1380 }
1381
1382 return ret;
1383 }
1384
smu_v14_0_2_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)1385 static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu,
1386 uint8_t pcie_gen_cap,
1387 uint8_t pcie_width_cap)
1388 {
1389 struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1390 struct smu_pcie_table *pcie_table =
1391 &dpm_context->dpm_tables.pcie_table;
1392 int lclk_levels;
1393 uint32_t smu_pcie_arg;
1394 uint32_t link_level;
1395 struct smu_table_context *table_context = &smu->smu_table;
1396 PPTable_t *pptable = table_context->driver_pptable;
1397 SkuTable_t *skutable = &pptable->SkuTable;
1398 int ret = 0;
1399 int i;
1400
1401 pcie_table->lclk_levels = 0;
1402 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
1403 if (!skutable->PcieGenSpeed[link_level] &&
1404 !skutable->PcieLaneCount[link_level] &&
1405 !skutable->LclkFreq[link_level])
1406 continue;
1407
1408 pcie_table->pcie_gen[pcie_table->lclk_levels] =
1409 skutable->PcieGenSpeed[link_level];
1410 pcie_table->pcie_lane[pcie_table->lclk_levels] =
1411 skutable->PcieLaneCount[link_level];
1412 pcie_table->lclk_freq[pcie_table->lclk_levels] =
1413 skutable->LclkFreq[link_level];
1414 pcie_table->lclk_levels++;
1415 }
1416 lclk_levels = pcie_table->lclk_levels;
1417 if (!lclk_levels)
1418 return 0;
1419
1420 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
1421 if (pcie_table->pcie_gen[lclk_levels - 1] < pcie_gen_cap)
1422 pcie_gen_cap = pcie_table->pcie_gen[lclk_levels - 1];
1423
1424 if (pcie_table->pcie_lane[lclk_levels - 1] < pcie_width_cap)
1425 pcie_width_cap = pcie_table->pcie_lane[lclk_levels - 1];
1426
1427 /* Force all levels to use the same settings */
1428 for (i = 0; i < lclk_levels; i++) {
1429 pcie_table->pcie_gen[i] = pcie_gen_cap;
1430 pcie_table->pcie_lane[i] = pcie_width_cap;
1431 smu_pcie_arg = i << 16;
1432 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1433 smu_pcie_arg |= pcie_table->pcie_lane[i];
1434
1435 ret = smu_cmn_send_smc_msg_with_param(smu,
1436 SMU_MSG_OverridePcieParameters,
1437 smu_pcie_arg,
1438 NULL);
1439 if (ret)
1440 break;
1441 }
1442 } else {
1443 for (i = 0; i < lclk_levels; i++) {
1444 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
1445 pcie_table->pcie_lane[i] > pcie_width_cap) {
1446 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ?
1447 pcie_gen_cap : pcie_table->pcie_gen[i];
1448 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ?
1449 pcie_width_cap : pcie_table->pcie_lane[i];
1450 smu_pcie_arg = i << 16;
1451 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1452 smu_pcie_arg |= pcie_table->pcie_lane[i];
1453
1454 ret = smu_cmn_send_smc_msg_with_param(smu,
1455 SMU_MSG_OverridePcieParameters,
1456 smu_pcie_arg,
1457 NULL);
1458 if (ret)
1459 break;
1460 }
1461 }
1462 }
1463
1464 return ret;
1465 }
1466
1467 static const struct smu_temperature_range smu14_thermal_policy[] = {
1468 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1469 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1470 };
1471
smu_v14_0_2_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1472 static int smu_v14_0_2_get_thermal_temperature_range(struct smu_context *smu,
1473 struct smu_temperature_range *range)
1474 {
1475 struct smu_table_context *table_context = &smu->smu_table;
1476 struct smu_14_0_2_powerplay_table *powerplay_table =
1477 table_context->power_play_table;
1478 PPTable_t *pptable = smu->smu_table.driver_pptable;
1479
1480 if (amdgpu_sriov_vf(smu->adev))
1481 return 0;
1482
1483 if (!range)
1484 return -EINVAL;
1485
1486 memcpy(range, &smu14_thermal_policy[0], sizeof(struct smu_temperature_range));
1487
1488 range->max = pptable->CustomSkuTable.TemperatureLimit[TEMP_EDGE] *
1489 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1490 range->edge_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1491 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1492 range->hotspot_crit_max = pptable->CustomSkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1493 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1494 range->hotspot_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1495 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1496 range->mem_crit_max = pptable->CustomSkuTable.TemperatureLimit[TEMP_MEM] *
1497 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1498 range->mem_emergency_max = (pptable->CustomSkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1499 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1500 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1501 range->software_shutdown_temp_offset = pptable->CustomSkuTable.FanAbnormalTempLimitOffset;
1502
1503 return 0;
1504 }
1505
smu_v14_0_2_populate_umd_state_clk(struct smu_context * smu)1506 static int smu_v14_0_2_populate_umd_state_clk(struct smu_context *smu)
1507 {
1508 struct smu_14_0_dpm_context *dpm_context =
1509 smu->smu_dpm.dpm_context;
1510 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1511 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
1512 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
1513 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
1514 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
1515 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
1516 struct smu_umd_pstate_table *pstate_table =
1517 &smu->pstate_table;
1518 struct smu_table_context *table_context = &smu->smu_table;
1519 PPTable_t *pptable = table_context->driver_pptable;
1520 DriverReportedClocks_t driver_clocks =
1521 pptable->SkuTable.DriverReportedClocks;
1522
1523 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
1524 if (driver_clocks.GameClockAc &&
1525 (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table)))
1526 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
1527 else
1528 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
1529
1530 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
1531 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
1532
1533 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
1534 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
1535
1536 pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table);
1537 pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table);
1538
1539 pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table);
1540 pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table);
1541
1542 pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table);
1543 pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table);
1544
1545 if (driver_clocks.BaseClockAc &&
1546 driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table))
1547 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
1548 else
1549 pstate_table->gfxclk_pstate.standard =
1550 SMU_DPM_TABLE_MAX(gfx_table);
1551 pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table);
1552 pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table);
1553 pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table);
1554 pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table);
1555 pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table);
1556
1557 return 0;
1558 }
1559
smu_v14_0_2_get_unique_id(struct smu_context * smu)1560 static void smu_v14_0_2_get_unique_id(struct smu_context *smu)
1561 {
1562 struct smu_table_context *smu_table = &smu->smu_table;
1563 SmuMetrics_t *metrics =
1564 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
1565 struct amdgpu_device *adev = smu->adev;
1566 uint32_t upper32 = 0, lower32 = 0;
1567 int ret;
1568
1569 ret = smu_cmn_get_metrics_table(smu, NULL, false);
1570 if (ret)
1571 goto out;
1572
1573 upper32 = metrics->PublicSerialNumberUpper;
1574 lower32 = metrics->PublicSerialNumberLower;
1575
1576 out:
1577 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1578 }
1579
smu_v14_0_2_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1580 static int smu_v14_0_2_get_fan_speed_pwm(struct smu_context *smu,
1581 uint32_t *speed)
1582 {
1583 int ret;
1584
1585 if (!speed)
1586 return -EINVAL;
1587
1588 ret = smu_v14_0_2_get_smu_metrics_data(smu,
1589 METRICS_CURR_FANPWM,
1590 speed);
1591 if (ret) {
1592 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
1593 return ret;
1594 }
1595
1596 /* Convert the PMFW output which is in percent to pwm(255) based */
1597 *speed = min(*speed * 255 / 100, (uint32_t)255);
1598
1599 return 0;
1600 }
1601
smu_v14_0_2_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1602 static int smu_v14_0_2_get_fan_speed_rpm(struct smu_context *smu,
1603 uint32_t *speed)
1604 {
1605 if (!speed)
1606 return -EINVAL;
1607
1608 return smu_v14_0_2_get_smu_metrics_data(smu,
1609 METRICS_CURR_FANSPEED,
1610 speed);
1611 }
1612
smu_v14_0_2_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1613 static int smu_v14_0_2_get_power_limit(struct smu_context *smu,
1614 uint32_t *current_power_limit,
1615 uint32_t *default_power_limit,
1616 uint32_t *max_power_limit,
1617 uint32_t *min_power_limit)
1618 {
1619 struct smu_table_context *table_context = &smu->smu_table;
1620 struct smu_14_0_2_powerplay_table *powerplay_table =
1621 table_context->power_play_table;
1622 PPTable_t *pptable = table_context->driver_pptable;
1623 CustomSkuTable_t *skutable = &pptable->CustomSkuTable;
1624 int16_t od_percent_upper = 0, od_percent_lower = 0;
1625 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
1626 uint32_t power_limit;
1627
1628 if (smu_v14_0_get_current_power_limit(smu, &power_limit))
1629 power_limit = smu->adev->pm.ac_power ?
1630 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1631 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1632
1633 if (current_power_limit)
1634 *current_power_limit = power_limit;
1635 if (default_power_limit)
1636 *default_power_limit = power_limit;
1637
1638 if (powerplay_table) {
1639 if (smu->od_enabled &&
1640 smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
1641 od_percent_upper = pptable->SkuTable.OverDriveLimitsBasicMax.Ppt;
1642 od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt;
1643 } else if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
1644 od_percent_upper = 0;
1645 od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt;
1646 }
1647 }
1648
1649 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
1650 od_percent_upper, od_percent_lower, power_limit);
1651
1652 if (max_power_limit) {
1653 *max_power_limit = msg_limit * (100 + od_percent_upper);
1654 *max_power_limit /= 100;
1655 }
1656
1657 if (min_power_limit) {
1658 *min_power_limit = power_limit * (100 + od_percent_lower);
1659 *min_power_limit /= 100;
1660 }
1661
1662 return 0;
1663 }
1664
smu_v14_0_2_get_power_profile_mode(struct smu_context * smu,char * buf)1665 static int smu_v14_0_2_get_power_profile_mode(struct smu_context *smu,
1666 char *buf)
1667 {
1668 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1669 DpmActivityMonitorCoeffInt_t *activity_monitor =
1670 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1671 static const char *title[] = {
1672 "PROFILE_INDEX(NAME)",
1673 "CLOCK_TYPE(NAME)",
1674 "FPS",
1675 "MinActiveFreqType",
1676 "MinActiveFreq",
1677 "BoosterFreqType",
1678 "BoosterFreq",
1679 "PD_Data_limit_c",
1680 "PD_Data_error_coeff",
1681 "PD_Data_error_rate_coeff"};
1682 int16_t workload_type = 0;
1683 uint32_t i, size = 0;
1684 int result = 0;
1685
1686 if (!buf)
1687 return -EINVAL;
1688
1689 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
1690 title[0], title[1], title[2], title[3], title[4], title[5],
1691 title[6], title[7], title[8], title[9]);
1692
1693 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1694 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1695 workload_type = smu_cmn_to_asic_specific_index(smu,
1696 CMN2ASIC_MAPPING_WORKLOAD,
1697 i);
1698 if (workload_type == -ENOTSUPP)
1699 continue;
1700 else if (workload_type < 0)
1701 return -EINVAL;
1702
1703 result = smu_cmn_update_table(smu,
1704 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1705 workload_type,
1706 (void *)(&activity_monitor_external),
1707 false);
1708 if (result) {
1709 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1710 return result;
1711 }
1712
1713 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1714 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1715
1716 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1717 " ",
1718 0,
1719 "GFXCLK",
1720 activity_monitor->Gfx_FPS,
1721 activity_monitor->Gfx_MinActiveFreqType,
1722 activity_monitor->Gfx_MinActiveFreq,
1723 activity_monitor->Gfx_BoosterFreqType,
1724 activity_monitor->Gfx_BoosterFreq,
1725 activity_monitor->Gfx_PD_Data_limit_c,
1726 activity_monitor->Gfx_PD_Data_error_coeff,
1727 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1728
1729 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1730 " ",
1731 1,
1732 "FCLK",
1733 activity_monitor->Fclk_FPS,
1734 activity_monitor->Fclk_MinActiveFreqType,
1735 activity_monitor->Fclk_MinActiveFreq,
1736 activity_monitor->Fclk_BoosterFreqType,
1737 activity_monitor->Fclk_BoosterFreq,
1738 activity_monitor->Fclk_PD_Data_limit_c,
1739 activity_monitor->Fclk_PD_Data_error_coeff,
1740 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1741 }
1742
1743 return size;
1744 }
1745
1746 #define SMU_14_0_2_CUSTOM_PARAMS_COUNT 9
1747 #define SMU_14_0_2_CUSTOM_PARAMS_CLOCK_COUNT 2
1748 #define SMU_14_0_2_CUSTOM_PARAMS_SIZE (SMU_14_0_2_CUSTOM_PARAMS_CLOCK_COUNT * SMU_14_0_2_CUSTOM_PARAMS_COUNT * sizeof(long))
1749
smu_v14_0_2_set_power_profile_mode_coeff(struct smu_context * smu,long * input)1750 static int smu_v14_0_2_set_power_profile_mode_coeff(struct smu_context *smu,
1751 long *input)
1752 {
1753 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1754 DpmActivityMonitorCoeffInt_t *activity_monitor =
1755 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1756 int ret, idx;
1757
1758 ret = smu_cmn_update_table(smu,
1759 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1760 WORKLOAD_PPLIB_CUSTOM_BIT,
1761 (void *)(&activity_monitor_external),
1762 false);
1763 if (ret) {
1764 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1765 return ret;
1766 }
1767
1768 idx = 0 * SMU_14_0_2_CUSTOM_PARAMS_COUNT;
1769 if (input[idx]) {
1770 /* Gfxclk */
1771 activity_monitor->Gfx_FPS = input[idx + 1];
1772 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2];
1773 activity_monitor->Gfx_MinActiveFreq = input[idx + 3];
1774 activity_monitor->Gfx_BoosterFreqType = input[idx + 4];
1775 activity_monitor->Gfx_BoosterFreq = input[idx + 5];
1776 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6];
1777 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7];
1778 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8];
1779 }
1780 idx = 1 * SMU_14_0_2_CUSTOM_PARAMS_COUNT;
1781 if (input[idx]) {
1782 /* Fclk */
1783 activity_monitor->Fclk_FPS = input[idx + 1];
1784 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2];
1785 activity_monitor->Fclk_MinActiveFreq = input[idx + 3];
1786 activity_monitor->Fclk_BoosterFreqType = input[idx + 4];
1787 activity_monitor->Fclk_BoosterFreq = input[idx + 5];
1788 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6];
1789 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7];
1790 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8];
1791 }
1792
1793 ret = smu_cmn_update_table(smu,
1794 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1795 WORKLOAD_PPLIB_CUSTOM_BIT,
1796 (void *)(&activity_monitor_external),
1797 true);
1798 if (ret) {
1799 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1800 return ret;
1801 }
1802
1803 return ret;
1804 }
1805
smu_v14_0_2_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1806 static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu,
1807 u32 workload_mask,
1808 long *custom_params,
1809 u32 custom_params_max_idx)
1810 {
1811 u32 backend_workload_mask = 0;
1812 int ret, idx = -1, i;
1813
1814 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1815 &backend_workload_mask);
1816
1817 /* disable deep sleep if compute is enabled */
1818 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE))
1819 smu_v14_0_deep_sleep_control(smu, false);
1820 else
1821 smu_v14_0_deep_sleep_control(smu, true);
1822
1823 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
1824 if (!smu->custom_profile_params) {
1825 smu->custom_profile_params =
1826 kzalloc(SMU_14_0_2_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
1827 if (!smu->custom_profile_params)
1828 return -ENOMEM;
1829 }
1830 if (custom_params && custom_params_max_idx) {
1831 if (custom_params_max_idx != SMU_14_0_2_CUSTOM_PARAMS_COUNT)
1832 return -EINVAL;
1833 if (custom_params[0] >= SMU_14_0_2_CUSTOM_PARAMS_CLOCK_COUNT)
1834 return -EINVAL;
1835 idx = custom_params[0] * SMU_14_0_2_CUSTOM_PARAMS_COUNT;
1836 smu->custom_profile_params[idx] = 1;
1837 for (i = 1; i < custom_params_max_idx; i++)
1838 smu->custom_profile_params[idx + i] = custom_params[i];
1839 }
1840 ret = smu_v14_0_2_set_power_profile_mode_coeff(smu,
1841 smu->custom_profile_params);
1842 if (ret) {
1843 if (idx != -1)
1844 smu->custom_profile_params[idx] = 0;
1845 return ret;
1846 }
1847 } else if (smu->custom_profile_params) {
1848 memset(smu->custom_profile_params, 0, SMU_14_0_2_CUSTOM_PARAMS_SIZE);
1849 }
1850
1851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1852 backend_workload_mask, NULL);
1853 if (ret) {
1854 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
1855 workload_mask);
1856 if (idx != -1)
1857 smu->custom_profile_params[idx] = 0;
1858 return ret;
1859 }
1860
1861 return ret;
1862 }
1863
smu_v14_0_2_baco_enter(struct smu_context * smu)1864 static int smu_v14_0_2_baco_enter(struct smu_context *smu)
1865 {
1866 struct smu_baco_context *smu_baco = &smu->smu_baco;
1867 struct amdgpu_device *adev = smu->adev;
1868
1869 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
1870 return smu_v14_0_baco_set_armd3_sequence(smu,
1871 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO);
1872 else
1873 return smu_v14_0_baco_enter(smu);
1874 }
1875
smu_v14_0_2_baco_exit(struct smu_context * smu)1876 static int smu_v14_0_2_baco_exit(struct smu_context *smu)
1877 {
1878 struct amdgpu_device *adev = smu->adev;
1879
1880 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
1881 /* Wait for PMFW handling for the Dstate change */
1882 usleep_range(10000, 11000);
1883 return smu_v14_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
1884 } else {
1885 return smu_v14_0_baco_exit(smu);
1886 }
1887 }
1888
smu_v14_0_2_is_mode1_reset_supported(struct smu_context * smu)1889 static bool smu_v14_0_2_is_mode1_reset_supported(struct smu_context *smu)
1890 {
1891 // TODO
1892
1893 return true;
1894 }
1895
smu_v14_0_2_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1896 static int smu_v14_0_2_i2c_xfer(struct i2c_adapter *i2c_adap,
1897 struct i2c_msg *msg, int num_msgs)
1898 {
1899 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1900 struct amdgpu_device *adev = smu_i2c->adev;
1901 struct smu_context *smu = adev->powerplay.pp_handle;
1902 struct smu_table_context *smu_table = &smu->smu_table;
1903 struct smu_table *table = &smu_table->driver_table;
1904 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1905 int i, j, r, c;
1906 u16 dir;
1907
1908 if (!adev->pm.dpm_enabled)
1909 return -EBUSY;
1910
1911 req = kzalloc_obj(*req);
1912 if (!req)
1913 return -ENOMEM;
1914
1915 req->I2CcontrollerPort = smu_i2c->port;
1916 req->I2CSpeed = I2C_SPEED_FAST_400K;
1917 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1918 dir = msg[0].flags & I2C_M_RD;
1919
1920 for (c = i = 0; i < num_msgs; i++) {
1921 for (j = 0; j < msg[i].len; j++, c++) {
1922 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1923
1924 if (!(msg[i].flags & I2C_M_RD)) {
1925 /* write */
1926 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1927 cmd->ReadWriteData = msg[i].buf[j];
1928 }
1929
1930 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1931 /* The direction changes.
1932 */
1933 dir = msg[i].flags & I2C_M_RD;
1934 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1935 }
1936
1937 req->NumCmds++;
1938
1939 /*
1940 * Insert STOP if we are at the last byte of either last
1941 * message for the transaction or the client explicitly
1942 * requires a STOP at this particular message.
1943 */
1944 if ((j == msg[i].len - 1) &&
1945 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1946 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1947 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1948 }
1949 }
1950 }
1951 mutex_lock(&adev->pm.mutex);
1952 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1953 mutex_unlock(&adev->pm.mutex);
1954 if (r)
1955 goto fail;
1956
1957 for (c = i = 0; i < num_msgs; i++) {
1958 if (!(msg[i].flags & I2C_M_RD)) {
1959 c += msg[i].len;
1960 continue;
1961 }
1962 for (j = 0; j < msg[i].len; j++, c++) {
1963 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1964
1965 msg[i].buf[j] = cmd->ReadWriteData;
1966 }
1967 }
1968 r = num_msgs;
1969 fail:
1970 kfree(req);
1971 return r;
1972 }
1973
smu_v14_0_2_i2c_func(struct i2c_adapter * adap)1974 static u32 smu_v14_0_2_i2c_func(struct i2c_adapter *adap)
1975 {
1976 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1977 }
1978
1979 static const struct i2c_algorithm smu_v14_0_2_i2c_algo = {
1980 .master_xfer = smu_v14_0_2_i2c_xfer,
1981 .functionality = smu_v14_0_2_i2c_func,
1982 };
1983
1984 static const struct i2c_adapter_quirks smu_v14_0_2_i2c_control_quirks = {
1985 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1986 .max_read_len = MAX_SW_I2C_COMMANDS,
1987 .max_write_len = MAX_SW_I2C_COMMANDS,
1988 .max_comb_1st_msg_len = 2,
1989 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1990 };
1991
smu_v14_0_2_i2c_control_init(struct smu_context * smu)1992 static int smu_v14_0_2_i2c_control_init(struct smu_context *smu)
1993 {
1994 struct amdgpu_device *adev = smu->adev;
1995 int res, i;
1996
1997 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1998 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1999 struct i2c_adapter *control = &smu_i2c->adapter;
2000
2001 smu_i2c->adev = adev;
2002 smu_i2c->port = i;
2003 mutex_init(&smu_i2c->mutex);
2004 control->owner = THIS_MODULE;
2005 control->dev.parent = &adev->pdev->dev;
2006 control->algo = &smu_v14_0_2_i2c_algo;
2007 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2008 control->quirks = &smu_v14_0_2_i2c_control_quirks;
2009 i2c_set_adapdata(control, smu_i2c);
2010
2011 res = devm_i2c_add_adapter(adev->dev, control);
2012 if (res) {
2013 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2014 return res;
2015 }
2016 }
2017
2018 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2019 /* XXX ideally this would be something in a vbios data table */
2020 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2021 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2022
2023 return 0;
2024 }
2025
smu_v14_0_2_i2c_control_fini(struct smu_context * smu)2026 static void smu_v14_0_2_i2c_control_fini(struct smu_context *smu)
2027 {
2028 struct amdgpu_device *adev = smu->adev;
2029
2030 adev->pm.ras_eeprom_i2c_bus = NULL;
2031 adev->pm.fru_eeprom_i2c_bus = NULL;
2032 }
2033
smu_v14_0_2_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2034 static int smu_v14_0_2_set_mp1_state(struct smu_context *smu,
2035 enum pp_mp1_state mp1_state)
2036 {
2037 int ret;
2038
2039 switch (mp1_state) {
2040 case PP_MP1_STATE_UNLOAD:
2041 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2042 break;
2043 default:
2044 /* Ignore others */
2045 ret = 0;
2046 }
2047
2048 return ret;
2049 }
2050
smu_v14_0_2_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2051 static int smu_v14_0_2_set_df_cstate(struct smu_context *smu,
2052 enum pp_df_cstate state)
2053 {
2054 return smu_cmn_send_smc_msg_with_param(smu,
2055 SMU_MSG_DFCstateControl,
2056 state,
2057 NULL);
2058 }
2059
smu_v14_0_2_mode1_reset(struct smu_context * smu)2060 static int smu_v14_0_2_mode1_reset(struct smu_context *smu)
2061 {
2062 int ret = 0;
2063
2064 ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
2065 if (!ret) {
2066 if (amdgpu_emu_mode == 1) {
2067 msleep(50000);
2068 } else {
2069 /* disable mmio access while doing mode 1 reset*/
2070 smu->adev->no_hw_access = true;
2071 /* ensure no_hw_access is globally visible before any MMIO */
2072 smp_mb();
2073 msleep(1000);
2074 }
2075 }
2076
2077 return ret;
2078 }
2079
smu_v14_0_2_mode2_reset(struct smu_context * smu)2080 static int smu_v14_0_2_mode2_reset(struct smu_context *smu)
2081 {
2082 int ret = 0;
2083
2084 // TODO
2085
2086 return ret;
2087 }
2088
smu_v14_0_2_enable_gfx_features(struct smu_context * smu)2089 static int smu_v14_0_2_enable_gfx_features(struct smu_context *smu)
2090 {
2091 struct amdgpu_device *adev = smu->adev;
2092
2093 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2))
2094 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2095 FEATURE_PWR_GFX, NULL);
2096 else
2097 return -EOPNOTSUPP;
2098 }
2099
smu_v14_0_2_init_msg_ctl(struct smu_context * smu)2100 static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu)
2101 {
2102 struct amdgpu_device *adev = smu->adev;
2103 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2104
2105 ctl->smu = smu;
2106 mutex_init(&ctl->lock);
2107 ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66);
2108 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90);
2109 ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82);
2110 ctl->config.num_arg_regs = 1;
2111 ctl->ops = &smu_msg_v1_ops;
2112 ctl->default_timeout = adev->usec_timeout * 20;
2113 ctl->message_map = smu_v14_0_2_message_map;
2114 ctl->flags = 0;
2115
2116 /* Set up debug mailbox registers */
2117 ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53);
2118 ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75);
2119 ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);
2120 ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;
2121 }
2122
smu_v14_0_2_get_gpu_metrics(struct smu_context * smu,void ** table)2123 static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
2124 void **table)
2125 {
2126 struct gpu_metrics_v1_3 *gpu_metrics =
2127 (struct gpu_metrics_v1_3 *)smu_driver_table_ptr(
2128 smu, SMU_DRIVER_TABLE_GPU_METRICS);
2129 SmuMetricsExternal_t metrics_ext;
2130 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2131 int ret = 0;
2132
2133 ret = smu_cmn_get_metrics_table(smu,
2134 &metrics_ext,
2135 true);
2136 if (ret)
2137 return ret;
2138
2139 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2140
2141 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2142 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2143 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2144 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2145 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2146 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2147 metrics->AvgTemperature[TEMP_VR_MEM1]);
2148
2149 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2150 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2151 gpu_metrics->average_mm_activity = max(metrics->AverageVcn0ActivityPercentage,
2152 metrics->Vcn1ActivityPercentage);
2153
2154 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2155 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2156
2157 if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
2158 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2159 else
2160 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2161
2162 if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
2163 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2164 else
2165 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2166
2167 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2168 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2169 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2170 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2171
2172 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2173 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2174 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2175 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2176 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2177 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_0];
2178 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_0];
2179
2180 gpu_metrics->throttle_status =
2181 smu_v14_0_2_get_throttler_status(metrics);
2182 gpu_metrics->indep_throttle_status =
2183 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2184 smu_v14_0_2_throttler_map);
2185
2186 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2187
2188 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2189 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2190 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2191 else
2192 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2193
2194 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2195
2196 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
2197 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_VDD_SOC];
2198 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VDDIO_MEM];
2199
2200 *table = (void *)gpu_metrics;
2201
2202 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
2203
2204 return sizeof(struct gpu_metrics_v1_3);
2205 }
2206
smu_v14_0_2_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2207 static void smu_v14_0_2_dump_od_table(struct smu_context *smu,
2208 OverDriveTableExternal_t *od_table)
2209 {
2210 struct amdgpu_device *adev = smu->adev;
2211
2212 dev_dbg(adev->dev, "OD: Gfxclk offset: (%d)\n", od_table->OverDriveTable.GfxclkFoffset);
2213 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
2214 od_table->OverDriveTable.UclkFmax);
2215 }
2216
smu_v14_0_2_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2217 static int smu_v14_0_2_upload_overdrive_table(struct smu_context *smu,
2218 OverDriveTableExternal_t *od_table)
2219 {
2220 int ret;
2221 ret = smu_cmn_update_table(smu,
2222 SMU_TABLE_OVERDRIVE,
2223 0,
2224 (void *)od_table,
2225 true);
2226 if (ret)
2227 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2228
2229 return ret;
2230 }
2231
smu_v14_0_2_set_supported_od_feature_mask(struct smu_context * smu)2232 static void smu_v14_0_2_set_supported_od_feature_mask(struct smu_context *smu)
2233 {
2234 struct amdgpu_device *adev = smu->adev;
2235
2236 if (smu_v14_0_2_is_od_feature_supported(smu,
2237 PP_OD_FEATURE_FAN_CURVE_BIT))
2238 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2239 OD_OPS_SUPPORT_FAN_CURVE_SET |
2240 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2241 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2242 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2243 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2244 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2245 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2246 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2247 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2248 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2249 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET;
2250 }
2251
smu_v14_0_2_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)2252 static int smu_v14_0_2_get_overdrive_table(struct smu_context *smu,
2253 OverDriveTableExternal_t *od_table)
2254 {
2255 int ret;
2256 ret = smu_cmn_update_table(smu,
2257 SMU_TABLE_OVERDRIVE,
2258 0,
2259 (void *)od_table,
2260 false);
2261 if (ret)
2262 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2263
2264 return ret;
2265 }
2266
smu_v14_0_2_set_default_od_settings(struct smu_context * smu)2267 static int smu_v14_0_2_set_default_od_settings(struct smu_context *smu)
2268 {
2269 OverDriveTableExternal_t *od_table =
2270 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2271 OverDriveTableExternal_t *boot_od_table =
2272 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2273 OverDriveTableExternal_t *user_od_table =
2274 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2275 OverDriveTableExternal_t user_od_table_bak;
2276 int ret;
2277 int i;
2278
2279 ret = smu_v14_0_2_get_overdrive_table(smu, boot_od_table);
2280 if (ret)
2281 return ret;
2282
2283 smu_v14_0_2_dump_od_table(smu, boot_od_table);
2284
2285 memcpy(od_table,
2286 boot_od_table,
2287 sizeof(OverDriveTableExternal_t));
2288
2289 /*
2290 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2291 * but we have to preserve user defined values in "user_od_table".
2292 */
2293 if (!smu->adev->in_suspend) {
2294 memcpy(user_od_table,
2295 boot_od_table,
2296 sizeof(OverDriveTableExternal_t));
2297 smu->user_dpm_profile.user_od = false;
2298 } else if (smu->user_dpm_profile.user_od) {
2299 memcpy(&user_od_table_bak,
2300 user_od_table,
2301 sizeof(OverDriveTableExternal_t));
2302 memcpy(user_od_table,
2303 boot_od_table,
2304 sizeof(OverDriveTableExternal_t));
2305 user_od_table->OverDriveTable.GfxclkFoffset =
2306 user_od_table_bak.OverDriveTable.GfxclkFoffset;
2307 user_od_table->OverDriveTable.UclkFmin =
2308 user_od_table_bak.OverDriveTable.UclkFmin;
2309 user_od_table->OverDriveTable.UclkFmax =
2310 user_od_table_bak.OverDriveTable.UclkFmax;
2311 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2312 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2313 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2314 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2315 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2316 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2317 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2318 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2319 }
2320 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2321 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2322 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2323 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2324 user_od_table->OverDriveTable.FanTargetTemperature =
2325 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2326 user_od_table->OverDriveTable.FanMinimumPwm =
2327 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2328 user_od_table->OverDriveTable.FanZeroRpmEnable =
2329 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2330 }
2331
2332 smu_v14_0_2_set_supported_od_feature_mask(smu);
2333
2334 return 0;
2335 }
2336
smu_v14_0_2_restore_user_od_settings(struct smu_context * smu)2337 static int smu_v14_0_2_restore_user_od_settings(struct smu_context *smu)
2338 {
2339 struct smu_table_context *table_context = &smu->smu_table;
2340 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2341 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2342 int res;
2343
2344 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2345 BIT(PP_OD_FEATURE_UCLK_BIT) |
2346 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2347 BIT(PP_OD_FEATURE_FAN_CURVE_BIT) |
2348 BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
2349 res = smu_v14_0_2_upload_overdrive_table(smu, user_od_table);
2350 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2351 if (res == 0)
2352 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2353
2354 return res;
2355 }
2356
smu_v14_0_2_od_restore_table_single(struct smu_context * smu,long input)2357 static int smu_v14_0_2_od_restore_table_single(struct smu_context *smu, long input)
2358 {
2359 struct smu_table_context *table_context = &smu->smu_table;
2360 OverDriveTableExternal_t *boot_overdrive_table =
2361 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
2362 OverDriveTableExternal_t *od_table =
2363 (OverDriveTableExternal_t *)table_context->overdrive_table;
2364 struct amdgpu_device *adev = smu->adev;
2365 int i;
2366
2367 switch (input) {
2368 case PP_OD_EDIT_FAN_CURVE:
2369 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
2370 od_table->OverDriveTable.FanLinearTempPoints[i] =
2371 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
2372 od_table->OverDriveTable.FanLinearPwmPoints[i] =
2373 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
2374 }
2375 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2376 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2377 break;
2378 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
2379 od_table->OverDriveTable.FanZeroRpmEnable =
2380 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
2381 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
2382 break;
2383 case PP_OD_EDIT_ACOUSTIC_LIMIT:
2384 od_table->OverDriveTable.AcousticLimitRpmThreshold =
2385 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
2386 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2387 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2388 break;
2389 case PP_OD_EDIT_ACOUSTIC_TARGET:
2390 od_table->OverDriveTable.AcousticTargetRpmThreshold =
2391 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
2392 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2393 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2394 break;
2395 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
2396 od_table->OverDriveTable.FanTargetTemperature =
2397 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
2398 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2399 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2400 break;
2401 case PP_OD_EDIT_FAN_MINIMUM_PWM:
2402 od_table->OverDriveTable.FanMinimumPwm =
2403 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
2404 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2405 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2406 break;
2407 default:
2408 dev_info(adev->dev, "Invalid table index: %ld\n", input);
2409 return -EINVAL;
2410 }
2411
2412 return 0;
2413 }
2414
smu_v14_0_2_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2415 static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu,
2416 enum PP_OD_DPM_TABLE_COMMAND type,
2417 long input[],
2418 uint32_t size)
2419 {
2420 struct smu_table_context *table_context = &smu->smu_table;
2421 OverDriveTableExternal_t *od_table =
2422 (OverDriveTableExternal_t *)table_context->overdrive_table;
2423 struct amdgpu_device *adev = smu->adev;
2424 uint32_t offset_of_voltageoffset;
2425 int32_t minimum, maximum;
2426 uint32_t feature_ctrlmask;
2427 int i, ret = 0;
2428
2429 switch (type) {
2430 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2431 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
2432 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
2433 return -ENOTSUPP;
2434 }
2435
2436 if (size != 1) {
2437 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
2438 return -EINVAL;
2439 }
2440
2441 smu_v14_0_2_get_od_setting_limits(smu,
2442 PP_OD_FEATURE_GFXCLK_FMAX,
2443 &minimum,
2444 &maximum);
2445 if (input[0] < minimum ||
2446 input[0] > maximum) {
2447 dev_info(adev->dev, "GfxclkFoffset must be within [%d, %u]!\n",
2448 minimum, maximum);
2449 return -EINVAL;
2450 }
2451
2452 od_table->OverDriveTable.GfxclkFoffset = input[0];
2453 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
2454 break;
2455
2456 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2457 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
2458 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
2459 return -ENOTSUPP;
2460 }
2461
2462 for (i = 0; i < size; i += 2) {
2463 if (i + 2 > size) {
2464 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
2465 return -EINVAL;
2466 }
2467
2468 switch (input[i]) {
2469 case 0:
2470 smu_v14_0_2_get_od_setting_limits(smu,
2471 PP_OD_FEATURE_UCLK_FMIN,
2472 &minimum,
2473 &maximum);
2474 if (input[i + 1] < minimum ||
2475 input[i + 1] > maximum) {
2476 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
2477 input[i + 1], minimum, maximum);
2478 return -EINVAL;
2479 }
2480
2481 od_table->OverDriveTable.UclkFmin = input[i + 1];
2482 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
2483 break;
2484
2485 case 1:
2486 smu_v14_0_2_get_od_setting_limits(smu,
2487 PP_OD_FEATURE_UCLK_FMAX,
2488 &minimum,
2489 &maximum);
2490 if (input[i + 1] < minimum ||
2491 input[i + 1] > maximum) {
2492 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
2493 input[i + 1], minimum, maximum);
2494 return -EINVAL;
2495 }
2496
2497 od_table->OverDriveTable.UclkFmax = input[i + 1];
2498 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
2499 break;
2500
2501 default:
2502 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2503 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
2504 return -EINVAL;
2505 }
2506 }
2507
2508 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
2509 dev_err(adev->dev,
2510 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
2511 (uint32_t)od_table->OverDriveTable.UclkFmin,
2512 (uint32_t)od_table->OverDriveTable.UclkFmax);
2513 return -EINVAL;
2514 }
2515 break;
2516
2517 case PP_OD_EDIT_VDDGFX_OFFSET:
2518 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
2519 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
2520 return -ENOTSUPP;
2521 }
2522
2523 smu_v14_0_2_get_od_setting_limits(smu,
2524 PP_OD_FEATURE_GFX_VF_CURVE,
2525 &minimum,
2526 &maximum);
2527 if (input[0] < minimum ||
2528 input[0] > maximum) {
2529 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
2530 input[0], minimum, maximum);
2531 return -EINVAL;
2532 }
2533
2534 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2535 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
2536 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
2537 break;
2538
2539 case PP_OD_EDIT_FAN_CURVE:
2540 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2541 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2542 return -ENOTSUPP;
2543 }
2544
2545 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
2546 input[0] < 0)
2547 return -EINVAL;
2548
2549 smu_v14_0_2_get_od_setting_limits(smu,
2550 PP_OD_FEATURE_FAN_CURVE_TEMP,
2551 &minimum,
2552 &maximum);
2553 if (input[1] < minimum ||
2554 input[1] > maximum) {
2555 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
2556 input[1], minimum, maximum);
2557 return -EINVAL;
2558 }
2559
2560 smu_v14_0_2_get_od_setting_limits(smu,
2561 PP_OD_FEATURE_FAN_CURVE_PWM,
2562 &minimum,
2563 &maximum);
2564 if (input[2] < minimum ||
2565 input[2] > maximum) {
2566 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
2567 input[2], minimum, maximum);
2568 return -EINVAL;
2569 }
2570
2571 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
2572 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
2573 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
2574 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2575 break;
2576
2577 case PP_OD_EDIT_ACOUSTIC_LIMIT:
2578 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2579 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2580 return -ENOTSUPP;
2581 }
2582
2583 smu_v14_0_2_get_od_setting_limits(smu,
2584 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
2585 &minimum,
2586 &maximum);
2587 if (input[0] < minimum ||
2588 input[0] > maximum) {
2589 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
2590 input[0], minimum, maximum);
2591 return -EINVAL;
2592 }
2593
2594 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
2595 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2596 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2597 break;
2598
2599 case PP_OD_EDIT_ACOUSTIC_TARGET:
2600 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2601 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2602 return -ENOTSUPP;
2603 }
2604
2605 smu_v14_0_2_get_od_setting_limits(smu,
2606 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
2607 &minimum,
2608 &maximum);
2609 if (input[0] < minimum ||
2610 input[0] > maximum) {
2611 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
2612 input[0], minimum, maximum);
2613 return -EINVAL;
2614 }
2615
2616 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
2617 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2618 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2619 break;
2620
2621 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
2622 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2623 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2624 return -ENOTSUPP;
2625 }
2626
2627 smu_v14_0_2_get_od_setting_limits(smu,
2628 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
2629 &minimum,
2630 &maximum);
2631 if (input[0] < minimum ||
2632 input[0] > maximum) {
2633 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
2634 input[0], minimum, maximum);
2635 return -EINVAL;
2636 }
2637
2638 od_table->OverDriveTable.FanTargetTemperature = input[0];
2639 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2640 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2641 break;
2642
2643 case PP_OD_EDIT_FAN_MINIMUM_PWM:
2644 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
2645 dev_warn(adev->dev, "Fan curve setting not supported!\n");
2646 return -ENOTSUPP;
2647 }
2648
2649 smu_v14_0_2_get_od_setting_limits(smu,
2650 PP_OD_FEATURE_FAN_MINIMUM_PWM,
2651 &minimum,
2652 &maximum);
2653 if (input[0] < minimum ||
2654 input[0] > maximum) {
2655 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
2656 input[0], minimum, maximum);
2657 return -EINVAL;
2658 }
2659
2660 od_table->OverDriveTable.FanMinimumPwm = input[0];
2661 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
2662 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2663 break;
2664
2665 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
2666 if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
2667 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
2668 return -ENOTSUPP;
2669 }
2670
2671 smu_v14_0_2_get_od_setting_limits(smu,
2672 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
2673 &minimum,
2674 &maximum);
2675 if (input[0] < minimum ||
2676 input[0] > maximum) {
2677 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
2678 input[0], minimum, maximum);
2679 return -EINVAL;
2680 }
2681
2682 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
2683 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
2684 break;
2685
2686 case PP_OD_RESTORE_DEFAULT_TABLE:
2687 if (size == 1) {
2688 ret = smu_v14_0_2_od_restore_table_single(smu, input[0]);
2689 if (ret)
2690 return ret;
2691 } else {
2692 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
2693 memcpy(od_table,
2694 table_context->boot_overdrive_table,
2695 sizeof(OverDriveTableExternal_t));
2696 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
2697 }
2698 fallthrough;
2699 case PP_OD_COMMIT_DPM_TABLE:
2700 /*
2701 * The member below instructs PMFW the settings focused in
2702 * this single operation.
2703 * `uint32_t FeatureCtrlMask;`
2704 * It does not contain actual informations about user's custom
2705 * settings. Thus we do not cache it.
2706 */
2707 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
2708 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
2709 table_context->user_overdrive_table + offset_of_voltageoffset,
2710 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
2711 smu_v14_0_2_dump_od_table(smu, od_table);
2712
2713 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2714 if (ret) {
2715 dev_err(adev->dev, "Failed to upload overdrive table!\n");
2716 return ret;
2717 }
2718
2719 od_table->OverDriveTable.FeatureCtrlMask = 0;
2720 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
2721 (u8 *)od_table + offset_of_voltageoffset,
2722 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
2723
2724 if (!memcmp(table_context->user_overdrive_table,
2725 table_context->boot_overdrive_table,
2726 sizeof(OverDriveTableExternal_t)))
2727 smu->user_dpm_profile.user_od = false;
2728 else
2729 smu->user_dpm_profile.user_od = true;
2730 }
2731 break;
2732
2733 default:
2734 return -ENOSYS;
2735 }
2736
2737 return ret;
2738 }
2739
smu_v14_0_2_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2740 static int smu_v14_0_2_set_power_limit(struct smu_context *smu,
2741 enum smu_ppt_limit_type limit_type,
2742 uint32_t limit)
2743 {
2744 PPTable_t *pptable = smu->smu_table.driver_pptable;
2745 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2746 struct smu_table_context *table_context = &smu->smu_table;
2747 OverDriveTableExternal_t *od_table =
2748 (OverDriveTableExternal_t *)table_context->overdrive_table;
2749 int ret = 0;
2750
2751 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2752 return -EINVAL;
2753
2754 if (limit <= msg_limit) {
2755 if (smu->current_power_limit > msg_limit) {
2756 od_table->OverDriveTable.Ppt = 0;
2757 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2758
2759 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2760 if (ret) {
2761 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2762 return ret;
2763 }
2764 }
2765 return smu_v14_0_set_power_limit(smu, limit_type, limit);
2766 } else if (smu->od_enabled) {
2767 ret = smu_v14_0_set_power_limit(smu, limit_type, msg_limit);
2768 if (ret)
2769 return ret;
2770
2771 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2772 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2773
2774 ret = smu_v14_0_2_upload_overdrive_table(smu, od_table);
2775 if (ret) {
2776 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2777 return ret;
2778 }
2779
2780 smu->current_power_limit = limit;
2781 } else {
2782 return -EINVAL;
2783 }
2784
2785 return 0;
2786 }
2787
2788 static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
2789 .init_allowed_features = smu_v14_0_2_init_allowed_features,
2790 .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
2791 .i2c_init = smu_v14_0_2_i2c_control_init,
2792 .i2c_fini = smu_v14_0_2_i2c_control_fini,
2793 .is_dpm_running = smu_v14_0_2_is_dpm_running,
2794 .init_microcode = smu_v14_0_init_microcode,
2795 .load_microcode = smu_v14_0_load_microcode,
2796 .fini_microcode = smu_v14_0_fini_microcode,
2797 .init_smc_tables = smu_v14_0_2_init_smc_tables,
2798 .fini_smc_tables = smu_v14_0_fini_smc_tables,
2799 .init_power = smu_v14_0_init_power,
2800 .fini_power = smu_v14_0_fini_power,
2801 .check_fw_status = smu_v14_0_check_fw_status,
2802 .setup_pptable = smu_v14_0_2_setup_pptable,
2803 .check_fw_version = smu_cmn_check_fw_version,
2804 .set_driver_table_location = smu_v14_0_set_driver_table_location,
2805 .system_features_control = smu_v14_0_system_features_control,
2806 .set_allowed_mask = smu_v14_0_set_allowed_mask,
2807 .get_enabled_mask = smu_cmn_get_enabled_mask,
2808 .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable,
2809 .dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable,
2810 .get_dpm_ultimate_freq = smu_v14_0_2_get_dpm_ultimate_freq,
2811 .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values,
2812 .read_sensor = smu_v14_0_2_read_sensor,
2813 .feature_is_enabled = smu_cmn_feature_is_enabled,
2814 .emit_clk_levels = smu_v14_0_2_emit_clk_levels,
2815 .force_clk_levels = smu_v14_0_2_force_clk_levels,
2816 .update_pcie_parameters = smu_v14_0_2_update_pcie_parameters,
2817 .get_thermal_temperature_range = smu_v14_0_2_get_thermal_temperature_range,
2818 .register_irq_handler = smu_v14_0_register_irq_handler,
2819 .enable_thermal_alert = smu_v14_0_enable_thermal_alert,
2820 .disable_thermal_alert = smu_v14_0_disable_thermal_alert,
2821 .notify_memory_pool_location = smu_v14_0_notify_memory_pool_location,
2822 .get_gpu_metrics = smu_v14_0_2_get_gpu_metrics,
2823 .set_soft_freq_limited_range = smu_v14_0_set_soft_freq_limited_range,
2824 .set_default_od_settings = smu_v14_0_2_set_default_od_settings,
2825 .restore_user_od_settings = smu_v14_0_2_restore_user_od_settings,
2826 .od_edit_dpm_table = smu_v14_0_2_od_edit_dpm_table,
2827 .init_pptable_microcode = smu_v14_0_init_pptable_microcode,
2828 .populate_umd_state_clk = smu_v14_0_2_populate_umd_state_clk,
2829 .set_performance_level = smu_v14_0_set_performance_level,
2830 .gfx_off_control = smu_v14_0_gfx_off_control,
2831 .get_unique_id = smu_v14_0_2_get_unique_id,
2832 .get_fan_speed_pwm = smu_v14_0_2_get_fan_speed_pwm,
2833 .get_fan_speed_rpm = smu_v14_0_2_get_fan_speed_rpm,
2834 .get_power_limit = smu_v14_0_2_get_power_limit,
2835 .set_power_limit = smu_v14_0_2_set_power_limit,
2836 .get_power_profile_mode = smu_v14_0_2_get_power_profile_mode,
2837 .set_power_profile_mode = smu_v14_0_2_set_power_profile_mode,
2838 .run_btc = smu_v14_0_run_btc,
2839 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2840 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2841 .set_tool_table_location = smu_v14_0_set_tool_table_location,
2842 .deep_sleep_control = smu_v14_0_deep_sleep_control,
2843 .gfx_ulv_control = smu_v14_0_gfx_ulv_control,
2844 .get_bamaco_support = smu_v14_0_get_bamaco_support,
2845 .baco_get_state = smu_v14_0_baco_get_state,
2846 .baco_set_state = smu_v14_0_baco_set_state,
2847 .baco_enter = smu_v14_0_2_baco_enter,
2848 .baco_exit = smu_v14_0_2_baco_exit,
2849 .mode1_reset_is_support = smu_v14_0_2_is_mode1_reset_supported,
2850 .mode1_reset = smu_v14_0_2_mode1_reset,
2851 .mode2_reset = smu_v14_0_2_mode2_reset,
2852 .enable_gfx_features = smu_v14_0_2_enable_gfx_features,
2853 .set_mp1_state = smu_v14_0_2_set_mp1_state,
2854 .set_df_cstate = smu_v14_0_2_set_df_cstate,
2855 #if 0
2856 .gpo_control = smu_v14_0_gpo_control,
2857 #endif
2858 };
2859
smu_v14_0_2_set_ppt_funcs(struct smu_context * smu)2860 void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
2861 {
2862 smu->ppt_funcs = &smu_v14_0_2_ppt_funcs;
2863 smu->clock_map = smu_v14_0_2_clk_map;
2864 smu->feature_map = smu_v14_0_2_feature_mask_map;
2865 smu->table_map = smu_v14_0_2_table_map;
2866 smu->pwr_src_map = smu_v14_0_2_pwr_src_map;
2867 smu->workload_map = smu_v14_0_2_workload_map;
2868 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
2869 smu_v14_0_2_init_msg_ctl(smu);
2870 }
2871