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Searched refs:ARRAY_2D_TILED_THIN1 (Results 1 – 25 of 36) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c423 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
431 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
439 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
447 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
458 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
466 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
474 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
486 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
494 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
502 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
[all...]
H A Dgfx_v8_0.c2078 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2082 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2086 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2090 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2094 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2112 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2124 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2172 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2250 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2254 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
[all...]
H A Dgfx_v7_0.c1025 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1029 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1033 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1037 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1041 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1058 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1070 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1118 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1192 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1196 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
[all...]
H A Ddce_v10_0.c1986 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1997 ARRAY_2D_TILED_THIN1); in dce_v10_0_crtc_do_set_base()
/linux/drivers/gpu/drm/radeon/
H A Dsi.c2496 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2505 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2514 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2523 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2541 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2550 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2559 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2586 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2595 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2604 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
[all...]
H A Devergreen_cs.c97 return ARRAY_2D_TILED_THIN1; in evergreen_cs_get_aray_mode()
312 case ARRAY_2D_TILED_THIN1: in evergreen_surface_check()
327 case ARRAY_2D_TILED_THIN1: in evergreen_surface_value_conv_check()
884 case ARRAY_2D_TILED_THIN1: in evergreen_cs_track_validate_texture()
H A Dsid.h1184 # define ARRAY_2D_TILED_THIN1 4 macro
H A Dcikd.h1222 # define ARRAY_2D_TILED_THIN1 4 macro
/linux/sound/soc/amd/include/
H A Dacp_2_2_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Dsmu_7_1_0_enum.h81 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Dsmu_7_1_2_enum.h88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Dsmu_7_1_3_enum.h85 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Dsmu_7_1_1_enum.h88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Dbif_5_0_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Dgmc_8_1_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Ddce_10_0_enum.h613 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_enum.h541 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Duvd_5_0_enum.h51 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_enum.h223 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Doss_3_0_1_enum.h924 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
H A Doss_3_0_enum.h337 ARRAY_2D_TILED_THIN1 = 0x4, enumerator

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