Searched refs:AR71XX_RESET_REG_MISC_INT_ENABLE (Results 1 – 3 of 3) sorted by relevance
21 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 macro 44 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler() 68 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 69 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 72 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask() 81 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 82 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 85 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask() 127 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_intc_domain_init()
532 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); in qca956x_clocks_init() 534 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); in qca956x_clocks_init()
517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro