Searched refs:APLL (Results 1 – 10 of 10) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | apll.txt | 1 Binding for Texas Instruments APLL clock.
4 register-mapped APLL with usually two selectable input clocks
8 modes (locked, low power stop etc.) APLL mostly behaves like
18 - reg : address and length of the register set for controlling the APLL.
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| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | xlnx-zynqmp-clk.h | 14 #define APLL 2 macro
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| /linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 236 case APLL: in ma35d1_clk_pll_recalc_rate()
271 case APLL: in ma35d1_clk_pll_determine_rate()
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| H A D | clk-ma35d1.c | 506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
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| /linux/arch/arm64/boot/dts/nuvoton/ |
| H A D | ma35d1-iot-512m.dts | 43 <&clk APLL>,
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| H A D | ma35d1-som-256m.dts | 43 <&clk APLL>,
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| /linux/include/dt-bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.h | 22 #define APLL 11 macro
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| /linux/sound/soc/mediatek/mt8189/ |
| H A D | mt8189-dai-pcm.c | 87 APLL, enumerator
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| /linux/drivers/clk/ingenic/ |
| H A D | jz4780-cgu.c | 295 .pll = DEF_PLL(APLL),
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3036.dtsi | 239 * Fix the emac parent clock is DPLL instead of APLL.
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