1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * adv7180.c Analog Devices ADV7180 video decoder driver
4 * Copyright (c) 2009 Intel Corporation
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 */
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/of.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-ioctl.h>
20 #include <media/v4l2-event.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ctrls.h>
23 #include <linux/mutex.h>
24 #include <linux/delay.h>
25
26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
27 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
28 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
29 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
30 #define ADV7180_STD_NTSC_J 0x4
31 #define ADV7180_STD_NTSC_M 0x5
32 #define ADV7180_STD_PAL60 0x6
33 #define ADV7180_STD_NTSC_443 0x7
34 #define ADV7180_STD_PAL_BG 0x8
35 #define ADV7180_STD_PAL_N 0x9
36 #define ADV7180_STD_PAL_M 0xa
37 #define ADV7180_STD_PAL_M_PED 0xb
38 #define ADV7180_STD_PAL_COMB_N 0xc
39 #define ADV7180_STD_PAL_COMB_N_PED 0xd
40 #define ADV7180_STD_PAL_SECAM 0xe
41 #define ADV7180_STD_PAL_SECAM_PED 0xf
42
43 #define ADV7180_REG_INPUT_CONTROL 0x0000
44 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
45
46 #define ADV7182_REG_INPUT_VIDSEL 0x0002
47 #define ADV7182_REG_INPUT_RESERVED BIT(2)
48
49 #define ADV7180_REG_OUTPUT_CONTROL 0x0003
50 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
51 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
52
53 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
54 #define ADV7180_AUTODETECT_DEFAULT 0x7f
55 /* Contrast */
56 #define ADV7180_REG_CON 0x0008 /*Unsigned */
57 #define ADV7180_CON_MIN 0
58 #define ADV7180_CON_DEF 128
59 #define ADV7180_CON_MAX 255
60 /* Brightness*/
61 #define ADV7180_REG_BRI 0x000a /*Signed */
62 #define ADV7180_BRI_MIN -128
63 #define ADV7180_BRI_DEF 0
64 #define ADV7180_BRI_MAX 127
65 /* Hue */
66 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
67 #define ADV7180_HUE_MIN -127
68 #define ADV7180_HUE_DEF 0
69 #define ADV7180_HUE_MAX 128
70
71 #define ADV7180_REG_DEF_VALUE_Y 0x000c
72 #define ADV7180_DEF_VAL_EN 0x1
73 #define ADV7180_DEF_VAL_AUTO_EN 0x2
74 #define ADV7180_REG_CTRL 0x000e
75 #define ADV7180_CTRL_IRQ_SPACE 0x20
76
77 #define ADV7180_REG_PWR_MAN 0x0f
78 #define ADV7180_PWR_MAN_ON 0x04
79 #define ADV7180_PWR_MAN_OFF 0x24
80 #define ADV7180_PWR_MAN_RES 0x80
81
82 #define ADV7180_REG_STATUS1 0x0010
83 #define ADV7180_STATUS1_IN_LOCK 0x01
84 #define ADV7180_STATUS1_AUTOD_MASK 0x70
85 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
86 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
87 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
88 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
89 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
90 #define ADV7180_STATUS1_AUTOD_SECAM 0x50
91 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
92 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
93
94 #define ADV7180_REG_IDENT 0x0011
95 #define ADV7180_ID_7180 0x18
96
97 #define ADV7180_REG_STATUS3 0x0013
98 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
99 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
100 #define ADV7180_REG_CTRL_2 0x001d
101 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
102 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
103 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
104 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
105 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
106 #define ADV7180_REG_LOCK_CNT 0x0051
107 #define ADV7180_REG_CVBS_TRIM 0x0052
108 #define ADV7180_REG_CLAMP_ADJ 0x005a
109 #define ADV7180_REG_RES_CIR 0x005f
110 #define ADV7180_REG_DIFF_MODE 0x0060
111
112 #define ADV7180_REG_ICONF1 0x2040
113 #define ADV7180_ICONF1_ACTIVE_LOW 0x01
114 #define ADV7180_ICONF1_PSYNC_ONLY 0x10
115 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
116 /* Saturation */
117 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
118 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
119 #define ADV7180_SAT_MIN 0
120 #define ADV7180_SAT_DEF 128
121 #define ADV7180_SAT_MAX 255
122
123 #define ADV7180_IRQ1_LOCK 0x01
124 #define ADV7180_IRQ1_UNLOCK 0x02
125 #define ADV7180_REG_ISR1 0x2042
126 #define ADV7180_REG_ICR1 0x2043
127 #define ADV7180_REG_IMR1 0x2044
128 #define ADV7180_REG_IMR2 0x2048
129 #define ADV7180_IRQ3_AD_CHANGE 0x08
130 #define ADV7180_REG_ISR3 0x204A
131 #define ADV7180_REG_ICR3 0x204B
132 #define ADV7180_REG_IMR3 0x204C
133 #define ADV7180_REG_IMR4 0x2050
134
135 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
136 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
137
138 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
139 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
140
141 #define ADV7180_REG_ACE_CTRL1 0x4080
142 #define ADV7180_REG_ACE_CTRL5 0x4084
143 #define ADV7180_REG_FLCONTROL 0x40e0
144 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
145
146 #define ADV7180_REG_RST_CLAMP 0x809c
147 #define ADV7180_REG_AGC_ADJ1 0x80b6
148 #define ADV7180_REG_AGC_ADJ2 0x80c0
149
150 #define ADV7180_CSI_REG_PWRDN 0x00
151 #define ADV7180_CSI_PWRDN 0x80
152
153 #define ADV7180_INPUT_CVBS_AIN1 0x00
154 #define ADV7180_INPUT_CVBS_AIN2 0x01
155 #define ADV7180_INPUT_CVBS_AIN3 0x02
156 #define ADV7180_INPUT_CVBS_AIN4 0x03
157 #define ADV7180_INPUT_CVBS_AIN5 0x04
158 #define ADV7180_INPUT_CVBS_AIN6 0x05
159 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
160 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
161 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
162 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
163 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
164
165 #define ADV7182_INPUT_CVBS_AIN1 0x00
166 #define ADV7182_INPUT_CVBS_AIN2 0x01
167 #define ADV7182_INPUT_CVBS_AIN3 0x02
168 #define ADV7182_INPUT_CVBS_AIN4 0x03
169 #define ADV7182_INPUT_CVBS_AIN5 0x04
170 #define ADV7182_INPUT_CVBS_AIN6 0x05
171 #define ADV7182_INPUT_CVBS_AIN7 0x06
172 #define ADV7182_INPUT_CVBS_AIN8 0x07
173 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
174 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
175 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
176 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
177 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
178 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
179 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
180 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
181 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
182 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
183
184 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
185 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
186
187 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
188
189 /* Initial number of frames to skip to avoid possible garbage */
190 #define ADV7180_NUM_OF_SKIP_FRAMES 2
191
192 struct adv7180_state;
193
194 #define ADV7180_FLAG_RESET_POWERED BIT(0)
195 #define ADV7180_FLAG_V2 BIT(1)
196 #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
197 #define ADV7180_FLAG_I2P BIT(3)
198 #define ADV7180_FLAG_TEST_PATTERN BIT(4)
199
200 struct adv7180_chip_info {
201 unsigned int flags;
202 unsigned int valid_input_mask;
203 int (*set_std)(struct adv7180_state *st, unsigned int std);
204 int (*select_input)(struct adv7180_state *st, unsigned int input);
205 int (*init)(struct adv7180_state *state);
206 };
207
208 struct adv7180_state {
209 struct v4l2_ctrl_handler ctrl_hdl;
210 struct v4l2_subdev sd;
211 struct media_pad pad;
212 struct mutex mutex; /* mutual excl. when accessing chip */
213 int irq;
214 struct gpio_desc *pwdn_gpio;
215 struct gpio_desc *rst_gpio;
216 v4l2_std_id curr_norm;
217 bool powered;
218 bool streaming;
219 u8 input;
220
221 struct i2c_client *client;
222 unsigned int register_page;
223 struct i2c_client *csi_client;
224 struct i2c_client *vpp_client;
225 const struct adv7180_chip_info *chip_info;
226 enum v4l2_field field;
227 bool force_bt656_4;
228 };
229 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
230 struct adv7180_state, \
231 ctrl_hdl)->sd)
232
adv7180_select_page(struct adv7180_state * state,unsigned int page)233 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
234 {
235 if (state->register_page != page) {
236 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
237 page);
238 state->register_page = page;
239 }
240
241 return 0;
242 }
243
adv7180_write(struct adv7180_state * state,unsigned int reg,unsigned int value)244 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
245 unsigned int value)
246 {
247 lockdep_assert_held(&state->mutex);
248 adv7180_select_page(state, reg >> 8);
249 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
250 }
251
adv7180_read(struct adv7180_state * state,unsigned int reg)252 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
253 {
254 lockdep_assert_held(&state->mutex);
255 adv7180_select_page(state, reg >> 8);
256 return i2c_smbus_read_byte_data(state->client, reg & 0xff);
257 }
258
adv7180_csi_write(struct adv7180_state * state,unsigned int reg,unsigned int value)259 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
260 unsigned int value)
261 {
262 return i2c_smbus_write_byte_data(state->csi_client, reg, value);
263 }
264
adv7180_set_video_standard(struct adv7180_state * state,unsigned int std)265 static int adv7180_set_video_standard(struct adv7180_state *state,
266 unsigned int std)
267 {
268 return state->chip_info->set_std(state, std);
269 }
270
adv7180_vpp_write(struct adv7180_state * state,unsigned int reg,unsigned int value)271 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
272 unsigned int value)
273 {
274 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
275 }
276
adv7180_std_to_v4l2(u8 status1)277 static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
278 {
279 /* in case V4L2_IN_ST_NO_SIGNAL */
280 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
281 return V4L2_STD_UNKNOWN;
282
283 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
284 case ADV7180_STATUS1_AUTOD_NTSM_M_J:
285 return V4L2_STD_NTSC;
286 case ADV7180_STATUS1_AUTOD_NTSC_4_43:
287 return V4L2_STD_NTSC_443;
288 case ADV7180_STATUS1_AUTOD_PAL_M:
289 return V4L2_STD_PAL_M;
290 case ADV7180_STATUS1_AUTOD_PAL_60:
291 return V4L2_STD_PAL_60;
292 case ADV7180_STATUS1_AUTOD_PAL_B_G:
293 return V4L2_STD_PAL;
294 case ADV7180_STATUS1_AUTOD_SECAM:
295 return V4L2_STD_SECAM;
296 case ADV7180_STATUS1_AUTOD_PAL_COMB:
297 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
298 case ADV7180_STATUS1_AUTOD_SECAM_525:
299 return V4L2_STD_SECAM;
300 default:
301 return V4L2_STD_UNKNOWN;
302 }
303 }
304
v4l2_std_to_adv7180(v4l2_std_id std)305 static int v4l2_std_to_adv7180(v4l2_std_id std)
306 {
307 if (std == V4L2_STD_PAL_60)
308 return ADV7180_STD_PAL60;
309 if (std == V4L2_STD_NTSC_443)
310 return ADV7180_STD_NTSC_443;
311 if (std == V4L2_STD_PAL_N)
312 return ADV7180_STD_PAL_N;
313 if (std == V4L2_STD_PAL_M)
314 return ADV7180_STD_PAL_M;
315 if (std == V4L2_STD_PAL_Nc)
316 return ADV7180_STD_PAL_COMB_N;
317
318 if (std & V4L2_STD_PAL)
319 return ADV7180_STD_PAL_BG;
320 if (std & V4L2_STD_NTSC)
321 return ADV7180_STD_NTSC_M;
322 if (std & V4L2_STD_SECAM)
323 return ADV7180_STD_PAL_SECAM;
324
325 return -EINVAL;
326 }
327
adv7180_status_to_v4l2(u8 status1)328 static u32 adv7180_status_to_v4l2(u8 status1)
329 {
330 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
331 return V4L2_IN_ST_NO_SIGNAL;
332
333 return 0;
334 }
335
__adv7180_status(struct adv7180_state * state,u32 * status,v4l2_std_id * std)336 static int __adv7180_status(struct adv7180_state *state, u32 *status,
337 v4l2_std_id *std)
338 {
339 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
340
341 if (status1 < 0)
342 return status1;
343
344 if (status)
345 *status = adv7180_status_to_v4l2(status1);
346 if (std)
347 *std = adv7180_std_to_v4l2(status1);
348
349 return 0;
350 }
351
to_state(struct v4l2_subdev * sd)352 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
353 {
354 return container_of(sd, struct adv7180_state, sd);
355 }
356
adv7180_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)357 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
358 {
359 struct adv7180_state *state = to_state(sd);
360 int err = mutex_lock_interruptible(&state->mutex);
361 if (err)
362 return err;
363
364 if (state->streaming) {
365 err = -EBUSY;
366 goto unlock;
367 }
368
369 err = adv7180_set_video_standard(state,
370 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
371 if (err)
372 goto unlock;
373
374 msleep(100);
375 __adv7180_status(state, NULL, std);
376
377 err = v4l2_std_to_adv7180(state->curr_norm);
378 if (err < 0)
379 goto unlock;
380
381 err = adv7180_set_video_standard(state, err);
382
383 unlock:
384 mutex_unlock(&state->mutex);
385 return err;
386 }
387
adv7180_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)388 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
389 u32 output, u32 config)
390 {
391 struct adv7180_state *state = to_state(sd);
392 int ret = mutex_lock_interruptible(&state->mutex);
393
394 if (ret)
395 return ret;
396
397 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
398 ret = -EINVAL;
399 goto out;
400 }
401
402 ret = state->chip_info->select_input(state, input);
403
404 if (ret == 0)
405 state->input = input;
406 out:
407 mutex_unlock(&state->mutex);
408 return ret;
409 }
410
adv7180_g_input_status(struct v4l2_subdev * sd,u32 * status)411 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
412 {
413 struct adv7180_state *state = to_state(sd);
414 int ret = mutex_lock_interruptible(&state->mutex);
415 if (ret)
416 return ret;
417
418 ret = __adv7180_status(state, status, NULL);
419 mutex_unlock(&state->mutex);
420 return ret;
421 }
422
adv7180_program_std(struct adv7180_state * state)423 static int adv7180_program_std(struct adv7180_state *state)
424 {
425 int ret;
426
427 ret = v4l2_std_to_adv7180(state->curr_norm);
428 if (ret < 0)
429 return ret;
430
431 ret = adv7180_set_video_standard(state, ret);
432 if (ret < 0)
433 return ret;
434 return 0;
435 }
436
adv7180_s_std(struct v4l2_subdev * sd,v4l2_std_id std)437 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
438 {
439 struct adv7180_state *state = to_state(sd);
440 int ret = mutex_lock_interruptible(&state->mutex);
441
442 if (ret)
443 return ret;
444
445 /* Make sure we can support this std */
446 ret = v4l2_std_to_adv7180(std);
447 if (ret < 0)
448 goto out;
449
450 state->curr_norm = std;
451
452 ret = adv7180_program_std(state);
453 out:
454 mutex_unlock(&state->mutex);
455 return ret;
456 }
457
adv7180_g_std(struct v4l2_subdev * sd,v4l2_std_id * norm)458 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
459 {
460 struct adv7180_state *state = to_state(sd);
461
462 *norm = state->curr_norm;
463
464 return 0;
465 }
466
adv7180_get_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)467 static int adv7180_get_frame_interval(struct v4l2_subdev *sd,
468 struct v4l2_subdev_state *sd_state,
469 struct v4l2_subdev_frame_interval *fi)
470 {
471 struct adv7180_state *state = to_state(sd);
472
473 /*
474 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
475 * subdev active state API.
476 */
477 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
478 return -EINVAL;
479
480 if (state->curr_norm & V4L2_STD_525_60) {
481 fi->interval.numerator = 1001;
482 fi->interval.denominator = 30000;
483 } else {
484 fi->interval.numerator = 1;
485 fi->interval.denominator = 25;
486 }
487
488 return 0;
489 }
490
adv7180_set_power_pin(struct adv7180_state * state,bool on)491 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
492 {
493 if (!state->pwdn_gpio)
494 return;
495
496 if (on) {
497 gpiod_set_value_cansleep(state->pwdn_gpio, 0);
498 usleep_range(5000, 10000);
499 } else {
500 gpiod_set_value_cansleep(state->pwdn_gpio, 1);
501 }
502 }
503
adv7180_set_reset_pin(struct adv7180_state * state,bool on)504 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
505 {
506 if (!state->rst_gpio)
507 return;
508
509 if (on) {
510 gpiod_set_value_cansleep(state->rst_gpio, 1);
511 } else {
512 gpiod_set_value_cansleep(state->rst_gpio, 0);
513 usleep_range(5000, 10000);
514 }
515 }
516
adv7180_set_power(struct adv7180_state * state,bool on)517 static int adv7180_set_power(struct adv7180_state *state, bool on)
518 {
519 u8 val;
520 int ret;
521
522 if (on)
523 val = ADV7180_PWR_MAN_ON;
524 else
525 val = ADV7180_PWR_MAN_OFF;
526
527 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
528 if (ret)
529 return ret;
530
531 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
532 if (on) {
533 adv7180_csi_write(state, 0xDE, 0x02);
534 adv7180_csi_write(state, 0xD2, 0xF7);
535 adv7180_csi_write(state, 0xD8, 0x65);
536 adv7180_csi_write(state, 0xE0, 0x09);
537 adv7180_csi_write(state, 0x2C, 0x00);
538 if (state->field == V4L2_FIELD_NONE)
539 adv7180_csi_write(state, 0x1D, 0x80);
540 adv7180_csi_write(state, 0x00, 0x00);
541 } else {
542 adv7180_csi_write(state, 0x00, 0x80);
543 }
544 }
545
546 return 0;
547 }
548
adv7180_s_power(struct v4l2_subdev * sd,int on)549 static int adv7180_s_power(struct v4l2_subdev *sd, int on)
550 {
551 struct adv7180_state *state = to_state(sd);
552 int ret;
553
554 ret = mutex_lock_interruptible(&state->mutex);
555 if (ret)
556 return ret;
557
558 ret = adv7180_set_power(state, on);
559 if (ret == 0)
560 state->powered = on;
561
562 mutex_unlock(&state->mutex);
563 return ret;
564 }
565
566 static const char * const test_pattern_menu[] = {
567 "Single color",
568 "Color bars",
569 "Luma ramp",
570 "Boundary box",
571 "Disable",
572 };
573
adv7180_test_pattern(struct adv7180_state * state,int value)574 static int adv7180_test_pattern(struct adv7180_state *state, int value)
575 {
576 unsigned int reg = 0;
577
578 /* Map menu value into register value */
579 if (value < 3)
580 reg = value;
581 if (value == 3)
582 reg = 5;
583
584 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
585
586 if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
587 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
588 reg &= ~ADV7180_DEF_VAL_EN;
589 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
590 return 0;
591 }
592
593 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
594 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
595 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
596
597 return 0;
598 }
599
adv7180_s_ctrl(struct v4l2_ctrl * ctrl)600 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
601 {
602 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
603 struct adv7180_state *state = to_state(sd);
604 int ret = mutex_lock_interruptible(&state->mutex);
605 int val;
606
607 if (ret)
608 return ret;
609 val = ctrl->val;
610 switch (ctrl->id) {
611 case V4L2_CID_BRIGHTNESS:
612 ret = adv7180_write(state, ADV7180_REG_BRI, val);
613 break;
614 case V4L2_CID_HUE:
615 /*Hue is inverted according to HSL chart */
616 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
617 break;
618 case V4L2_CID_CONTRAST:
619 ret = adv7180_write(state, ADV7180_REG_CON, val);
620 break;
621 case V4L2_CID_SATURATION:
622 /*
623 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
624 *Let's not confuse the user, everybody understands saturation
625 */
626 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
627 if (ret < 0)
628 break;
629 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
630 break;
631 case V4L2_CID_ADV_FAST_SWITCH:
632 if (ctrl->val) {
633 /* ADI required write */
634 adv7180_write(state, 0x80d9, 0x44);
635 adv7180_write(state, ADV7180_REG_FLCONTROL,
636 ADV7180_FLCONTROL_FL_ENABLE);
637 } else {
638 /* ADI required write */
639 adv7180_write(state, 0x80d9, 0xc4);
640 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
641 }
642 break;
643 case V4L2_CID_TEST_PATTERN:
644 ret = adv7180_test_pattern(state, val);
645 break;
646 default:
647 ret = -EINVAL;
648 }
649
650 mutex_unlock(&state->mutex);
651 return ret;
652 }
653
654 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
655 .s_ctrl = adv7180_s_ctrl,
656 };
657
658 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
659 .ops = &adv7180_ctrl_ops,
660 .id = V4L2_CID_ADV_FAST_SWITCH,
661 .name = "Fast Switching",
662 .type = V4L2_CTRL_TYPE_BOOLEAN,
663 .min = 0,
664 .max = 1,
665 .step = 1,
666 };
667
adv7180_init_controls(struct adv7180_state * state)668 static int adv7180_init_controls(struct adv7180_state *state)
669 {
670 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
671
672 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
673 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
674 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
675 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
676 V4L2_CID_CONTRAST, ADV7180_CON_MIN,
677 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
678 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
679 V4L2_CID_SATURATION, ADV7180_SAT_MIN,
680 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
681 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
682 V4L2_CID_HUE, ADV7180_HUE_MIN,
683 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
684 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
685
686 if (state->chip_info->flags & ADV7180_FLAG_TEST_PATTERN) {
687 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl,
688 &adv7180_ctrl_ops,
689 V4L2_CID_TEST_PATTERN,
690 ARRAY_SIZE(test_pattern_menu) - 1,
691 0,
692 ARRAY_SIZE(test_pattern_menu) - 1,
693 test_pattern_menu);
694 }
695
696 state->sd.ctrl_handler = &state->ctrl_hdl;
697 if (state->ctrl_hdl.error) {
698 int err = state->ctrl_hdl.error;
699
700 v4l2_ctrl_handler_free(&state->ctrl_hdl);
701 return err;
702 }
703 v4l2_ctrl_handler_setup(&state->ctrl_hdl);
704
705 return 0;
706 }
adv7180_exit_controls(struct adv7180_state * state)707 static void adv7180_exit_controls(struct adv7180_state *state)
708 {
709 v4l2_ctrl_handler_free(&state->ctrl_hdl);
710 }
711
adv7180_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)712 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
713 struct v4l2_subdev_state *sd_state,
714 struct v4l2_subdev_mbus_code_enum *code)
715 {
716 if (code->index != 0)
717 return -EINVAL;
718
719 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
720
721 return 0;
722 }
723
adv7180_mbus_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt)724 static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
725 struct v4l2_mbus_framefmt *fmt)
726 {
727 struct adv7180_state *state = to_state(sd);
728
729 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
730 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
731 fmt->width = 720;
732 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
733
734 if (state->field == V4L2_FIELD_ALTERNATE)
735 fmt->height /= 2;
736
737 return 0;
738 }
739
adv7180_set_field_mode(struct adv7180_state * state)740 static int adv7180_set_field_mode(struct adv7180_state *state)
741 {
742 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
743 return 0;
744
745 if (state->field == V4L2_FIELD_NONE) {
746 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
747 adv7180_csi_write(state, 0x01, 0x20);
748 adv7180_csi_write(state, 0x02, 0x28);
749 adv7180_csi_write(state, 0x03, 0x38);
750 adv7180_csi_write(state, 0x04, 0x30);
751 adv7180_csi_write(state, 0x05, 0x30);
752 adv7180_csi_write(state, 0x06, 0x80);
753 adv7180_csi_write(state, 0x07, 0x70);
754 adv7180_csi_write(state, 0x08, 0x50);
755 }
756 adv7180_vpp_write(state, 0xa3, 0x00);
757 adv7180_vpp_write(state, 0x5b, 0x00);
758 adv7180_vpp_write(state, 0x55, 0x80);
759 } else {
760 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
761 adv7180_csi_write(state, 0x01, 0x18);
762 adv7180_csi_write(state, 0x02, 0x18);
763 adv7180_csi_write(state, 0x03, 0x30);
764 adv7180_csi_write(state, 0x04, 0x20);
765 adv7180_csi_write(state, 0x05, 0x28);
766 adv7180_csi_write(state, 0x06, 0x40);
767 adv7180_csi_write(state, 0x07, 0x58);
768 adv7180_csi_write(state, 0x08, 0x30);
769 }
770 adv7180_vpp_write(state, 0xa3, 0x70);
771 adv7180_vpp_write(state, 0x5b, 0x80);
772 adv7180_vpp_write(state, 0x55, 0x00);
773 }
774
775 return 0;
776 }
777
adv7180_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)778 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
779 struct v4l2_subdev_state *sd_state,
780 struct v4l2_subdev_format *format)
781 {
782 struct adv7180_state *state = to_state(sd);
783
784 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
785 format->format = *v4l2_subdev_state_get_format(sd_state, 0);
786 } else {
787 adv7180_mbus_fmt(sd, &format->format);
788 format->format.field = state->field;
789 }
790
791 return 0;
792 }
793
adv7180_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)794 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
795 struct v4l2_subdev_state *sd_state,
796 struct v4l2_subdev_format *format)
797 {
798 struct adv7180_state *state = to_state(sd);
799 struct v4l2_mbus_framefmt *framefmt;
800 int ret;
801
802 switch (format->format.field) {
803 case V4L2_FIELD_NONE:
804 if (state->chip_info->flags & ADV7180_FLAG_I2P)
805 break;
806 fallthrough;
807 default:
808 format->format.field = V4L2_FIELD_ALTERNATE;
809 break;
810 }
811
812 ret = adv7180_mbus_fmt(sd, &format->format);
813
814 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
815 if (state->field != format->format.field) {
816 state->field = format->format.field;
817 adv7180_set_power(state, false);
818 adv7180_set_field_mode(state);
819 adv7180_set_power(state, true);
820 }
821 } else {
822 framefmt = v4l2_subdev_state_get_format(sd_state, 0);
823 *framefmt = format->format;
824 }
825
826 return ret;
827 }
828
adv7180_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)829 static int adv7180_init_state(struct v4l2_subdev *sd,
830 struct v4l2_subdev_state *sd_state)
831 {
832 struct v4l2_subdev_format fmt = {
833 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
834 : V4L2_SUBDEV_FORMAT_ACTIVE,
835 };
836
837 return adv7180_set_pad_format(sd, sd_state, &fmt);
838 }
839
adv7180_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)840 static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
841 unsigned int pad,
842 struct v4l2_mbus_config *cfg)
843 {
844 struct adv7180_state *state = to_state(sd);
845
846 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
847 cfg->type = V4L2_MBUS_CSI2_DPHY;
848 cfg->bus.mipi_csi2.num_data_lanes = 1;
849 cfg->bus.mipi_csi2.flags = 0;
850 } else {
851 /*
852 * The ADV7180 sensor supports BT.601/656 output modes.
853 * The BT.656 is default and not yet configurable by s/w.
854 */
855 cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
856 V4L2_MBUS_PCLK_SAMPLE_RISING |
857 V4L2_MBUS_DATA_ACTIVE_HIGH;
858 cfg->type = V4L2_MBUS_BT656;
859 }
860
861 return 0;
862 }
863
adv7180_get_skip_frames(struct v4l2_subdev * sd,u32 * frames)864 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
865 {
866 *frames = ADV7180_NUM_OF_SKIP_FRAMES;
867
868 return 0;
869 }
870
adv7180_g_tvnorms(struct v4l2_subdev * sd,v4l2_std_id * norm)871 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
872 {
873 *norm = V4L2_STD_ALL;
874 return 0;
875 }
876
adv7180_s_stream(struct v4l2_subdev * sd,int enable)877 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
878 {
879 struct adv7180_state *state = to_state(sd);
880 int ret;
881
882 /* It's always safe to stop streaming, no need to take the lock */
883 if (!enable) {
884 state->streaming = enable;
885 return 0;
886 }
887
888 /* Must wait until querystd released the lock */
889 ret = mutex_lock_interruptible(&state->mutex);
890 if (ret)
891 return ret;
892 state->streaming = enable;
893 mutex_unlock(&state->mutex);
894 return 0;
895 }
896
adv7180_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)897 static int adv7180_subscribe_event(struct v4l2_subdev *sd,
898 struct v4l2_fh *fh,
899 struct v4l2_event_subscription *sub)
900 {
901 switch (sub->type) {
902 case V4L2_EVENT_SOURCE_CHANGE:
903 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
904 case V4L2_EVENT_CTRL:
905 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
906 default:
907 return -EINVAL;
908 }
909 }
910
911 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
912 .s_std = adv7180_s_std,
913 .g_std = adv7180_g_std,
914 .querystd = adv7180_querystd,
915 .g_input_status = adv7180_g_input_status,
916 .s_routing = adv7180_s_routing,
917 .g_tvnorms = adv7180_g_tvnorms,
918 .s_stream = adv7180_s_stream,
919 };
920
921 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
922 .s_power = adv7180_s_power,
923 .subscribe_event = adv7180_subscribe_event,
924 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
925 };
926
927 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
928 .enum_mbus_code = adv7180_enum_mbus_code,
929 .set_fmt = adv7180_set_pad_format,
930 .get_fmt = adv7180_get_pad_format,
931 .get_frame_interval = adv7180_get_frame_interval,
932 .get_mbus_config = adv7180_get_mbus_config,
933 };
934
935 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
936 .g_skip_frames = adv7180_get_skip_frames,
937 };
938
939 static const struct v4l2_subdev_ops adv7180_ops = {
940 .core = &adv7180_core_ops,
941 .video = &adv7180_video_ops,
942 .pad = &adv7180_pad_ops,
943 .sensor = &adv7180_sensor_ops,
944 };
945
946 static const struct v4l2_subdev_internal_ops adv7180_internal_ops = {
947 .init_state = adv7180_init_state,
948 };
949
adv7180_irq(int irq,void * devid)950 static irqreturn_t adv7180_irq(int irq, void *devid)
951 {
952 struct adv7180_state *state = devid;
953 u8 isr3;
954
955 mutex_lock(&state->mutex);
956 isr3 = adv7180_read(state, ADV7180_REG_ISR3);
957 /* clear */
958 adv7180_write(state, ADV7180_REG_ICR3, isr3);
959
960 if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
961 static const struct v4l2_event src_ch = {
962 .type = V4L2_EVENT_SOURCE_CHANGE,
963 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
964 };
965
966 v4l2_subdev_notify_event(&state->sd, &src_ch);
967 }
968 mutex_unlock(&state->mutex);
969
970 return IRQ_HANDLED;
971 }
972
adv7180_init(struct adv7180_state * state)973 static int adv7180_init(struct adv7180_state *state)
974 {
975 int ret;
976
977 /* ITU-R BT.656-4 compatible */
978 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
979 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
980 if (ret < 0)
981 return ret;
982
983 /* Manually set V bit end position in NTSC mode */
984 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
985 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
986 }
987
adv7180_set_std(struct adv7180_state * state,unsigned int std)988 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
989 {
990 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
991 (std << 4) | state->input);
992 }
993
adv7180_select_input(struct adv7180_state * state,unsigned int input)994 static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
995 {
996 int ret;
997
998 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
999 if (ret < 0)
1000 return ret;
1001
1002 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
1003 ret |= input;
1004 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1005 }
1006
adv7182_init(struct adv7180_state * state)1007 static int adv7182_init(struct adv7180_state *state)
1008 {
1009 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1010 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1011 ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
1012
1013 if (state->chip_info->flags & ADV7180_FLAG_I2P)
1014 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1015 ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
1016
1017 if (state->chip_info->flags & ADV7180_FLAG_V2) {
1018 /* ADI recommended writes for improved video quality */
1019 adv7180_write(state, 0x0080, 0x51);
1020 adv7180_write(state, 0x0081, 0x51);
1021 adv7180_write(state, 0x0082, 0x68);
1022 }
1023
1024 /* ADI required writes */
1025 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1026 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1027 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1028 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1029 } else {
1030 if (state->chip_info->flags & ADV7180_FLAG_V2) {
1031 if (state->force_bt656_4) {
1032 /* ITU-R BT.656-4 compatible */
1033 adv7180_write(state,
1034 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1035 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1036 /* Manually set NEWAVMODE */
1037 adv7180_write(state,
1038 ADV7180_REG_VSYNC_FIELD_CTL_1,
1039 ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
1040 /* Manually set V bit end position in NTSC mode */
1041 adv7180_write(state,
1042 ADV7180_REG_NTSC_V_BIT_END,
1043 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1044 } else {
1045 adv7180_write(state,
1046 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1047 0x17);
1048 }
1049 } else {
1050 adv7180_write(state,
1051 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1052 0x07);
1053 }
1054 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1055 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1056 }
1057
1058 adv7180_write(state, 0x0013, 0x00);
1059
1060 return 0;
1061 }
1062
adv7182_set_std(struct adv7180_state * state,unsigned int std)1063 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
1064 {
1065 /* Failing to set the reserved bit can result in increased video noise */
1066 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1067 (std << 4) | ADV7182_REG_INPUT_RESERVED);
1068 }
1069
1070 enum adv7182_input_type {
1071 ADV7182_INPUT_TYPE_CVBS,
1072 ADV7182_INPUT_TYPE_DIFF_CVBS,
1073 ADV7182_INPUT_TYPE_SVIDEO,
1074 ADV7182_INPUT_TYPE_YPBPR,
1075 };
1076
adv7182_get_input_type(unsigned int input)1077 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
1078 {
1079 switch (input) {
1080 case ADV7182_INPUT_CVBS_AIN1:
1081 case ADV7182_INPUT_CVBS_AIN2:
1082 case ADV7182_INPUT_CVBS_AIN3:
1083 case ADV7182_INPUT_CVBS_AIN4:
1084 case ADV7182_INPUT_CVBS_AIN5:
1085 case ADV7182_INPUT_CVBS_AIN6:
1086 case ADV7182_INPUT_CVBS_AIN7:
1087 case ADV7182_INPUT_CVBS_AIN8:
1088 return ADV7182_INPUT_TYPE_CVBS;
1089 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1090 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1091 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1092 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1093 return ADV7182_INPUT_TYPE_SVIDEO;
1094 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1095 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1096 return ADV7182_INPUT_TYPE_YPBPR;
1097 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1098 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1099 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1100 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1101 return ADV7182_INPUT_TYPE_DIFF_CVBS;
1102 default: /* Will never happen */
1103 return 0;
1104 }
1105 }
1106
1107 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1108 static unsigned int adv7182_lbias_settings[][3] = {
1109 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1110 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1111 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1112 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1113 };
1114
1115 static unsigned int adv7280_lbias_settings[][3] = {
1116 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1117 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1118 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1119 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1120 };
1121
adv7182_select_input(struct adv7180_state * state,unsigned int input)1122 static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1123 {
1124 enum adv7182_input_type input_type;
1125 unsigned int *lbias;
1126 unsigned int i;
1127 int ret;
1128
1129 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1130 if (ret)
1131 return ret;
1132
1133 /* Reset clamp circuitry - ADI recommended writes */
1134 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1135 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1136
1137 input_type = adv7182_get_input_type(input);
1138
1139 switch (input_type) {
1140 case ADV7182_INPUT_TYPE_CVBS:
1141 case ADV7182_INPUT_TYPE_DIFF_CVBS:
1142 /* ADI recommends to use the SH1 filter */
1143 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1144 break;
1145 default:
1146 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1147 break;
1148 }
1149
1150 if (state->chip_info->flags & ADV7180_FLAG_V2)
1151 lbias = adv7280_lbias_settings[input_type];
1152 else
1153 lbias = adv7182_lbias_settings[input_type];
1154
1155 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1156 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1157
1158 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1159 /* ADI required writes to make differential CVBS work */
1160 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1161 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1162 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1163 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1164 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1165 } else {
1166 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1167 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1168 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1169 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1170 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1171 }
1172
1173 return 0;
1174 }
1175
1176 static const struct adv7180_chip_info adv7180_info = {
1177 .flags = ADV7180_FLAG_RESET_POWERED,
1178 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1179 * all inputs and let the card driver take care of validation
1180 */
1181 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1182 BIT(ADV7180_INPUT_CVBS_AIN2) |
1183 BIT(ADV7180_INPUT_CVBS_AIN3) |
1184 BIT(ADV7180_INPUT_CVBS_AIN4) |
1185 BIT(ADV7180_INPUT_CVBS_AIN5) |
1186 BIT(ADV7180_INPUT_CVBS_AIN6) |
1187 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1188 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1189 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1190 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1191 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1192 .init = adv7180_init,
1193 .set_std = adv7180_set_std,
1194 .select_input = adv7180_select_input,
1195 };
1196
1197 static const struct adv7180_chip_info adv7182_info = {
1198 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1199 BIT(ADV7182_INPUT_CVBS_AIN2) |
1200 BIT(ADV7182_INPUT_CVBS_AIN3) |
1201 BIT(ADV7182_INPUT_CVBS_AIN4) |
1202 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1203 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1204 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1205 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1206 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1207 .init = adv7182_init,
1208 .set_std = adv7182_set_std,
1209 .select_input = adv7182_select_input,
1210 };
1211
1212 static const struct adv7180_chip_info adv7280_info = {
1213 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1214 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1215 BIT(ADV7182_INPUT_CVBS_AIN2) |
1216 BIT(ADV7182_INPUT_CVBS_AIN3) |
1217 BIT(ADV7182_INPUT_CVBS_AIN4) |
1218 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1219 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1220 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1221 .init = adv7182_init,
1222 .set_std = adv7182_set_std,
1223 .select_input = adv7182_select_input,
1224 };
1225
1226 static const struct adv7180_chip_info adv7280_m_info = {
1227 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1228 ADV7180_FLAG_TEST_PATTERN,
1229 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1230 BIT(ADV7182_INPUT_CVBS_AIN2) |
1231 BIT(ADV7182_INPUT_CVBS_AIN3) |
1232 BIT(ADV7182_INPUT_CVBS_AIN4) |
1233 BIT(ADV7182_INPUT_CVBS_AIN5) |
1234 BIT(ADV7182_INPUT_CVBS_AIN6) |
1235 BIT(ADV7182_INPUT_CVBS_AIN7) |
1236 BIT(ADV7182_INPUT_CVBS_AIN8) |
1237 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1238 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1239 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1240 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1241 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1242 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1243 .init = adv7182_init,
1244 .set_std = adv7182_set_std,
1245 .select_input = adv7182_select_input,
1246 };
1247
1248 static const struct adv7180_chip_info adv7281_info = {
1249 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1250 ADV7180_FLAG_TEST_PATTERN,
1251 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1252 BIT(ADV7182_INPUT_CVBS_AIN2) |
1253 BIT(ADV7182_INPUT_CVBS_AIN7) |
1254 BIT(ADV7182_INPUT_CVBS_AIN8) |
1255 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1256 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1257 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1258 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1259 .init = adv7182_init,
1260 .set_std = adv7182_set_std,
1261 .select_input = adv7182_select_input,
1262 };
1263
1264 static const struct adv7180_chip_info adv7281_m_info = {
1265 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1266 ADV7180_FLAG_TEST_PATTERN,
1267 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1268 BIT(ADV7182_INPUT_CVBS_AIN2) |
1269 BIT(ADV7182_INPUT_CVBS_AIN3) |
1270 BIT(ADV7182_INPUT_CVBS_AIN4) |
1271 BIT(ADV7182_INPUT_CVBS_AIN7) |
1272 BIT(ADV7182_INPUT_CVBS_AIN8) |
1273 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1274 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1275 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1276 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1277 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1278 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1279 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1280 .init = adv7182_init,
1281 .set_std = adv7182_set_std,
1282 .select_input = adv7182_select_input,
1283 };
1284
1285 static const struct adv7180_chip_info adv7281_ma_info = {
1286 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1287 ADV7180_FLAG_TEST_PATTERN,
1288 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1289 BIT(ADV7182_INPUT_CVBS_AIN2) |
1290 BIT(ADV7182_INPUT_CVBS_AIN3) |
1291 BIT(ADV7182_INPUT_CVBS_AIN4) |
1292 BIT(ADV7182_INPUT_CVBS_AIN5) |
1293 BIT(ADV7182_INPUT_CVBS_AIN6) |
1294 BIT(ADV7182_INPUT_CVBS_AIN7) |
1295 BIT(ADV7182_INPUT_CVBS_AIN8) |
1296 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1297 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1298 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1299 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1300 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1301 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1302 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1303 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1304 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1305 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1306 .init = adv7182_init,
1307 .set_std = adv7182_set_std,
1308 .select_input = adv7182_select_input,
1309 };
1310
1311 static const struct adv7180_chip_info adv7282_info = {
1312 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1313 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1314 BIT(ADV7182_INPUT_CVBS_AIN2) |
1315 BIT(ADV7182_INPUT_CVBS_AIN7) |
1316 BIT(ADV7182_INPUT_CVBS_AIN8) |
1317 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1318 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1319 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1320 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1321 .init = adv7182_init,
1322 .set_std = adv7182_set_std,
1323 .select_input = adv7182_select_input,
1324 };
1325
1326 static const struct adv7180_chip_info adv7282_m_info = {
1327 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1328 ADV7180_FLAG_TEST_PATTERN,
1329 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1330 BIT(ADV7182_INPUT_CVBS_AIN2) |
1331 BIT(ADV7182_INPUT_CVBS_AIN3) |
1332 BIT(ADV7182_INPUT_CVBS_AIN4) |
1333 BIT(ADV7182_INPUT_CVBS_AIN7) |
1334 BIT(ADV7182_INPUT_CVBS_AIN8) |
1335 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1336 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1337 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1338 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1339 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1340 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1341 .init = adv7182_init,
1342 .set_std = adv7182_set_std,
1343 .select_input = adv7182_select_input,
1344 };
1345
init_device(struct adv7180_state * state)1346 static int init_device(struct adv7180_state *state)
1347 {
1348 int ret;
1349
1350 mutex_lock(&state->mutex);
1351
1352 adv7180_set_power_pin(state, true);
1353 adv7180_set_reset_pin(state, false);
1354
1355 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1356 usleep_range(5000, 10000);
1357
1358 ret = state->chip_info->init(state);
1359 if (ret)
1360 goto out_unlock;
1361
1362 ret = adv7180_program_std(state);
1363 if (ret)
1364 goto out_unlock;
1365
1366 adv7180_set_field_mode(state);
1367
1368 /* register for interrupts */
1369 if (state->irq > 0) {
1370 /* config the Interrupt pin to be active low */
1371 ret = adv7180_write(state, ADV7180_REG_ICONF1,
1372 ADV7180_ICONF1_ACTIVE_LOW |
1373 ADV7180_ICONF1_PSYNC_ONLY);
1374 if (ret < 0)
1375 goto out_unlock;
1376
1377 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1378 if (ret < 0)
1379 goto out_unlock;
1380
1381 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1382 if (ret < 0)
1383 goto out_unlock;
1384
1385 /* enable AD change interrupts interrupts */
1386 ret = adv7180_write(state, ADV7180_REG_IMR3,
1387 ADV7180_IRQ3_AD_CHANGE);
1388 if (ret < 0)
1389 goto out_unlock;
1390
1391 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
1392 if (ret < 0)
1393 goto out_unlock;
1394 }
1395
1396 out_unlock:
1397 mutex_unlock(&state->mutex);
1398
1399 return ret;
1400 }
1401
adv7180_probe(struct i2c_client * client)1402 static int adv7180_probe(struct i2c_client *client)
1403 {
1404 struct device_node *np = client->dev.of_node;
1405 struct adv7180_state *state;
1406 struct v4l2_subdev *sd;
1407 int ret;
1408
1409 /* Check if the adapter supports the needed features */
1410 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1411 return -EIO;
1412
1413 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1414 if (state == NULL)
1415 return -ENOMEM;
1416
1417 state->client = client;
1418 state->field = V4L2_FIELD_ALTERNATE;
1419 state->chip_info = i2c_get_match_data(client);
1420
1421 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1422 GPIOD_OUT_HIGH);
1423 if (IS_ERR(state->pwdn_gpio)) {
1424 ret = PTR_ERR(state->pwdn_gpio);
1425 v4l_err(client, "request for power pin failed: %d\n", ret);
1426 return ret;
1427 }
1428
1429 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1430 GPIOD_OUT_HIGH);
1431 if (IS_ERR(state->rst_gpio)) {
1432 ret = PTR_ERR(state->rst_gpio);
1433 v4l_err(client, "request for reset pin failed: %d\n", ret);
1434 return ret;
1435 }
1436
1437 if (of_property_read_bool(np, "adv,force-bt656-4") ||
1438 of_property_read_bool(np, "adi,force-bt656-4"))
1439 state->force_bt656_4 = true;
1440
1441 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1442 state->csi_client = i2c_new_dummy_device(client->adapter,
1443 ADV7180_DEFAULT_CSI_I2C_ADDR);
1444 if (IS_ERR(state->csi_client))
1445 return PTR_ERR(state->csi_client);
1446 }
1447
1448 if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1449 state->vpp_client = i2c_new_dummy_device(client->adapter,
1450 ADV7180_DEFAULT_VPP_I2C_ADDR);
1451 if (IS_ERR(state->vpp_client)) {
1452 ret = PTR_ERR(state->vpp_client);
1453 goto err_unregister_csi_client;
1454 }
1455 }
1456
1457 state->irq = client->irq;
1458 mutex_init(&state->mutex);
1459 state->curr_norm = V4L2_STD_NTSC;
1460 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1461 state->powered = true;
1462 else
1463 state->powered = false;
1464 state->input = 0;
1465 sd = &state->sd;
1466 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1467 sd->internal_ops = &adv7180_internal_ops;
1468 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1469
1470 ret = adv7180_init_controls(state);
1471 if (ret)
1472 goto err_unregister_vpp_client;
1473
1474 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1475 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1476 ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1477 if (ret)
1478 goto err_free_ctrl;
1479
1480 ret = init_device(state);
1481 if (ret)
1482 goto err_media_entity_cleanup;
1483
1484 if (state->irq > 0) {
1485 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1486 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1487 KBUILD_MODNAME, state);
1488 if (ret)
1489 goto err_media_entity_cleanup;
1490 }
1491
1492 ret = v4l2_async_register_subdev(sd);
1493 if (ret)
1494 goto err_free_irq;
1495
1496 mutex_lock(&state->mutex);
1497 ret = adv7180_read(state, ADV7180_REG_IDENT);
1498 mutex_unlock(&state->mutex);
1499 if (ret < 0)
1500 goto err_v4l2_async_unregister;
1501
1502 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
1503 ret, client->addr, client->adapter->name);
1504
1505 return 0;
1506
1507 err_v4l2_async_unregister:
1508 v4l2_async_unregister_subdev(sd);
1509 err_free_irq:
1510 if (state->irq > 0)
1511 free_irq(client->irq, state);
1512 err_media_entity_cleanup:
1513 media_entity_cleanup(&sd->entity);
1514 err_free_ctrl:
1515 adv7180_exit_controls(state);
1516 err_unregister_vpp_client:
1517 i2c_unregister_device(state->vpp_client);
1518 err_unregister_csi_client:
1519 i2c_unregister_device(state->csi_client);
1520 mutex_destroy(&state->mutex);
1521 return ret;
1522 }
1523
adv7180_remove(struct i2c_client * client)1524 static void adv7180_remove(struct i2c_client *client)
1525 {
1526 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1527 struct adv7180_state *state = to_state(sd);
1528
1529 v4l2_async_unregister_subdev(sd);
1530
1531 if (state->irq > 0)
1532 free_irq(client->irq, state);
1533
1534 media_entity_cleanup(&sd->entity);
1535 adv7180_exit_controls(state);
1536
1537 i2c_unregister_device(state->vpp_client);
1538 i2c_unregister_device(state->csi_client);
1539
1540 adv7180_set_reset_pin(state, true);
1541 adv7180_set_power_pin(state, false);
1542
1543 mutex_destroy(&state->mutex);
1544 }
1545
1546 #ifdef CONFIG_PM_SLEEP
adv7180_suspend(struct device * dev)1547 static int adv7180_suspend(struct device *dev)
1548 {
1549 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1550 struct adv7180_state *state = to_state(sd);
1551
1552 return adv7180_set_power(state, false);
1553 }
1554
adv7180_resume(struct device * dev)1555 static int adv7180_resume(struct device *dev)
1556 {
1557 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1558 struct adv7180_state *state = to_state(sd);
1559 int ret;
1560
1561 ret = init_device(state);
1562 if (ret < 0)
1563 return ret;
1564
1565 ret = adv7180_set_power(state, state->powered);
1566 if (ret)
1567 return ret;
1568
1569 return 0;
1570 }
1571
1572 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1573 #define ADV7180_PM_OPS (&adv7180_pm_ops)
1574
1575 #else
1576 #define ADV7180_PM_OPS NULL
1577 #endif
1578
1579 static const struct i2c_device_id adv7180_id[] = {
1580 { "adv7180", (kernel_ulong_t)&adv7180_info },
1581 { "adv7180cp", (kernel_ulong_t)&adv7180_info },
1582 { "adv7180st", (kernel_ulong_t)&adv7180_info },
1583 { "adv7182", (kernel_ulong_t)&adv7182_info },
1584 { "adv7280", (kernel_ulong_t)&adv7280_info },
1585 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1586 { "adv7281", (kernel_ulong_t)&adv7281_info },
1587 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1588 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1589 { "adv7282", (kernel_ulong_t)&adv7282_info },
1590 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1591 {}
1592 };
1593 MODULE_DEVICE_TABLE(i2c, adv7180_id);
1594
1595 static const struct of_device_id adv7180_of_id[] = {
1596 { .compatible = "adi,adv7180", &adv7180_info },
1597 { .compatible = "adi,adv7180cp", &adv7180_info },
1598 { .compatible = "adi,adv7180st", &adv7180_info },
1599 { .compatible = "adi,adv7182", &adv7182_info },
1600 { .compatible = "adi,adv7280", &adv7280_info },
1601 { .compatible = "adi,adv7280-m", &adv7280_m_info },
1602 { .compatible = "adi,adv7281", &adv7281_info },
1603 { .compatible = "adi,adv7281-m", &adv7281_m_info },
1604 { .compatible = "adi,adv7281-ma", &adv7281_ma_info },
1605 { .compatible = "adi,adv7282", &adv7282_info },
1606 { .compatible = "adi,adv7282-m", &adv7282_m_info },
1607 {}
1608 };
1609 MODULE_DEVICE_TABLE(of, adv7180_of_id);
1610
1611 static struct i2c_driver adv7180_driver = {
1612 .driver = {
1613 .name = KBUILD_MODNAME,
1614 .pm = ADV7180_PM_OPS,
1615 .of_match_table = adv7180_of_id,
1616 },
1617 .probe = adv7180_probe,
1618 .remove = adv7180_remove,
1619 .id_table = adv7180_id,
1620 };
1621
1622 module_i2c_driver(adv7180_driver);
1623
1624 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1625 MODULE_AUTHOR("Mocean Laboratories");
1626 MODULE_LICENSE("GPL v2");
1627