| /linux/arch/arm/boot/dts/arm/ |
| H A D | vexpress-v2p-ca15_a7.dts | 257 /* A15 PLL 0 reference clock */ 266 /* A15 PLL 1 reference clock */ 338 /* A15 CPU core voltage */ 341 regulator-name = "A15 Vcore"; 345 label = "A15 Vcore"; 360 /* Total current for the two A15 cores */ 363 label = "A15 Icore"; 381 /* Total power for the two A15 cores */ 384 label = "A15 Pcore"; 395 /* Total energy for the two A15 cores */ [all …]
|
| H A D | vexpress-v2p-ca15-tc1.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
|
| /linux/arch/arm/include/debug/ |
| H A D | exynos.S | 23 teq \tmp, #0xf0 @@ A15 27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
|
| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5420-cpus.dtsi | 9 * boards: CPU[0123] being the A15. 14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
|
| H A D | exynos5422-odroidxu3.dts | 27 /* A15 cluster: VDD_ARM */
|
| H A D | exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
|
| H A D | exynos5422-cpus.dtsi | 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
|
| /linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | vexpress.txt | 22 label = "A15 Jcore";
|
| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso | 34 AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */
|
| H A D | k3-am62p5-var-som.dtsi | 263 AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
|
| /linux/arch/arm/boot/dts/xen/ |
| H A D | xenvm-4.2.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
|
| /linux/arch/arm/mach-hisi/ |
| H A D | Kconfig | 37 bool "Hisilicon HiP04 Cortex A15 family"
|
| /linux/Documentation/arch/arm/keystone/ |
| H A D | overview.rst | 7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
|
| /linux/arch/arm/mach-exynos/ |
| H A D | Kconfig | 67 Samsung Exynos5 (Cortex-A15/A7) SoC based systems
|
| /linux/arch/arm/crypto/ |
| H A D | Kconfig | 40 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am335x-boneblue.dts | 124 …AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0… 463 "WIFI_LED", /* A15 */
|
| H A D | am335x-icev2.dts | 159 …AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0…
|
| /linux/Documentation/arch/arm/ |
| H A D | sunxi.rst | 123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
|
| /linux/drivers/pinctrl/aspeed/ |
| H A D | pinctrl-aspeed-g5.c | 583 #define A15 71 macro 591 SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1); 592 SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC); 593 PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO); 595 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15); 596 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15); 597 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15); 598 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15); 1907 ASPEED_PINCTRL_PIN(A15), 2526 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24), [all …]
|
| H A D | pinctrl-aspeed-g6.c | 576 #define A15 71 macro 577 SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7)); 578 SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7)); 579 PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI); 580 FUNC_GROUP_DECL(BMCINT, A15); 581 FUNC_GROUP_DECL(SIOSCI, A15); 1650 ASPEED_PINCTRL_PIN(A15), 2426 ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
|
| H A D | pinctrl-aspeed-g4.c | 332 #define A15 35 macro 333 SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); 336 SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE); 337 PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT); 339 FUNC_GROUP_DECL(NRI3, A15); 340 FUNC_GROUP_DECL(GPIE2, B15, A15); 1912 ASPEED_PINCTRL_PIN(A15), 2537 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
|
| /linux/drivers/soc/tegra/ |
| H A D | Kconfig | 75 Tegra124's "4+1" Cortex-A15 CPU complex.
|
| /linux/arch/arm/mm/ |
| H A D | proc-v7.S | 521 ldr r10, =0x00000c0f @ Cortex-A15 primary part number 622 @ Cortex-A15 - needs iciallu switch_mm for hardening
|
| /linux/arch/arm/kernel/ |
| H A D | entry-header.S | 350 @ We must avoid clrex due to Cortex-A15 erratum #830321
|
| /linux/arch/arm/mach-versatile/ |
| H A D | Kconfig | 259 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
|