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/linux/drivers/gpu/drm/ci/xfails/
H A Di915-glk-skips.txt80 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
81 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
82 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
83 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
84 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
85 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
86 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
87 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
88 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
89 # i915 0000:00:02.0: [drm] *ERROR* AUX A/DDI A/PHY A: not done (status 0x00000000)
[all …]
/linux/rust/kernel/alloc/
H A Dkbox.rs81 pub struct Box<#[cfg_attr(CONFIG_RUSTC_HAS_COERCE_POINTEE, pointee)] T: ?Sized, A: Allocator>(
83 PhantomData<A>,
89 impl<T, U, A> core::ops::CoerceUnsized<Box<U, A>> for Box<T, A>
93 A: Allocator,
100 impl<T, U, A> core::ops::DispatchFromDyn<Box<U, A>> for Box<T, A>
104 A: Allocator,
146 unsafe impl<T, A: Allocator> ZeroableOption for Box<T, A> {}
149 unsafe impl<T, A> Send for Box<T, A>
152 A: Allocator,
157 unsafe impl<T, A> Sync for Box<T, A>
[all …]
H A Dkvec.rs104 pub struct Vec<T, A: Allocator> {
112 _p: PhantomData<A>,
155 unsafe impl<T, A> Send for Vec<T, A>
158 A: Allocator,
163 unsafe impl<T, A> Sync for Vec<T, A>
166 A: Allocator,
170 impl<T, A> Vec<T, A>
172 A: Allocator,
295 _p: PhantomData::<A>, in new()
567 _p: PhantomData::<A>, in from_raw_parts()
[all …]
/linux/fs/squashfs/
H A Dsquashfs_fs.h130 #define SQUASHFS_INODE_BLK(A) ((unsigned int) ((A) >> 16)) argument
132 #define SQUASHFS_INODE_OFFSET(A) ((unsigned int) ((A) & 0xffff)) argument
134 #define SQUASHFS_MKINODE(A, B) ((long long)(((long long) (A)\ argument
138 #define SQUASHFS_FRAGMENT_BYTES(A) \ argument
139 ((A) * sizeof(struct squashfs_fragment_entry))
141 #define SQUASHFS_FRAGMENT_INDEX(A) (SQUASHFS_FRAGMENT_BYTES(A) / \ argument
144 #define SQUASHFS_FRAGMENT_INDEX_OFFSET(A) (SQUASHFS_FRAGMENT_BYTES(A) % \ argument
147 #define SQUASHFS_FRAGMENT_INDEXES(A) ((SQUASHFS_FRAGMENT_BYTES(A) + \ argument
151 #define SQUASHFS_FRAGMENT_INDEX_BYTES(A) (SQUASHFS_FRAGMENT_INDEXES(A) *\ argument
155 #define SQUASHFS_LOOKUP_BYTES(A) ((A) * sizeof(u64)) argument
[all …]
/linux/scripts/coccinelle/misc/
H A Dboolconv.cocci19 expression A, B;
24 A == B
26 A != B
28 A > B
30 A < B
32 A >= B
34 A <= B
36 A && B
38 A || B
47 expression A, B;
[all …]
H A Dexcluded_middle.cocci3 /// Condition !A || A && B is equivalent to !A || B.
15 expression A, B;
19 * !A || (A &&@p B)
22 expression A, B;
25 !A ||
26 - (A && B)
33 coccilib.report.print_report(p[0], "WARNING !A || A && B is equivalent to !A || B")
39 coccilib.org.print_todo(p[0], "WARNING !A || A && B is equivalent to !A || B")
/linux/Documentation/translations/ko_KR/
H A Dmemory-barriers.txt181 { A == 1; B == 2 }
182 A = 3; x = B;
183 B = 4; y = A;
188 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
189 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
190 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
191 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
192 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
193 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
194 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
[all …]
/linux/include/drm/
H A Ddrm_fixed.h37 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ argument
38 #define dfixed_const_half(A) (u32)(((A) << 12) + 2048) argument
39 #define dfixed_const_666(A) (u32)(((A) << 12) + 2731) argument
40 #define dfixed_const_8(A) (u32)(((A) << 12) + 3277) argument
41 #define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) argument
42 #define dfixed_init(A) { .full = dfixed_const((A)) } argument
43 #define dfixed_init_half(A) { .full = dfixed_const_half((A)) } argument
44 #define dfixed_trunc(A) ((A).full >> 12) argument
45 #define dfixed_frac(A) ((A).full & ((1 << 12) - 1)) argument
47 static inline u32 dfixed_floor(fixed20_12 A) in dfixed_floor() argument
[all …]
/linux/rust/kernel/time/hrtimer/
H A Dtbox.rs20 pub struct BoxHrTimerHandle<T, A>
23 A: crate::alloc::Allocator,
26 _p: core::marker::PhantomData<A>,
31 unsafe impl<T, A> HrTimerHandle for BoxHrTimerHandle<T, A>
34 A: crate::alloc::Allocator,
47 impl<T, A> Drop for BoxHrTimerHandle<T, A>
50 A: crate::alloc::Allocator,
56 drop(unsafe { Box::<T, A>::from_raw(self.inner.as_ptr()) }) in drop()
60 impl<T, A> HrTimerPointer for Pin<Box<T, A>>
65 T: for<'a> HrTimerCallback<Pointer<'a> = Pin<Box<T, A>>>,
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5_macb0.dtsi19 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
20 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
21 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
22 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
23 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
24 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
25 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
26 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
27 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
28 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
[all …]
H A Dsama5d3_gmac.dtsi19 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
20 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
21 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
22 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
23 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
24 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
25 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
26 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
41 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
42 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
[all …]
H A Dat91sam9g45.dtsi197 /* A B */
257 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
258 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
265 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
266 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
326 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
331 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
386 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
387 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
388 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
[all …]
/linux/drivers/gpu/drm/i915/selftests/
H A Di915_sw_fence.c98 struct i915_sw_fence *A, *B, *C; in test_dag() local
105 A = alloc_fence(); in test_dag()
106 if (!A) in test_dag()
109 if (i915_sw_fence_await_sw_fence_gfp(A, A, GFP_KERNEL) != -EINVAL) { in test_dag()
120 i915_sw_fence_await_sw_fence_gfp(A, B, GFP_KERNEL); in test_dag()
121 if (i915_sw_fence_await_sw_fence_gfp(B, A, GFP_KERNEL) != -EINVAL) { in test_dag()
140 if (i915_sw_fence_await_sw_fence_gfp(C, A, GFP_KERNEL) != -EINVAL) { in test_dag()
144 if (i915_sw_fence_await_sw_fence_gfp(A, C, GFP_KERNEL) == -EINVAL) { in test_dag()
149 i915_sw_fence_commit(A); in test_dag()
162 if (!i915_sw_fence_done(A)) { in test_dag()
[all …]
/linux/Documentation/i2c/
H A Dsmbus-protocol.rst43 A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
48 Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and
50 Count (8 bits) A data byte containing the length of a block operation.
62 S Addr Rd/Wr [A] P
77 S Addr Rd [A] [Data] NA P
92 S Addr Wr [A] Data [A] P
105 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P
119 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
139 S Addr Wr [A] Comm [A] Data [A] P
153 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
[all …]
H A Di2c-protocol.rst15 A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
18 Data (8 bits) A plain data byte.
30 S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
38 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
50 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
62 client. Setting this flag treats any [NA] as [A], and all of
67 In a read message, master A/NA bit is skipped.
70 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
74 S Addr Rd [A] [Data] NA Data [A] P
91 S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.h137 #define NVBO_RD32(A...) DRF_RD(NVBO_RD32_, ##A) argument
138 #define NVBO_RV32(A...) DRF_RV(NVBO_RD32_, ##A) argument
139 #define NVBO_TV32(A...) DRF_TV(NVBO_RD32_, ##A) argument
140 #define NVBO_TD32(A...) DRF_TD(NVBO_RD32_, ##A) argument
141 #define NVBO_WR32(A...) DRF_WR( NVBO_WR32_, ##A) argument
142 #define NVBO_WV32(A...) DRF_WV( NVBO_WR32_, ##A) argument
143 #define NVBO_WD32(A...) DRF_WD( NVBO_WR32_, ##A) argument
144 #define NVBO_MR32(A...) DRF_MR(NVBO_RD32_, NVBO_WR32_, u32, ##A) argument
145 #define NVBO_MV32(A...) DRF_MV(NVBO_RD32_, NVBO_WR32_, u32, ##A) argument
146 #define NVBO_MD32(A...) DRF_MD(NVBO_RD32_, NVBO_WR32_, u32, ##A) argument
/linux/drivers/atm/
H A Diphase.h74 #define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A } argument
75 #define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A } argument
76 #define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A } argument
78 #define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A } argument
79 #define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A } argument
80 #define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A } argument
81 #define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A } argument
82 #define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A } argument
84 #define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A } argument
85 #define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A } argument
[all …]
/linux/Documentation/translations/it_IT/i2c/
H A Di2c-protocol.rst15 A, NA (1 bit) Bit di riconoscimento (ACK) e di non riconoscimento (NACK).
30 S Addr Wr [A] Dati [A] Dati [A] ... [A] Dati [A] P
38 S Addr Rd [A] [Dati] A [Dati] A ... A [Dati] NA P
50 S Addr Rd [A] [Dati] NA S Addr Wr [A] Dati [A] P
63 [A] e tutto il messaggio viene inviato.
68 In un messaggio di lettura, il bit A/NA del master viene saltato.
72 "S Addr Wr/Rd [A]".
76 S Addr Rd [A] [Dati] NA Dati [A] P
94 S Addr Rd [A] Dati [A] Dati [A] ... [A] Dati [A] P
/linux/Documentation/arch/arm64/
H A Dsilicon-errata.rst15 Category A A critical error without a viable workaround.
16 Category B A significant or critical error with an acceptable
18 Category C A minor error that is not expected to occur under normal
28 sequence of code, or configuring the processor in a particular way. A
30 a Category A erratum into a Category C erratum. These are collectively
103 | ARM | Cortex-A57 | #852523 | N/A |
111 | ARM | Cortex-A72 | #853709 | N/A |
127 | ARM | Cortex-A76 | #1490853 | N/A |
131 | ARM | Cortex-A77 | #1491015 | N/A |
157 | ARM | Cortex-X1 | #1502854 | N/A |
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/
H A Ddrf.h66 #define NVVAL(A...) NVVAL_(X, ##A, NVVAL_I, NVVAL_N)(X, ##A) argument
71 #define NVDEF(A...) NVDEF_(X, ##A, NVDEF_I, NVDEF_N)(X, ##A) argument
77 #define NVVAL_GET(A...) NVVAL_GET_(X, ##A, NVVAL_GET_I, NVVAL_GET_N)(X, ##A) argument
83 #define NVVAL_TEST(A...) NVVAL_TEST_(X, ##A, NVVAL_TEST_I, NVVAL_TEST_N)(X, ##A) argument
88 #define NVDEF_TEST(A...) NVDEF_TEST_(X, ##A, NVDEF_TEST_I, NVDEF_TEST_N)(X, ##A) argument
94 #define NVVAL_SET(A...) NVVAL_SET_(X, ##A, NVVAL_SET_I, NVVAL_SET_N)(X, ##A) argument
99 #define NVDEF_SET(A...) NVDEF_SET_(X, ##A, NVDEF_SET_I, NVDEF_SET_N)(X, ##A) argument
108 #define NVVAL_MW_GET(A...) NVVAL_MW_GET_(X, ##A, NVVAL_MW_GET_I, NVVAL_MW_GET_N)(X, ##A) argument
118 #define NVVAL_MW_SET(A...) NVVAL_MW_SET_(X, ##A, NVVAL_MW_SET_I, NVVAL_MW_SET_N)(X, ##A) argument
123 #define NVDEF_MW_SET(A...) NVDEF_MW_SET_(X, ##A, NVDEF_MW_SET_I, NVDEF_MW_SET_N)(X, ##A) argument
[all …]
/linux/Documentation/features/core/mseal_sys_mappings/
H A Darch-support.txt10 | arc: | N/A |
11 | arm: | N/A |
13 | csky: | N/A |
14 | hexagon: | N/A |
16 | m68k: | N/A |
17 | microblaze: | N/A |
19 | nios2: | N/A |
20 | openrisc: | N/A |
25 | sh: | N/A |
29 | xtensa: | N/A |
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dobject.h116 #define NVIF_RD32(p,A...) DRF_RD(NVIF_RD32_, (p), 0, ##A) argument
117 #define NVIF_RV32(p,A...) DRF_RV(NVIF_RD32_, (p), 0, ##A) argument
118 #define NVIF_TV32(p,A...) DRF_TV(NVIF_RD32_, (p), 0, ##A) argument
119 #define NVIF_TD32(p,A...) DRF_TD(NVIF_RD32_, (p), 0, ##A) argument
120 #define NVIF_WR32(p,A...) DRF_WR( NVIF_WR32_, (p), 0, ##A) argument
121 #define NVIF_WV32(p,A...) DRF_WV( NVIF_WR32_, (p), 0, ##A) argument
122 #define NVIF_WD32(p,A...) DRF_WD( NVIF_WR32_, (p), 0, ##A) argument
123 #define NVIF_MR32(p,A...) DRF_MR(NVIF_RD32_, NVIF_WR32_, u32, (p), 0, ##A) argument
124 #define NVIF_MV32(p,A...) DRF_MV(NVIF_RD32_, NVIF_WR32_, u32, (p), 0, ##A) argument
125 #define NVIF_MD32(p,A...) DRF_MD(NVIF_RD32_, NVIF_WR32_, u32, (p), 0, ##A) argument
/linux/net/batman-adv/
H A DKconfig2 # Copyright (C) B.A.T.M.A.N. contributors:
7 # B.A.T.M.A.N meshing protocol
11 tristate "B.A.T.M.A.N. Advanced Meshing Protocol"
14 B.A.T.M.A.N. (better approach to mobile ad-hoc networking) is
21 bool "B.A.T.M.A.N. V protocol"
25 This option enables the B.A.T.M.A.N. V protocol, the successor
26 of the currently used B.A.T.M.A.N. IV protocol. The main
31 B.A.T.M.A.N. V is currently considered experimental and not
32 compatible to B.A.T.M.A.N. IV networks.
66 bool "B.A.T.M.A.N. debugging"
[all …]
/linux/lib/crypto/x86/
H A Dsha1-ssse3-and-avx.S113 mov (HASH_PTR), A
127 RR F1,A,B,C,D,E,0
128 RR F1,D,E,A,B,C,2
129 RR F1,B,C,D,E,A,4
130 RR F1,E,A,B,C,D,6
131 RR F1,C,D,E,A,B,8
133 RR F1,A,B,C,D,E,10
134 RR F1,D,E,A,B,C,12
135 RR F1,B,C,D,E,A,14
136 RR F1,E,A,B,C,D,16
[all …]
/linux/Documentation/translations/zh_CN/driver-api/
H A Dio_ordering.rst28 CPU A: spin_lock_irqsave(&dev_lock, flags)
29 CPU A: val = readl(my_status);
30 CPU A: ...
31 CPU A: writel(newval, ring_ptr);
32 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
45 CPU A: spin_lock_irqsave(&dev_lock, flags)
46 CPU A: val = readl(my_status);
47 CPU A: ...
48 CPU A: writel(newval, ring_ptr);
49 CPU A: (void)readl(safe_register); /* 配置寄存器？*/
[all …]

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