1 #ifndef _X86_MSR_H_ 2 #define _X86_MSR_H_ 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_SPEC_CTRL 0x00000048 36 #define SPEC_CTRL_IBRS BIT(0) 37 #define SPEC_CTRL_STIBP BIT(1) 38 #define SPEC_CTRL_SSBD BIT(2) 39 40 #define MSR_IA32_PRED_CMD 0x00000049 41 #define PRED_CMD_IBPB BIT(0) 42 43 #define MSR_IA32_FLUSH_CMD 0x0000010b 44 #define L1D_FLUSH BIT(0) 45 46 #define MSR_IA32_PMC0 0x000004c1 47 #define MSR_IA32_PERFCTR0 0x000000c1 48 #define MSR_IA32_PERFCTR1 0x000000c2 49 #define MSR_FSB_FREQ 0x000000cd 50 51 #define MSR_MTRRcap 0x000000fe 52 #define MSR_IA32_BBL_CR_CTL 0x00000119 53 54 #define MSR_IA32_SYSENTER_CS 0x00000174 55 #define MSR_IA32_SYSENTER_ESP 0x00000175 56 #define MSR_IA32_SYSENTER_EIP 0x00000176 57 58 #define MSR_IA32_MCG_CAP 0x00000179 59 #define MSR_IA32_MCG_STATUS 0x0000017a 60 #define MSR_IA32_MCG_CTL 0x0000017b 61 62 #define MSR_IA32_PEBS_ENABLE 0x000003f1 63 #define MSR_PEBS_DATA_CFG 0x000003f2 64 #define MSR_IA32_DS_AREA 0x00000600 65 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 66 67 #define MSR_MTRRfix64K_00000 0x00000250 68 #define MSR_MTRRfix16K_80000 0x00000258 69 #define MSR_MTRRfix16K_A0000 0x00000259 70 #define MSR_MTRRfix4K_C0000 0x00000268 71 #define MSR_MTRRfix4K_C8000 0x00000269 72 #define MSR_MTRRfix4K_D0000 0x0000026a 73 #define MSR_MTRRfix4K_D8000 0x0000026b 74 #define MSR_MTRRfix4K_E0000 0x0000026c 75 #define MSR_MTRRfix4K_E8000 0x0000026d 76 #define MSR_MTRRfix4K_F0000 0x0000026e 77 #define MSR_MTRRfix4K_F8000 0x0000026f 78 #define MSR_MTRRdefType 0x000002ff 79 80 #define MSR_IA32_CR_PAT 0x00000277 81 82 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 83 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 84 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 85 #define MSR_IA32_LASTINTFROMIP 0x000001dd 86 #define MSR_IA32_LASTINTTOIP 0x000001de 87 88 /* Yes, AMD does indeed record mispredict info in the LBR records themselves. */ 89 #define AMD_LBR_RECORD_MISPREDICT BIT_ULL(63) 90 91 #define LBR_INFO_MISPRED BIT_ULL(63) 92 #define LBR_INFO_IN_TX BIT_ULL(62) 93 #define LBR_INFO_ABORT BIT_ULL(61) 94 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 95 #define LBR_INFO_CYCLES 0xffff 96 #define LBR_INFO_BR_TYPE_OFFSET 56 97 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 98 99 /* DEBUGCTLMSR bits (others vary by model): */ 100 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 101 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 102 #define DEBUGCTLMSR_TR (1UL << 6) 103 #define DEBUGCTLMSR_BTS (1UL << 7) 104 #define DEBUGCTLMSR_BTINT (1UL << 8) 105 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 106 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 107 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 108 109 #define MSR_LBR_NHM_FROM 0x00000680 110 #define MSR_LBR_NHM_TO 0x000006c0 111 #define MSR_LBR_CORE_FROM 0x00000040 112 #define MSR_LBR_CORE_TO 0x00000060 113 #define MSR_LBR_TOS 0x000001c9 114 #define MSR_LBR_SELECT 0x000001c8 115 116 #define MSR_IA32_MC0_CTL 0x00000400 117 #define MSR_IA32_MC0_STATUS 0x00000401 118 #define MSR_IA32_MC0_ADDR 0x00000402 119 #define MSR_IA32_MC0_MISC 0x00000403 120 121 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 122 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 123 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 124 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 125 126 /* These are consecutive and not in the normal 4er MCE bank block */ 127 #define MSR_IA32_MC0_CTL2 0x00000280 128 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 129 130 #define CMCI_EN (1ULL << 30) 131 #define CMCI_THRESHOLD_MASK 0xffffULL 132 133 #define MSR_P6_PERFCTR0 0x000000c1 134 #define MSR_P6_PERFCTR1 0x000000c2 135 #define MSR_P6_EVNTSEL0 0x00000186 136 #define MSR_P6_EVNTSEL1 0x00000187 137 138 #define MSR_IA32_RTIT_CTL 0x00000570 139 #define RTIT_CTL_TRACEEN BIT(0) 140 #define RTIT_CTL_CYCLEACC BIT(1) 141 #define RTIT_CTL_OS BIT(2) 142 #define RTIT_CTL_USR BIT(3) 143 #define RTIT_CTL_PWR_EVT_EN BIT(4) 144 #define RTIT_CTL_FUP_ON_PTW BIT(5) 145 #define RTIT_CTL_FABRIC_EN BIT(6) 146 #define RTIT_CTL_CR3EN BIT(7) 147 #define RTIT_CTL_TOPA BIT(8) 148 #define RTIT_CTL_MTC_EN BIT(9) 149 #define RTIT_CTL_TSC_EN BIT(10) 150 #define RTIT_CTL_DISRETC BIT(11) 151 #define RTIT_CTL_PTW_EN BIT(12) 152 #define RTIT_CTL_BRANCH_EN BIT(13) 153 #define RTIT_CTL_EVENT_EN BIT(31) 154 #define RTIT_CTL_NOTNT BIT_ULL(55) 155 #define RTIT_CTL_MTC_RANGE_OFFSET 14 156 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 157 #define RTIT_CTL_CYC_THRESH_OFFSET 19 158 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 159 #define RTIT_CTL_PSB_FREQ_OFFSET 24 160 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 161 #define RTIT_CTL_ADDR0_OFFSET 32 162 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 163 #define RTIT_CTL_ADDR1_OFFSET 36 164 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 165 #define RTIT_CTL_ADDR2_OFFSET 40 166 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 167 #define RTIT_CTL_ADDR3_OFFSET 44 168 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 169 170 171 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 172 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 173 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 174 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 175 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 176 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 177 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 178 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 179 180 /* AMD64 MSRs. Not complete. See the architecture manual for a more 181 complete list. */ 182 183 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 184 #define MSR_AMD64_NB_CFG 0xc001001f 185 #define MSR_AMD64_PATCH_LOADER 0xc0010020 186 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 187 #define MSR_AMD64_OSVW_STATUS 0xc0010141 188 #define MSR_AMD64_DC_CFG 0xc0011022 189 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 190 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 191 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 192 #define MSR_AMD64_IBSOPCTL 0xc0011033 193 #define MSR_AMD64_IBSOPRIP 0xc0011034 194 #define MSR_AMD64_IBSOPDATA 0xc0011035 195 #define MSR_AMD64_IBSOPDATA2 0xc0011036 196 #define MSR_AMD64_IBSOPDATA3 0xc0011037 197 #define MSR_AMD64_IBSDCLINAD 0xc0011038 198 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 199 #define MSR_AMD64_IBSCTL 0xc001103a 200 201 /* Fam 10h MSRs */ 202 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 203 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 204 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 205 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 206 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 207 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 208 #define MSR_FAM10H_NODE_ID 0xc001100c 209 210 /* Fam 15h MSRs */ 211 #define MSR_F15H_PERF_CTL 0xc0010200 212 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 213 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 214 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 215 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 216 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 217 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 218 219 #define MSR_F15H_PERF_CTR 0xc0010201 220 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 221 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 222 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 223 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 224 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 225 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 226 227 /* K8 MSRs */ 228 #define MSR_K8_TOP_MEM1 0xc001001a 229 #define MSR_K8_TOP_MEM2 0xc001001d 230 #define MSR_K8_SYSCFG 0xc0010010 231 #define MSR_K8_INT_PENDING_MSG 0xc0010055 232 /* C1E active bits in int pending message */ 233 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 234 #define MSR_K8_TSEG_ADDR 0xc0010112 235 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 236 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 237 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 238 239 /* K7 MSRs */ 240 #define MSR_K7_EVNTSEL0 0xc0010000 241 #define MSR_K7_PERFCTR0 0xc0010004 242 #define MSR_K7_EVNTSEL1 0xc0010001 243 #define MSR_K7_PERFCTR1 0xc0010005 244 #define MSR_K7_EVNTSEL2 0xc0010002 245 #define MSR_K7_PERFCTR2 0xc0010006 246 #define MSR_K7_EVNTSEL3 0xc0010003 247 #define MSR_K7_PERFCTR3 0xc0010007 248 #define MSR_K7_CLK_CTL 0xc001001b 249 #define MSR_K7_HWCR 0xc0010015 250 #define MSR_K7_FID_VID_CTL 0xc0010041 251 #define MSR_K7_FID_VID_STATUS 0xc0010042 252 253 /* K6 MSRs */ 254 #define MSR_K6_EFER 0xc0000080 255 #define MSR_K6_STAR 0xc0000081 256 #define MSR_K6_WHCR 0xc0000082 257 #define MSR_K6_UWCCR 0xc0000085 258 #define MSR_K6_EPMR 0xc0000086 259 #define MSR_K6_PSOR 0xc0000087 260 #define MSR_K6_PFIR 0xc0000088 261 262 /* Centaur-Hauls/IDT defined MSRs. */ 263 #define MSR_IDT_FCR1 0x00000107 264 #define MSR_IDT_FCR2 0x00000108 265 #define MSR_IDT_FCR3 0x00000109 266 #define MSR_IDT_FCR4 0x0000010a 267 268 #define MSR_IDT_MCR0 0x00000110 269 #define MSR_IDT_MCR1 0x00000111 270 #define MSR_IDT_MCR2 0x00000112 271 #define MSR_IDT_MCR3 0x00000113 272 #define MSR_IDT_MCR4 0x00000114 273 #define MSR_IDT_MCR5 0x00000115 274 #define MSR_IDT_MCR6 0x00000116 275 #define MSR_IDT_MCR7 0x00000117 276 #define MSR_IDT_MCR_CTRL 0x00000120 277 278 /* VIA Cyrix defined MSRs*/ 279 #define MSR_VIA_FCR 0x00001107 280 #define MSR_VIA_LONGHAUL 0x0000110a 281 #define MSR_VIA_RNG 0x0000110b 282 #define MSR_VIA_BCR2 0x00001147 283 284 /* Transmeta defined MSRs */ 285 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 286 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 287 #define MSR_TMTA_LRTI_READOUT 0x80868018 288 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 289 290 /* Intel defined MSRs. */ 291 #define MSR_IA32_P5_MC_ADDR 0x00000000 292 #define MSR_IA32_P5_MC_TYPE 0x00000001 293 #define MSR_IA32_TSC 0x00000010 294 #define MSR_IA32_PLATFORM_ID 0x00000017 295 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 296 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 297 #define MSR_IA32_TSC_ADJUST 0x0000003b 298 #define MSR_IA32_U_CET 0x000006a0 299 #define MSR_IA32_PL3_SSP 0x000006a7 300 #define MSR_IA32_PKRS 0x000006e1 301 302 #define FEATURE_CONTROL_LOCKED (1<<0) 303 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 304 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 305 306 #define MSR_IA32_APICBASE 0x0000001b 307 #define MSR_IA32_APICBASE_BSP (1<<8) 308 #define MSR_IA32_APICBASE_ENABLE (1<<11) 309 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 310 311 #define MSR_IA32_UCODE_WRITE 0x00000079 312 #define MSR_IA32_UCODE_REV 0x0000008b 313 314 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 315 #define ARCH_CAP_RDCL_NO (1ULL << 0) 316 #define ARCH_CAP_IBRS_ALL (1ULL << 1) 317 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1ULL << 3) 318 #define ARCH_CAP_SSB_NO (1ULL << 4) 319 #define ARCH_CAP_MDS_NO (1ULL << 5) 320 #define ARCH_CAP_PSCHANGE_MC_NO (1ULL << 6) 321 #define ARCH_CAP_TSX_CTRL_MSR (1ULL << 7) 322 #define ARCH_CAP_TAA_NO (1ULL << 8) 323 324 #define MSR_IA32_TSX_CTRL 0x00000122 325 #define TSX_CTRL_RTM_DISABLE (1ULL << 0) 326 #define TSX_CTRL_CPUID_CLEAR (1ULL << 1) 327 328 #define MSR_IA32_PERF_STATUS 0x00000198 329 #define MSR_IA32_PERF_CTL 0x00000199 330 331 #define MSR_IA32_MPERF 0x000000e7 332 #define MSR_IA32_APERF 0x000000e8 333 334 #define MSR_IA32_THERM_CONTROL 0x0000019a 335 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 336 337 #define THERM_INT_LOW_ENABLE (1 << 0) 338 #define THERM_INT_HIGH_ENABLE (1 << 1) 339 340 #define MSR_IA32_THERM_STATUS 0x0000019c 341 342 #define THERM_STATUS_PROCHOT (1 << 0) 343 344 #define MSR_THERM2_CTL 0x0000019d 345 346 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 347 348 #define MSR_IA32_MISC_ENABLE 0x000001a0 349 350 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 351 352 /* MISC_ENABLE bits: architectural */ 353 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 354 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 355 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 356 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 357 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 358 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 359 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 360 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 361 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 362 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 363 364 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 365 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 366 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 367 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 368 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 369 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 370 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 371 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 372 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 373 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 374 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 375 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 376 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 377 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 378 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 379 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 380 381 /* P4/Xeon+ specific */ 382 #define MSR_IA32_MCG_EAX 0x00000180 383 #define MSR_IA32_MCG_EBX 0x00000181 384 #define MSR_IA32_MCG_ECX 0x00000182 385 #define MSR_IA32_MCG_EDX 0x00000183 386 #define MSR_IA32_MCG_ESI 0x00000184 387 #define MSR_IA32_MCG_EDI 0x00000185 388 #define MSR_IA32_MCG_EBP 0x00000186 389 #define MSR_IA32_MCG_ESP 0x00000187 390 #define MSR_IA32_MCG_EFLAGS 0x00000188 391 #define MSR_IA32_MCG_EIP 0x00000189 392 #define MSR_IA32_MCG_RESERVED 0x0000018a 393 394 /* Pentium IV performance counter MSRs */ 395 #define MSR_P4_BPU_PERFCTR0 0x00000300 396 #define MSR_P4_BPU_PERFCTR1 0x00000301 397 #define MSR_P4_BPU_PERFCTR2 0x00000302 398 #define MSR_P4_BPU_PERFCTR3 0x00000303 399 #define MSR_P4_MS_PERFCTR0 0x00000304 400 #define MSR_P4_MS_PERFCTR1 0x00000305 401 #define MSR_P4_MS_PERFCTR2 0x00000306 402 #define MSR_P4_MS_PERFCTR3 0x00000307 403 #define MSR_P4_FLAME_PERFCTR0 0x00000308 404 #define MSR_P4_FLAME_PERFCTR1 0x00000309 405 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 406 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 407 #define MSR_P4_IQ_PERFCTR0 0x0000030c 408 #define MSR_P4_IQ_PERFCTR1 0x0000030d 409 #define MSR_P4_IQ_PERFCTR2 0x0000030e 410 #define MSR_P4_IQ_PERFCTR3 0x0000030f 411 #define MSR_P4_IQ_PERFCTR4 0x00000310 412 #define MSR_P4_IQ_PERFCTR5 0x00000311 413 #define MSR_P4_BPU_CCCR0 0x00000360 414 #define MSR_P4_BPU_CCCR1 0x00000361 415 #define MSR_P4_BPU_CCCR2 0x00000362 416 #define MSR_P4_BPU_CCCR3 0x00000363 417 #define MSR_P4_MS_CCCR0 0x00000364 418 #define MSR_P4_MS_CCCR1 0x00000365 419 #define MSR_P4_MS_CCCR2 0x00000366 420 #define MSR_P4_MS_CCCR3 0x00000367 421 #define MSR_P4_FLAME_CCCR0 0x00000368 422 #define MSR_P4_FLAME_CCCR1 0x00000369 423 #define MSR_P4_FLAME_CCCR2 0x0000036a 424 #define MSR_P4_FLAME_CCCR3 0x0000036b 425 #define MSR_P4_IQ_CCCR0 0x0000036c 426 #define MSR_P4_IQ_CCCR1 0x0000036d 427 #define MSR_P4_IQ_CCCR2 0x0000036e 428 #define MSR_P4_IQ_CCCR3 0x0000036f 429 #define MSR_P4_IQ_CCCR4 0x00000370 430 #define MSR_P4_IQ_CCCR5 0x00000371 431 #define MSR_P4_ALF_ESCR0 0x000003ca 432 #define MSR_P4_ALF_ESCR1 0x000003cb 433 #define MSR_P4_BPU_ESCR0 0x000003b2 434 #define MSR_P4_BPU_ESCR1 0x000003b3 435 #define MSR_P4_BSU_ESCR0 0x000003a0 436 #define MSR_P4_BSU_ESCR1 0x000003a1 437 #define MSR_P4_CRU_ESCR0 0x000003b8 438 #define MSR_P4_CRU_ESCR1 0x000003b9 439 #define MSR_P4_CRU_ESCR2 0x000003cc 440 #define MSR_P4_CRU_ESCR3 0x000003cd 441 #define MSR_P4_CRU_ESCR4 0x000003e0 442 #define MSR_P4_CRU_ESCR5 0x000003e1 443 #define MSR_P4_DAC_ESCR0 0x000003a8 444 #define MSR_P4_DAC_ESCR1 0x000003a9 445 #define MSR_P4_FIRM_ESCR0 0x000003a4 446 #define MSR_P4_FIRM_ESCR1 0x000003a5 447 #define MSR_P4_FLAME_ESCR0 0x000003a6 448 #define MSR_P4_FLAME_ESCR1 0x000003a7 449 #define MSR_P4_FSB_ESCR0 0x000003a2 450 #define MSR_P4_FSB_ESCR1 0x000003a3 451 #define MSR_P4_IQ_ESCR0 0x000003ba 452 #define MSR_P4_IQ_ESCR1 0x000003bb 453 #define MSR_P4_IS_ESCR0 0x000003b4 454 #define MSR_P4_IS_ESCR1 0x000003b5 455 #define MSR_P4_ITLB_ESCR0 0x000003b6 456 #define MSR_P4_ITLB_ESCR1 0x000003b7 457 #define MSR_P4_IX_ESCR0 0x000003c8 458 #define MSR_P4_IX_ESCR1 0x000003c9 459 #define MSR_P4_MOB_ESCR0 0x000003aa 460 #define MSR_P4_MOB_ESCR1 0x000003ab 461 #define MSR_P4_MS_ESCR0 0x000003c0 462 #define MSR_P4_MS_ESCR1 0x000003c1 463 #define MSR_P4_PMH_ESCR0 0x000003ac 464 #define MSR_P4_PMH_ESCR1 0x000003ad 465 #define MSR_P4_RAT_ESCR0 0x000003bc 466 #define MSR_P4_RAT_ESCR1 0x000003bd 467 #define MSR_P4_SAAT_ESCR0 0x000003ae 468 #define MSR_P4_SAAT_ESCR1 0x000003af 469 #define MSR_P4_SSU_ESCR0 0x000003be 470 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 471 472 #define MSR_P4_TBPU_ESCR0 0x000003c2 473 #define MSR_P4_TBPU_ESCR1 0x000003c3 474 #define MSR_P4_TC_ESCR0 0x000003c4 475 #define MSR_P4_TC_ESCR1 0x000003c5 476 #define MSR_P4_U2L_ESCR0 0x000003b0 477 #define MSR_P4_U2L_ESCR1 0x000003b1 478 479 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 480 481 /* Intel Core-based CPU performance counters */ 482 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 483 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 484 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 485 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 486 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 487 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 488 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 489 490 /* AMD Performance Counter Global Status and Control MSRs */ 491 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 492 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 493 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 494 495 /* Geode defined MSRs */ 496 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 497 498 /* Intel VT MSRs */ 499 #define MSR_IA32_VMX_BASIC 0x00000480 500 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 501 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 502 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 503 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 504 #define MSR_IA32_VMX_MISC 0x00000485 505 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 506 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 507 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 508 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 509 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 510 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 511 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 512 #define MSR_IA32_VMX_TRUE_PIN 0x0000048d 513 #define MSR_IA32_VMX_TRUE_PROC 0x0000048e 514 #define MSR_IA32_VMX_TRUE_EXIT 0x0000048f 515 #define MSR_IA32_VMX_TRUE_ENTRY 0x00000490 516 517 /* MSR_IA32_VMX_MISC bits */ 518 #define MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 519 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 520 521 #define MSR_IA32_TSCDEADLINE 0x000006e0 522 523 /* AMD-V MSRs */ 524 525 #define MSR_AMD64_TSC_RATIO 0xc0000104 526 #define MSR_VM_CR 0xc0010114 527 #define MSR_VM_IGNNE 0xc0010115 528 #define MSR_VM_HSAVE_PA 0xc0010117 529 530 #define MSR_SEV_STATUS 0xc0010131 531 #define SEV_STATUS_SEV_ENABLED BIT(0) 532 #define SEV_STATUS_SEV_ES_ENABLED BIT(1) 533 534 #define MSR_SEV_ES_GHCB 0xc0010130 535 536 #endif /* _X86_MSR_H_ */ 537