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Searched refs:MSR_IA32_PEBS_ENABLE (Results 1 – 10 of 10) sorted by relevance

/linux/arch/x86/kvm/vmx/
H A Dpmu_intel.c195 case MSR_IA32_PEBS_ENABLE: in intel_is_valid_msr()
350 case MSR_IA32_PEBS_ENABLE: in intel_pmu_get_msr()
399 case MSR_IA32_PEBS_ENABLE: in intel_pmu_set_msr()
H A Dvmx.c1013 case MSR_IA32_PEBS_ENABLE: in add_atomic_switch_msr()
1019 wrmsrq(MSR_IA32_PEBS_ENABLE, 0); in add_atomic_switch_msr()
/linux/arch/x86/xen/
H A Dpmu.c159 case MSR_IA32_PEBS_ENABLE: in is_intel_pmu_msr()
/linux/arch/x86/include/asm/
H A Dmsr-index.h310 #define MSR_IA32_PEBS_ENABLE 0x000003f1 macro
/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h310 #define MSR_IA32_PEBS_ENABLE 0x000003f1 macro
/linux/arch/x86/events/intel/
H A Dds.c1624 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1634 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
H A Dp4.c49 * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
901 * (void)wrmsrq_safe(MSR_IA32_PEBS_ENABLE, 0); in p4_pmu_disable_pebs()
948 (void)wrmsrq_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); in p4_pmu_enable_pebs()
H A Dcore.c2415 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; in intel_pmu_nhm_workaround()
3204 * MSR_IA32_PEBS_ENABLE is not updated. Because the in handle_pmi_common()
3209 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in handle_pmi_common()
4601 .msr = MSR_IA32_PEBS_ENABLE, in intel_guest_get_msrs()
4627 .msr = MSR_IA32_PEBS_ENABLE, in intel_guest_get_msrs()
/linux/arch/x86/events/
H A Dcore.c1572 rdmsrq(MSR_IA32_PEBS_ENABLE, pebs); in perf_event_print_debug()
/linux/arch/x86/kvm/
H A Dx86.c346 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,