1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_BO_TYPES_H_ 7 #define _XE_BO_TYPES_H_ 8 9 #include <linux/iosys-map.h> 10 11 #include <drm/drm_gpusvm.h> 12 #include <drm/ttm/ttm_bo.h> 13 #include <drm/ttm/ttm_device.h> 14 #include <drm/ttm/ttm_placement.h> 15 16 #include "xe_device_types.h" 17 #include "xe_ggtt_types.h" 18 19 struct xe_device; 20 struct xe_vm; 21 22 #define XE_BO_MAX_PLACEMENTS 3 23 24 /* TODO: To be selected with VM_MADVISE */ 25 #define XE_BO_PRIORITY_NORMAL 1 26 27 /** @xe_bo: XE buffer object */ 28 struct xe_bo { 29 /** @ttm: TTM base buffer object */ 30 struct ttm_buffer_object ttm; 31 /** @size: Size of this buffer object */ 32 size_t size; 33 /** @flags: flags for this buffer object */ 34 u32 flags; 35 /** @vm: VM this BO is attached to, for extobj this will be NULL */ 36 struct xe_vm *vm; 37 /** @tile: Tile this BO is attached to (kernel BO only) */ 38 struct xe_tile *tile; 39 /** @placements: valid placements for this BO */ 40 struct ttm_place placements[XE_BO_MAX_PLACEMENTS]; 41 /** @placement: current placement for this BO */ 42 struct ttm_placement placement; 43 /** @ggtt_node: Array of GGTT nodes if this BO is mapped in the GGTTs */ 44 struct xe_ggtt_node *ggtt_node[XE_MAX_TILES_PER_DEVICE]; 45 /** @vmap: iosys map of this buffer */ 46 struct iosys_map vmap; 47 /** @ttm_kmap: TTM bo kmap object for internal use only. Keep off. */ 48 struct ttm_bo_kmap_obj kmap; 49 /** @pinned_link: link to present / evicted list of pinned BO */ 50 struct list_head pinned_link; 51 #ifdef CONFIG_PROC_FS 52 /** 53 * @client: @xe_drm_client which created the bo 54 */ 55 struct xe_drm_client *client; 56 /** 57 * @client_link: Link into @xe_drm_client.objects_list 58 */ 59 struct list_head client_link; 60 #endif 61 /** 62 * @pxp_key_instance: PXP key instance this BO was created against. A 63 * 0 in this variable indicates that the BO does not use PXP encryption. 64 */ 65 u32 pxp_key_instance; 66 67 /** @freed: List node for delayed put. */ 68 struct llist_node freed; 69 /** @update_index: Update index if PT BO */ 70 int update_index; 71 /** @created: Whether the bo has passed initial creation */ 72 bool created; 73 74 /** @ccs_cleared */ 75 bool ccs_cleared; 76 77 /** 78 * @cpu_caching: CPU caching mode. Currently only used for userspace 79 * objects. Exceptions are system memory on DGFX, which is always 80 * WB. 81 */ 82 u16 cpu_caching; 83 84 /** @devmem_allocation: SVM device memory allocation */ 85 struct drm_gpusvm_devmem devmem_allocation; 86 87 /** @vram_userfault_link: Link into @mem_access.vram_userfault.list */ 88 struct list_head vram_userfault_link; 89 90 /** @min_align: minimum alignment needed for this BO if different 91 * from default 92 */ 93 u64 min_align; 94 }; 95 96 #endif 97