1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <linux/bitfield.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <net/ip.h>
14
15 #define WX_NCSI_SUP 0x8000
16 #define WX_NCSI_MASK 0x8000
17 #define WX_WOL_SUP 0x4000
18 #define WX_WOL_MASK 0x4000
19
20 /* MSI-X capability fields masks */
21 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
22 #define WX_PCI_LINK_STATUS 0xB2
23
24 /**************** Global Registers ****************************/
25 /* chip control Registers */
26 #define WX_MIS_PWR 0x10000
27 #define WX_MIS_RST 0x1000C
28 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
29 #define WX_MIS_RST_SW_RST BIT(0)
30 #define WX_MIS_ST 0x10028
31 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
32 #define WX_MIS_SWSM 0x1002C
33 #define WX_MIS_SWSM_SMBI BIT(0)
34 #define WX_MIS_RST_ST 0x10030
35 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
36 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
37
38 /* FMGR Registers */
39 #define WX_SPI_CMD 0x10104
40 #define WX_SPI_CMD_READ_DWORD 0x1
41 #define WX_SPI_CLK_DIV 0x3
42 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
43 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
44 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
45 #define WX_SPI_DATA 0x10108
46 #define WX_SPI_DATA_BYPASS BIT(31)
47 #define WX_SPI_DATA_OP_DONE BIT(0)
48 #define WX_SPI_STATUS 0x1010C
49 #define WX_SPI_STATUS_OPDONE BIT(0)
50 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
51 #define WX_SPI_ILDR_STATUS 0x10120
52
53 /* Sensors for PVT(Process Voltage Temperature) */
54 #define WX_TS_EN 0x10304
55 #define WX_TS_EN_ENA BIT(0)
56 #define WX_TS_ALARM_THRE 0x1030C
57 #define WX_TS_DALARM_THRE 0x10310
58 #define WX_TS_INT_EN 0x10314
59 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
60 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
61 #define WX_TS_ALARM_ST 0x10318
62 #define WX_TS_ALARM_ST_DALARM BIT(1)
63 #define WX_TS_ALARM_ST_ALARM BIT(0)
64
65 /* statistic */
66 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
67 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
68 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
69 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
70 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
71 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
72 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
73 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
74 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
75 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
76 #define WX_MAC_LXONOFFRXC 0x11E0C
77
78 /*********************** Receive DMA registers **************************/
79 #define WX_RDM_DRP_PKT 0x12500
80 #define WX_RDM_PKT_CNT 0x12504
81 #define WX_RDM_BYTE_CNT_LSB 0x12508
82 #define WX_RDM_BMC2OS_CNT 0x12510
83
84 /************************* Port Registers ************************************/
85 /* port cfg Registers */
86 #define WX_CFG_PORT_CTL 0x14400
87 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
88 #define WX_CFG_PORT_CTL_QINQ BIT(2)
89 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
90 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
91 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
92
93
94 /* GPIO Registers */
95 #define WX_GPIO_DR 0x14800
96 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
97 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
98 #define WX_GPIO_DDR 0x14804
99 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
100 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
101 #define WX_GPIO_CTL 0x14808
102 #define WX_GPIO_INTEN 0x14830
103 #define WX_GPIO_INTEN_0 BIT(0)
104 #define WX_GPIO_INTEN_1 BIT(1)
105 #define WX_GPIO_INTMASK 0x14834
106 #define WX_GPIO_INTTYPE_LEVEL 0x14838
107 #define WX_GPIO_POLARITY 0x1483C
108 #define WX_GPIO_INTSTATUS 0x14844
109 #define WX_GPIO_EOI 0x1484C
110 #define WX_GPIO_EXT 0x14850
111
112 /*********************** Transmit DMA registers **************************/
113 /* transmit global control */
114 #define WX_TDM_CTL 0x18000
115 /* TDM CTL BIT */
116 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
117 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
118 #define WX_TDM_RP_IDX 0x1820C
119 #define WX_TDM_PKT_CNT 0x18308
120 #define WX_TDM_BYTE_CNT_LSB 0x1830C
121 #define WX_TDM_OS2BMC_CNT 0x18314
122 #define WX_TDM_RP_RATE 0x18404
123
124 /***************************** RDB registers *********************************/
125 /* receive packet buffer */
126 #define WX_RDB_PB_CTL 0x19000
127 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
128 #define WX_RDB_PB_CTL_DISABLED BIT(0)
129 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
130 #define WX_RDB_PB_SZ_SHIFT 10
131 /* statistic */
132 #define WX_RDB_PFCMACDAL 0x19210
133 #define WX_RDB_PFCMACDAH 0x19214
134 #define WX_RDB_LXOFFTXC 0x19218
135 #define WX_RDB_LXONTXC 0x1921C
136 /* Flow Control Registers */
137 #define WX_RDB_RFCV 0x19200
138 #define WX_RDB_RFCL 0x19220
139 #define WX_RDB_RFCL_XONE BIT(31)
140 #define WX_RDB_RFCH 0x19260
141 #define WX_RDB_RFCH_XOFFE BIT(31)
142 #define WX_RDB_RFCRT 0x192A0
143 #define WX_RDB_RFCC 0x192A4
144 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
145 /* ring assignment */
146 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
147 #define WX_RDB_PL_CFG_L4HDR BIT(1)
148 #define WX_RDB_PL_CFG_L3HDR BIT(2)
149 #define WX_RDB_PL_CFG_L2HDR BIT(3)
150 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
151 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
152 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
153 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
154 #define WX_RDB_RA_CTL 0x194F4
155 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
156 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
157 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
158 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
159 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
160 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
161 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
162 #define WX_RDB_FDIR_MATCH 0x19558
163 #define WX_RDB_FDIR_MISS 0x1955C
164
165 /******************************* PSR Registers *******************************/
166 /* psr control */
167 #define WX_PSR_CTL 0x15000
168 /* Header split receive */
169 #define WX_PSR_CTL_SW_EN BIT(18)
170 #define WX_PSR_CTL_RSC_ACK BIT(17)
171 #define WX_PSR_CTL_RSC_DIS BIT(16)
172 #define WX_PSR_CTL_PCSD BIT(13)
173 #define WX_PSR_CTL_IPPCSE BIT(12)
174 #define WX_PSR_CTL_BAM BIT(10)
175 #define WX_PSR_CTL_UPE BIT(9)
176 #define WX_PSR_CTL_MPE BIT(8)
177 #define WX_PSR_CTL_MFE BIT(7)
178 #define WX_PSR_CTL_MO_SHIFT 5
179 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
180 #define WX_PSR_CTL_TPE BIT(4)
181 #define WX_PSR_MAX_SZ 0x15020
182 #define WX_PSR_VLAN_CTL 0x15088
183 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
184 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
185 /* EType Queue Filter */
186 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4))
187 #define WX_PSR_ETYPE_SWC_FILTER_1588 3
188 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31)
189 #define WX_PSR_ETYPE_SWC_1588 BIT(30)
190 /* 1588 */
191 #define WX_PSR_1588_MSG 0x15120
192 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)
193 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)
194 #define WX_PSR_1588_STMPL 0x151E8
195 #define WX_PSR_1588_STMPH 0x151A4
196 #define WX_PSR_1588_CTL 0x15188
197 #define WX_PSR_1588_CTL_ENABLED BIT(4)
198 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)
199 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)
200 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)
201 #define WX_PSR_1588_CTL_VALID BIT(0)
202 /* mcasst/ucast overflow tbl */
203 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
204 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
205
206 /* VM L2 contorl */
207 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
208 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
209 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
210 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
211 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
212 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
213 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
214 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
215
216 /* Management */
217 #define WX_PSR_MNG_FLEX_SEL 0x1582C
218 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
219 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
220 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
221 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
222 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
223 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
224 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
225
226 #define WX_PSR_WKUP_CTL 0x15B80
227 /* Wake Up Filter Control Bit */
228 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
229
230 /* vlan tbl */
231 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
232
233 /* mac switcher */
234 #define WX_PSR_MAC_SWC_AD_L 0x16200
235 #define WX_PSR_MAC_SWC_AD_H 0x16204
236 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
237 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
238 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
239 #define WX_PSR_MAC_SWC_VM_L 0x16208
240 #define WX_PSR_MAC_SWC_VM_H 0x1620C
241 #define WX_PSR_MAC_SWC_IDX 0x16210
242 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
243
244 /* vlan switch */
245 #define WX_PSR_VLAN_SWC 0x16220
246 #define WX_PSR_VLAN_SWC_VM_L 0x16224
247 #define WX_PSR_VLAN_SWC_VM_H 0x16228
248 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
249 /* VLAN pool filtering masks */
250 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
251 #define WX_PSR_VLAN_SWC_ENTRIES 64
252
253 /********************************* RSEC **************************************/
254 /* general rsec */
255 #define WX_RSC_CTL 0x17000
256 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
257 #define WX_RSC_CTL_CRC_STRIP BIT(2)
258 #define WX_RSC_CTL_RX_DIS BIT(1)
259 #define WX_RSC_ST 0x17004
260 #define WX_RSC_ST_RSEC_RDY BIT(0)
261
262 /****************************** TDB ******************************************/
263 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
264 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
265
266 /****************************** TSEC *****************************************/
267 /* Security Control Registers */
268 #define WX_TSC_CTL 0x1D000
269 #define WX_TSC_CTL_TX_DIS BIT(1)
270 #define WX_TSC_CTL_TSEC_DIS BIT(0)
271 #define WX_TSC_ST 0x1D004
272 #define WX_TSC_ST_SECTX_RDY BIT(0)
273 #define WX_TSC_BUF_AE 0x1D00C
274 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
275 /* 1588 */
276 #define WX_TSC_1588_CTL 0x11F00
277 #define WX_TSC_1588_CTL_ENABLED BIT(4)
278 #define WX_TSC_1588_CTL_VALID BIT(0)
279 #define WX_TSC_1588_STMPL 0x11F04
280 #define WX_TSC_1588_STMPH 0x11F08
281 #define WX_TSC_1588_SYSTIML 0x11F0C
282 #define WX_TSC_1588_SYSTIMH 0x11F10
283 #define WX_TSC_1588_INC 0x11F14
284 #define WX_TSC_1588_INT_ST 0x11F20
285 #define WX_TSC_1588_INT_ST_TT1 BIT(5)
286 #define WX_TSC_1588_INT_EN 0x11F24
287 #define WX_TSC_1588_INT_EN_TT1 BIT(5)
288 #define WX_TSC_1588_AUX_CTL 0x11F28
289 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8)
290 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2)
291 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1)
292 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0)
293 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */
294 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */
295 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */
296 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0)
297 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1)
298 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)
299 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1)
300 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5)
301
302 /************************************** MNG ********************************/
303 #define WX_MNG_SWFW_SYNC 0x1E008
304 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
305 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
306 #define WX_MNG_MBOX 0x1E100
307 #define WX_MNG_MBOX_CTL 0x1E044
308 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
309 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
310 #define WX_MNG_BMC2OS_CNT 0x1E090
311 #define WX_MNG_OS2BMC_CNT 0x1E094
312 #define WX_SW2FW_MBOX_CMD 0x1E0A0
313 #define WX_SW2FW_MBOX_CMD_VLD BIT(31)
314 #define WX_SW2FW_MBOX 0x1E200
315 #define WX_FW2SW_MBOX 0x1E300
316
317 /************************************* ETH MAC *****************************/
318 #define WX_MAC_TX_CFG 0x11000
319 #define WX_MAC_TX_CFG_TE BIT(0)
320 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
321 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
322 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
323 #define WX_MAC_RX_CFG 0x11004
324 #define WX_MAC_RX_CFG_RE BIT(0)
325 #define WX_MAC_RX_CFG_JE BIT(8)
326 #define WX_MAC_PKT_FLT 0x11008
327 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
328 #define WX_MAC_WDG_TIMEOUT 0x1100C
329 #define WX_MAC_RX_FLOW_CTRL 0x11090
330 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
331 /* MDIO Registers */
332 #define WX_MSCA 0x11200
333 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
334 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
335 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
336 #define WX_MSCC 0x11204
337 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
338
339 enum WX_MSCA_CMD_value {
340 WX_MSCA_CMD_RSV = 0,
341 WX_MSCA_CMD_WRITE,
342 WX_MSCA_CMD_POST_READ,
343 WX_MSCA_CMD_READ,
344 };
345
346 #define WX_MSCC_SADDR BIT(18)
347 #define WX_MSCC_BUSY BIT(22)
348 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
349 #define WX_MDIO_CLAUSE_SELECT 0x11220
350 #define WX_MMC_CONTROL 0x11800
351 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
352
353 /********************************* BAR registers ***************************/
354 /* Interrupt Registers */
355 #define WX_BME_CTL 0x12020
356 #define WX_PX_MISC_IC 0x100
357 #define WX_PX_MISC_ICS 0x104
358 #define WX_PX_MISC_IEN 0x108
359 #define WX_PX_INTA 0x110
360 #define WX_PX_GPIE 0x118
361 #define WX_PX_GPIE_MODEL BIT(0)
362 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
363 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
364 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
365 #define WX_PX_ISB_ADDR_L 0x160
366 #define WX_PX_ISB_ADDR_H 0x164
367 #define WX_PX_TRANSACTION_PENDING 0x168
368 #define WX_PX_ITRSEL 0x180
369 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
370 #define WX_PX_ITR_CNT_WDIS BIT(31)
371 #define WX_PX_MISC_IVAR 0x4FC
372 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
373
374 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
375 #define WX_7K_ITR 595
376 #define WX_12K_ITR 336
377 #define WX_20K_ITR 200
378 #define WX_SP_MAX_EITR 0x00000FF8U
379 #define WX_AML_MAX_EITR 0x00000FFFU
380 #define WX_EM_MAX_EITR 0x00007FFCU
381
382 /* transmit DMA Registers */
383 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
384 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
385 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
386 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
387 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
388 /* Transmit Config masks */
389 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
390 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
391 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
392 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
393 #define WX_PX_TR_CFG_THRE_SHIFT 8
394
395 /* Receive DMA Registers */
396 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
397 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
398 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
399 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
400 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
401 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
402 /* PX_RR_CFG bit definitions */
403 #define WX_PX_RR_CFG_VLAN BIT(31)
404 #define WX_PX_RR_CFG_DROP_EN BIT(30)
405 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
406 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
407 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
408 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
409 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
410 * + at bit 8 offset (<< 12)
411 * = (<< 6)
412 */
413 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
414 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
415 #define WX_PX_RR_CFG_RR_EN BIT(0)
416
417 /* Number of 80 microseconds we wait for PCI Express master disable */
418 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
419
420 /****************** Manageablility Host Interface defines ********************/
421 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
422 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
423 #define WX_HIC_HDR_INDEX_MAX 255
424
425 #define FW_READ_SHADOW_RAM_CMD 0x31
426 #define FW_READ_SHADOW_RAM_LEN 0x6
427 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
428 #define FW_NVM_DATA_OFFSET 3
429 #define FW_MAX_READ_BUFFER_SIZE 244
430 #define FW_RESET_CMD 0xDF
431 #define FW_RESET_LEN 0x2
432 #define FW_CEM_HDR_LEN 0x4
433 #define FW_CEM_CMD_RESERVED 0X0
434 #define FW_CEM_MAX_RETRIES 3
435 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
436 #define FW_PPS_SET_CMD 0xF6
437 #define FW_PPS_SET_LEN 0x14
438
439 #define WX_SW_REGION_PTR 0x1C
440
441 #define WX_MAC_STATE_DEFAULT 0x1
442 #define WX_MAC_STATE_MODIFIED 0x2
443 #define WX_MAC_STATE_IN_USE 0x4
444
445 /* BitTimes (BT) conversion */
446 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
447 #define WX_B2BT(BT) ((BT) * 8)
448
449 /* Calculate Delay to respond to PFC */
450 #define WX_PFC_D 672
451 /* Calculate Cable Delay */
452 #define WX_CABLE_DC 5556 /* Delay Copper */
453 /* Calculate Delay incurred from higher layer */
454 #define WX_HD 6144
455
456 /* Calculate Interface Delay */
457 #define WX_PHY_D 12800
458 #define WX_MAC_D 4096
459 #define WX_XAUI_D (2 * 1024)
460 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
461 /* Calculate PCI Bus delay for low thresholds */
462 #define WX_PCI_DELAY 10000
463
464 /* Calculate delay value in bit times */
465 #define WX_DV(_max_frame_link, _max_frame_tc) \
466 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
467 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
468 2 * WX_B2BT(_max_frame_tc))
469
470 /* Calculate low threshold delay values */
471 #define WX_LOW_DV(_max_frame_tc) \
472 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
473
474 /* flow control */
475 #define WX_DEFAULT_FCPAUSE 0xFFFF
476
477 #define WX_MAX_RXD 8192
478 #define WX_MAX_TXD 8192
479 #define WX_MIN_RXD 128
480 #define WX_MIN_TXD 128
481
482 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
483 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
484 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
485
486 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
487 #define VMDQ_P(p) p
488
489 /* Supported Rx Buffer Sizes */
490 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
491 #define WX_RXBUFFER_2K 2048
492 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
493
494 #if MAX_SKB_FRAGS < 8
495 #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
496 #else
497 #define WX_RX_BUFSZ WX_RXBUFFER_2K
498 #endif
499
500 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
501
502 #define WX_MAX_DATA_PER_TXD BIT(14)
503 /* Tx Descriptors needed, worst case */
504 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
505 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
506
507 #define WX_CFG_PORT_ST 0x14404
508
509 /******************* Receive Descriptor bit definitions **********************/
510 #define WX_RXD_STAT_DD BIT(0) /* Done */
511 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
512 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
513 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
514 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
515 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
516 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
517 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */
518
519 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
520 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
521 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
522 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
523
524 /* RSS Hash results */
525 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
526 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
527 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
528 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
529 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
530 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
531 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
532
533 #define WX_RSS_L4_TYPES_MASK \
534 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
535 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
536 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
537 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
538 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
539 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
540 /* TUN */
541 #define WX_PTYPE_TUN_IPV4 0x80
542 #define WX_PTYPE_TUN_IPV6 0xC0
543
544 /* PKT for TUN */
545 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
546 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
547 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
548 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
549 /* PKT for !TUN */
550 #define WX_PTYPE_PKT_MAC 0x10
551 #define WX_PTYPE_PKT_IP 0x20
552
553 /* TYP for PKT=mac */
554 #define WX_PTYPE_TYP_MAC 0x01
555 /* TYP for PKT=ip */
556 #define WX_PTYPE_PKT_IPV6 0x08
557 #define WX_PTYPE_TYP_IPFRAG 0x01
558 #define WX_PTYPE_TYP_IP 0x02
559 #define WX_PTYPE_TYP_UDP 0x03
560 #define WX_PTYPE_TYP_TCP 0x04
561 #define WX_PTYPE_TYP_SCTP 0x05
562
563 /* Packet type non-ip values */
564 enum wx_l2_ptypes {
565 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
566 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
567
568 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
569 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
570 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
571 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
572 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
573 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
574 WX_PTYPE_TYP_IPFRAG),
575 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
576 WX_PTYPE_TYP_IP),
577 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
578 WX_PTYPE_TYP_UDP),
579 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
580 WX_PTYPE_TYP_TCP),
581 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
582 WX_PTYPE_TYP_SCTP),
583
584 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
585 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
586 };
587
588 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
589 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
590
591 #define WX_RXD_PKTTYPE(_rxd) \
592 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
593 /*********************** Transmit Descriptor Config Masks ****************/
594 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
595 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
596 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
597 #define WX_TXD_EOP BIT(24) /* End of Packet */
598 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
599 #define WX_TXD_RS BIT(27) /* Report Status */
600
601 /*********************** Adv Transmit Descriptor Config Masks ****************/
602 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
603 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
604 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
605 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
606 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
607 #define WX_TXD_CC BIT(7) /* Check Context */
608 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
609 #define WX_TXD_L4CS BIT(9)
610 #define WX_TXD_IIPCS BIT(10)
611 #define WX_TXD_EIPCS BIT(11)
612 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
613 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
614 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
615
616 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
617 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
618
619 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
620 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
621 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
622 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
623 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
624
625 enum wx_tx_flags {
626 /* cmd_type flags */
627 WX_TX_FLAGS_HW_VLAN = 0x01,
628 WX_TX_FLAGS_TSO = 0x02,
629 WX_TX_FLAGS_TSTAMP = 0x04,
630
631 /* olinfo flags */
632 WX_TX_FLAGS_CC = 0x08,
633 WX_TX_FLAGS_IPV4 = 0x10,
634 WX_TX_FLAGS_CSUM = 0x20,
635 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
636 WX_TX_FLAGS_LINKSEC = 0x200,
637 WX_TX_FLAGS_IPSEC = 0x400,
638
639 /* software defined flags */
640 WX_TX_FLAGS_SW_VLAN = 0x40,
641 };
642
643 /* VLAN info */
644 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
645 #define WX_TX_FLAGS_VLAN_SHIFT 16
646
647 /* wx_dec_ptype.mac: outer mac */
648 enum wx_dec_ptype_mac {
649 WX_DEC_PTYPE_MAC_IP = 0,
650 WX_DEC_PTYPE_MAC_L2 = 2,
651 WX_DEC_PTYPE_MAC_FCOE = 3,
652 };
653
654 /* wx_dec_ptype.[e]ip: outer&encaped ip */
655 #define WX_DEC_PTYPE_IP_FRAG 0x4
656 enum wx_dec_ptype_ip {
657 WX_DEC_PTYPE_IP_NONE = 0,
658 WX_DEC_PTYPE_IP_IPV4 = 1,
659 WX_DEC_PTYPE_IP_IPV6 = 2,
660 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
661 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
662 };
663
664 /* wx_dec_ptype.etype: encaped type */
665 enum wx_dec_ptype_etype {
666 WX_DEC_PTYPE_ETYPE_NONE = 0,
667 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
668 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
669 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
670 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
671 };
672
673 /* wx_dec_ptype.proto: payload proto */
674 enum wx_dec_ptype_prot {
675 WX_DEC_PTYPE_PROT_NONE = 0,
676 WX_DEC_PTYPE_PROT_UDP = 1,
677 WX_DEC_PTYPE_PROT_TCP = 2,
678 WX_DEC_PTYPE_PROT_SCTP = 3,
679 WX_DEC_PTYPE_PROT_ICMP = 4,
680 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
681 };
682
683 /* wx_dec_ptype.layer: payload layer */
684 enum wx_dec_ptype_layer {
685 WX_DEC_PTYPE_LAYER_NONE = 0,
686 WX_DEC_PTYPE_LAYER_PAY2 = 1,
687 WX_DEC_PTYPE_LAYER_PAY3 = 2,
688 WX_DEC_PTYPE_LAYER_PAY4 = 3,
689 };
690
691 struct wx_dec_ptype {
692 u32 known:1;
693 u32 mac:2; /* outer mac */
694 u32 ip:3; /* outer ip*/
695 u32 etype:3; /* encaped type */
696 u32 eip:3; /* encaped ip */
697 u32 prot:4; /* payload proto */
698 u32 layer:3; /* payload layer */
699 };
700
701 /* macro to make the table lines short */
702 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
703 {1, \
704 WX_DEC_PTYPE_MAC_##mac, /* mac */\
705 WX_DEC_PTYPE_IP_##ip, /* ip */ \
706 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
707 WX_DEC_PTYPE_IP_##eip, /* eip */\
708 WX_DEC_PTYPE_PROT_##proto, /* proto */\
709 WX_DEC_PTYPE_LAYER_##layer /* layer */}
710
711 /* Host Interface Command Structures */
712 struct wx_hic_hdr {
713 u8 cmd;
714 u8 buf_len;
715 union {
716 u8 cmd_resv;
717 u8 ret_status;
718 } cmd_or_resp;
719 union {
720 u8 checksum;
721 u8 index;
722 };
723 };
724
725 struct wx_hic_hdr2_req {
726 u8 cmd;
727 u8 buf_lenh;
728 u8 buf_lenl;
729 union {
730 u8 checksum;
731 u8 index;
732 };
733 };
734
735 struct wx_hic_hdr2_rsp {
736 u8 cmd;
737 u8 buf_lenl;
738 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
739 union {
740 u8 checksum;
741 u8 index;
742 };
743 };
744
745 union wx_hic_hdr2 {
746 struct wx_hic_hdr2_req req;
747 struct wx_hic_hdr2_rsp rsp;
748 };
749
750 /* These need to be dword aligned */
751 struct wx_hic_read_shadow_ram {
752 union wx_hic_hdr2 hdr;
753 u32 address;
754 u16 length;
755 u16 pad2;
756 u16 data;
757 u16 pad3;
758 };
759
760 struct wx_hic_reset {
761 struct wx_hic_hdr hdr;
762 u16 lan_id;
763 u16 reset_type;
764 };
765
766 struct wx_hic_set_pps {
767 struct wx_hic_hdr hdr;
768 u8 lan_id;
769 u8 enable;
770 u16 pad2;
771 u64 nsec;
772 u64 cycles;
773 };
774
775 /* Bus parameters */
776 struct wx_bus_info {
777 u8 func;
778 u16 device;
779 };
780
781 struct wx_thermal_sensor_data {
782 s16 temp;
783 s16 alarm_thresh;
784 s16 dalarm_thresh;
785 };
786
787 enum wx_mac_type {
788 wx_mac_unknown = 0,
789 wx_mac_sp,
790 wx_mac_em,
791 wx_mac_aml,
792 };
793
794 enum sp_media_type {
795 sp_media_unknown = 0,
796 sp_media_fiber,
797 sp_media_copper,
798 sp_media_backplane
799 };
800
801 enum em_mac_type {
802 em_mac_type_unknown = 0,
803 em_mac_type_mdi,
804 em_mac_type_rgmii
805 };
806
807 struct wx_mac_info {
808 enum wx_mac_type type;
809 bool set_lben;
810 u8 addr[ETH_ALEN];
811 u8 perm_addr[ETH_ALEN];
812 u32 mta_shadow[128];
813 s32 mc_filter_type;
814 u32 mcft_size;
815 u32 vft_shadow[128];
816 u32 vft_size;
817 u32 num_rar_entries;
818 u32 rx_pb_size;
819 u32 tx_pb_size;
820 u32 max_tx_queues;
821 u32 max_rx_queues;
822
823 u16 max_msix_vectors;
824 struct wx_thermal_sensor_data sensor;
825 };
826
827 enum wx_eeprom_type {
828 wx_eeprom_uninitialized = 0,
829 wx_eeprom_spi,
830 wx_flash,
831 wx_eeprom_none /* No NVM support */
832 };
833
834 struct wx_eeprom_info {
835 enum wx_eeprom_type type;
836 u32 semaphore_delay;
837 u16 word_size;
838 u16 sw_region_offset;
839 };
840
841 struct wx_addr_filter_info {
842 u32 num_mc_addrs;
843 u32 mta_in_use;
844 bool user_set_promisc;
845 };
846
847 struct wx_mac_addr {
848 u8 addr[ETH_ALEN];
849 u16 state; /* bitmask */
850 u64 pools;
851 };
852
853 enum wx_reset_type {
854 WX_LAN_RESET = 0,
855 WX_SW_RESET,
856 WX_GLOBAL_RESET
857 };
858
859 struct wx_cb {
860 dma_addr_t dma;
861 u16 append_cnt; /* number of skb's appended */
862 bool page_released;
863 bool dma_released;
864 };
865
866 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
867
868 /* Transmit Descriptor */
869 union wx_tx_desc {
870 struct {
871 __le64 buffer_addr; /* Address of descriptor's data buf */
872 __le32 cmd_type_len;
873 __le32 olinfo_status;
874 } read;
875 struct {
876 __le64 rsvd; /* Reserved */
877 __le32 nxtseq_seed;
878 __le32 status;
879 } wb;
880 };
881
882 /* Receive Descriptor */
883 union wx_rx_desc {
884 struct {
885 __le64 pkt_addr; /* Packet buffer address */
886 __le64 hdr_addr; /* Header buffer address */
887 } read;
888 struct {
889 struct {
890 union {
891 __le32 data;
892 struct {
893 __le16 pkt_info; /* RSS, Pkt type */
894 __le16 hdr_info; /* Splithdr, hdrlen */
895 } hs_rss;
896 } lo_dword;
897 union {
898 __le32 rss; /* RSS Hash */
899 struct {
900 __le16 ip_id; /* IP id */
901 __le16 csum; /* Packet Checksum */
902 } csum_ip;
903 } hi_dword;
904 } lower;
905 struct {
906 __le32 status_error; /* ext status/error */
907 __le16 length; /* Packet length */
908 __le16 vlan; /* VLAN tag */
909 } upper;
910 } wb; /* writeback */
911 };
912
913 struct wx_tx_context_desc {
914 __le32 vlan_macip_lens;
915 __le32 seqnum_seed;
916 __le32 type_tucmd_mlhl;
917 __le32 mss_l4len_idx;
918 };
919
920 /* if _flag is in _input, return _result */
921 #define WX_SET_FLAG(_input, _flag, _result) \
922 (((_flag) <= (_result)) ? \
923 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
924 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
925
926 #define WX_RX_DESC(R, i) \
927 (&(((union wx_rx_desc *)((R)->desc))[i]))
928 #define WX_TX_DESC(R, i) \
929 (&(((union wx_tx_desc *)((R)->desc))[i]))
930 #define WX_TX_CTXTDESC(R, i) \
931 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
932
933 /* wrapper around a pointer to a socket buffer,
934 * so a DMA handle can be stored along with the buffer
935 */
936 struct wx_tx_buffer {
937 union wx_tx_desc *next_to_watch;
938 unsigned long time_stamp;
939 struct sk_buff *skb;
940 unsigned int bytecount;
941 unsigned short gso_segs;
942 DEFINE_DMA_UNMAP_ADDR(dma);
943 DEFINE_DMA_UNMAP_LEN(len);
944 __be16 protocol;
945 u32 tx_flags;
946 };
947
948 struct wx_rx_buffer {
949 struct sk_buff *skb;
950 dma_addr_t dma;
951 dma_addr_t page_dma;
952 struct page *page;
953 unsigned int page_offset;
954 };
955
956 struct wx_queue_stats {
957 u64 packets;
958 u64 bytes;
959 };
960
961 struct wx_tx_queue_stats {
962 u64 restart_queue;
963 u64 tx_busy;
964 };
965
966 struct wx_rx_queue_stats {
967 u64 non_eop_descs;
968 u64 csum_good_cnt;
969 u64 csum_err;
970 u64 alloc_rx_buff_failed;
971 };
972
973 /* iterator for handling rings in ring container */
974 #define wx_for_each_ring(posm, headm) \
975 for (posm = (headm).ring; posm; posm = posm->next)
976
977 struct wx_ring_container {
978 struct wx_ring *ring; /* pointer to linked list of rings */
979 unsigned int total_bytes; /* total bytes processed this int */
980 unsigned int total_packets; /* total packets processed this int */
981 u8 count; /* total number of rings in vector */
982 u8 itr; /* current ITR setting for ring */
983 };
984 struct wx_ring {
985 struct wx_ring *next; /* pointer to next ring in q_vector */
986 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
987 struct net_device *netdev; /* netdev ring belongs to */
988 struct device *dev; /* device for DMA mapping */
989 struct page_pool *page_pool;
990 void *desc; /* descriptor ring memory */
991 union {
992 struct wx_tx_buffer *tx_buffer_info;
993 struct wx_rx_buffer *rx_buffer_info;
994 };
995 u8 __iomem *tail;
996 dma_addr_t dma; /* phys. address of descriptor ring */
997 unsigned int size; /* length in bytes */
998
999 u16 count; /* amount of descriptors */
1000 unsigned long last_rx_timestamp;
1001
1002 u8 queue_index; /* needed for multiqueue queue management */
1003 u8 reg_idx; /* holds the special value that gets
1004 * the hardware register offset
1005 * associated with this ring, which is
1006 * different for DCB and RSS modes
1007 */
1008 u16 next_to_use;
1009 u16 next_to_clean;
1010 union {
1011 u16 next_to_alloc;
1012 struct {
1013 u8 atr_sample_rate;
1014 u8 atr_count;
1015 };
1016 };
1017
1018 struct wx_queue_stats stats;
1019 struct u64_stats_sync syncp;
1020 union {
1021 struct wx_tx_queue_stats tx_stats;
1022 struct wx_rx_queue_stats rx_stats;
1023 };
1024 } ____cacheline_internodealigned_in_smp;
1025
1026 struct wx_q_vector {
1027 struct wx *wx;
1028 int cpu; /* CPU for DCA */
1029 int numa_node;
1030 u16 v_idx; /* index of q_vector within array, also used for
1031 * finding the bit in EICR and friends that
1032 * represents the vector for this ring
1033 */
1034 u16 itr; /* Interrupt throttle rate written to EITR */
1035 struct wx_ring_container rx, tx;
1036 struct napi_struct napi;
1037 struct rcu_head rcu; /* to avoid race with update stats on free */
1038
1039 char name[IFNAMSIZ + 17];
1040
1041 /* for dynamic allocation of rings associated with this q_vector */
1042 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
1043 };
1044
1045 struct wx_ring_feature {
1046 u16 limit; /* upper limit on feature indices */
1047 u16 indices; /* current value of indices */
1048 u16 mask; /* Mask used for feature to ring mapping */
1049 u16 offset; /* offset to start of feature */
1050 };
1051
1052 enum wx_ring_f_enum {
1053 RING_F_NONE = 0,
1054 RING_F_RSS,
1055 RING_F_FDIR,
1056 RING_F_ARRAY_SIZE /* must be last in enum set */
1057 };
1058
1059 enum wx_isb_idx {
1060 WX_ISB_HEADER,
1061 WX_ISB_MISC,
1062 WX_ISB_VEC0,
1063 WX_ISB_VEC1,
1064 WX_ISB_MAX
1065 };
1066
1067 struct wx_fc_info {
1068 u32 high_water; /* Flow Ctrl High-water */
1069 u32 low_water; /* Flow Ctrl Low-water */
1070 };
1071
1072 /* Statistics counters collected by the MAC */
1073 struct wx_hw_stats {
1074 u64 gprc;
1075 u64 gptc;
1076 u64 gorc;
1077 u64 gotc;
1078 u64 tpr;
1079 u64 tpt;
1080 u64 bprc;
1081 u64 bptc;
1082 u64 mprc;
1083 u64 mptc;
1084 u64 roc;
1085 u64 ruc;
1086 u64 lxonoffrxc;
1087 u64 lxontxc;
1088 u64 lxofftxc;
1089 u64 o2bgptc;
1090 u64 b2ospc;
1091 u64 o2bspc;
1092 u64 b2ogprc;
1093 u64 rdmdrop;
1094 u64 crcerrs;
1095 u64 rlec;
1096 u64 qmprc;
1097 u64 fdirmatch;
1098 u64 fdirmiss;
1099 };
1100
1101 enum wx_state {
1102 WX_STATE_RESETTING,
1103 WX_STATE_SWFW_BUSY,
1104 WX_STATE_PTP_RUNNING,
1105 WX_STATE_PTP_TX_IN_PROGRESS,
1106 WX_STATE_NBITS /* must be last */
1107 };
1108
1109 enum wx_pf_flags {
1110 WX_FLAG_SWFW_RING,
1111 WX_FLAG_FDIR_CAPABLE,
1112 WX_FLAG_FDIR_HASH,
1113 WX_FLAG_FDIR_PERFECT,
1114 WX_FLAG_RSC_CAPABLE,
1115 WX_FLAG_RX_HWTSTAMP_ENABLED,
1116 WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
1117 WX_FLAG_PTP_PPS_ENABLED,
1118 WX_PF_FLAGS_NBITS /* must be last */
1119 };
1120
1121 struct wx {
1122 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1123 DECLARE_BITMAP(state, WX_STATE_NBITS);
1124 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1125
1126 void *priv;
1127 u8 __iomem *hw_addr;
1128 struct pci_dev *pdev;
1129 struct net_device *netdev;
1130 struct wx_bus_info bus;
1131 struct wx_mac_info mac;
1132 enum em_mac_type mac_type;
1133 enum sp_media_type media_type;
1134 struct wx_eeprom_info eeprom;
1135 struct wx_addr_filter_info addr_ctrl;
1136 struct wx_fc_info fc;
1137 struct wx_mac_addr *mac_table;
1138 u16 device_id;
1139 u16 vendor_id;
1140 u16 subsystem_device_id;
1141 u16 subsystem_vendor_id;
1142 u8 revision_id;
1143 u16 oem_ssid;
1144 u16 oem_svid;
1145 u16 msg_enable;
1146 bool adapter_stopped;
1147 u16 tpid[8];
1148 char eeprom_id[32];
1149 char *driver_name;
1150 enum wx_reset_type reset_type;
1151 u8 swfw_index;
1152
1153 /* PHY stuff */
1154 unsigned int link;
1155 int speed;
1156 int duplex;
1157 struct phy_device *phydev;
1158 struct phylink *phylink;
1159 struct phylink_config phylink_config;
1160
1161 bool wol_hw_supported;
1162 bool ncsi_enabled;
1163 bool gpio_ctrl;
1164 raw_spinlock_t gpio_lock;
1165
1166 /* Tx fast path data */
1167 int num_tx_queues;
1168 u16 tx_itr_setting;
1169 u16 tx_work_limit;
1170
1171 /* Rx fast path data */
1172 int num_rx_queues;
1173 u16 rx_itr_setting;
1174 u16 rx_work_limit;
1175
1176 int num_q_vectors; /* current number of q_vectors for device */
1177 int max_q_vectors; /* upper limit of q_vectors for device */
1178
1179 u32 tx_ring_count;
1180 u32 rx_ring_count;
1181
1182 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1183 struct wx_ring *rx_ring[64];
1184 struct wx_q_vector *q_vector[64];
1185
1186 unsigned int queues_per_pool;
1187 struct msix_entry *msix_q_entries;
1188 struct msix_entry *msix_entry;
1189 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1190
1191 /* misc interrupt status block */
1192 dma_addr_t isb_dma;
1193 u32 *isb_mem;
1194 u32 isb_tag[WX_ISB_MAX];
1195 bool misc_irq_domain;
1196
1197 #define WX_MAX_RETA_ENTRIES 128
1198 #define WX_RSS_INDIR_TBL_MAX 64
1199 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1200 bool rss_enabled;
1201 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1202 u32 *rss_key;
1203 u32 wol;
1204
1205 u16 bd_number;
1206
1207 struct wx_hw_stats stats;
1208 u64 tx_busy;
1209 u64 non_eop_descs;
1210 u64 restart_queue;
1211 u64 hw_csum_rx_good;
1212 u64 hw_csum_rx_error;
1213 u64 alloc_rx_buff_failed;
1214
1215 u32 atr_sample_rate;
1216 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1217 void (*configure_fdir)(struct wx *wx);
1218 void (*do_reset)(struct net_device *netdev);
1219 int (*ptp_setup_sdp)(struct wx *wx);
1220
1221 bool pps_enabled;
1222 u64 pps_width;
1223 u64 pps_edge_start;
1224 u64 pps_edge_end;
1225 u64 sec_to_cc;
1226 u32 base_incval;
1227 u32 tx_hwtstamp_pkts;
1228 u32 tx_hwtstamp_timeouts;
1229 u32 tx_hwtstamp_skipped;
1230 u32 tx_hwtstamp_errors;
1231 u32 rx_hwtstamp_cleared;
1232 unsigned long last_overflow_check;
1233 unsigned long last_rx_ptp_check;
1234 unsigned long ptp_tx_start;
1235 seqlock_t hw_tc_lock; /* seqlock for ptp */
1236 struct cyclecounter hw_cc;
1237 struct timecounter hw_tc;
1238 struct ptp_clock *ptp_clock;
1239 struct ptp_clock_info ptp_caps;
1240 struct kernel_hwtstamp_config tstamp_config;
1241 struct sk_buff *ptp_tx_skb;
1242 };
1243
1244 #define WX_INTR_ALL (~0ULL)
1245 #define WX_INTR_Q(i) BIT((i) + 1)
1246
1247 /* register operations */
1248 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1249 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1250 #define rd32a(a, reg, offset) ( \
1251 rd32((a), (reg) + ((offset) << 2)))
1252 #define wr32a(a, reg, off, val) \
1253 wr32((a), (reg) + ((off) << 2), (val))
1254
1255 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1256 rd32m(struct wx *wx, u32 reg, u32 mask)
1257 {
1258 u32 val;
1259
1260 val = rd32(wx, reg);
1261 return val & mask;
1262 }
1263
1264 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1265 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1266 {
1267 u32 val;
1268
1269 val = rd32(wx, reg);
1270 val = ((val & ~mask) | (field & mask));
1271
1272 wr32(wx, reg, val);
1273 }
1274
1275 static inline u64
rd64(struct wx * wx,u32 reg)1276 rd64(struct wx *wx, u32 reg)
1277 {
1278 u64 lsb, msb;
1279
1280 lsb = rd32(wx, reg);
1281 msb = rd32(wx, reg + 4);
1282
1283 return (lsb | msb << 32);
1284 }
1285
1286 static inline u32
rd32ptp(struct wx * wx,u32 reg)1287 rd32ptp(struct wx *wx, u32 reg)
1288 {
1289 if (wx->mac.type == wx_mac_em)
1290 return rd32(wx, reg);
1291
1292 return rd32(wx, reg + 0xB500);
1293 }
1294
1295 static inline void
wr32ptp(struct wx * wx,u32 reg,u32 value)1296 wr32ptp(struct wx *wx, u32 reg, u32 value)
1297 {
1298 if (wx->mac.type == wx_mac_em)
1299 return wr32(wx, reg, value);
1300
1301 return wr32(wx, reg + 0xB500, value);
1302 }
1303
1304 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1305 * flushing memory, here use readl() to flush PCI read and write.
1306 */
1307 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1308
1309 #define wx_err(wx, fmt, arg...) \
1310 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1311
1312 #define wx_dbg(wx, fmt, arg...) \
1313 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1314
phylink_to_wx(struct phylink_config * config)1315 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1316 {
1317 return container_of(config, struct wx, phylink_config);
1318 }
1319
wx_set_state_reset(struct wx * wx)1320 static inline int wx_set_state_reset(struct wx *wx)
1321 {
1322 u8 timeout = 50;
1323
1324 while (test_and_set_bit(WX_STATE_RESETTING, wx->state)) {
1325 timeout--;
1326 if (!timeout)
1327 return -EBUSY;
1328
1329 usleep_range(1000, 2000);
1330 }
1331
1332 return 0;
1333 }
1334
1335 #endif /* _WX_TYPE_H_ */
1336