1 // SPDX-License-Identifier: GPL-2.0 AND MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include <kunit/test.h>
7 #include <kunit/visibility.h>
8
9 #include "tests/xe_mocs_test.h"
10 #include "tests/xe_pci_test.h"
11 #include "tests/xe_test.h"
12
13 #include "xe_pci.h"
14 #include "xe_gt.h"
15 #include "xe_mocs.h"
16 #include "xe_device.h"
17
18 struct live_mocs {
19 struct xe_mocs_info table;
20 };
21
live_mocs_init(struct live_mocs * arg,struct xe_gt * gt)22 static int live_mocs_init(struct live_mocs *arg, struct xe_gt *gt)
23 {
24 unsigned int flags;
25 struct kunit *test = xe_cur_kunit();
26
27 memset(arg, 0, sizeof(*arg));
28
29 flags = get_mocs_settings(gt_to_xe(gt), &arg->table);
30
31 kunit_info(test, "table size %d", arg->table.size);
32 kunit_info(test, "table uc_index %d", arg->table.uc_index);
33 kunit_info(test, "table n_entries %d", arg->table.n_entries);
34
35 return flags;
36 }
37
read_l3cc_table(struct xe_gt * gt,const struct xe_mocs_info * info)38 static void read_l3cc_table(struct xe_gt *gt,
39 const struct xe_mocs_info *info)
40 {
41 unsigned int i;
42 u32 l3cc;
43 u32 reg_val;
44 u32 ret;
45
46 struct kunit *test = xe_cur_kunit();
47
48 xe_device_mem_access_get(gt_to_xe(gt));
49 ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
50 KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");
51 mocs_dbg(>_to_xe(gt)->drm, "L3CC entries:%d\n", info->n_entries);
52 for (i = 0;
53 i < (info->n_entries + 1) / 2 ?
54 (l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
55 get_entry_l3cc(info, 2 * i + 1))), 1 : 0;
56 i++) {
57 if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1250)
58 reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
59 else
60 reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
61 mocs_dbg(>_to_xe(gt)->drm, "%d 0x%x 0x%x 0x%x\n", i,
62 XELP_LNCFCMOCS(i).addr, reg_val, l3cc);
63 if (reg_val != l3cc)
64 KUNIT_FAIL(test, "l3cc reg 0x%x has incorrect val.\n",
65 XELP_LNCFCMOCS(i).addr);
66 }
67 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
68 xe_device_mem_access_put(gt_to_xe(gt));
69 }
70
read_mocs_table(struct xe_gt * gt,const struct xe_mocs_info * info)71 static void read_mocs_table(struct xe_gt *gt,
72 const struct xe_mocs_info *info)
73 {
74 struct xe_device *xe = gt_to_xe(gt);
75
76 unsigned int i;
77 u32 mocs;
78 u32 reg_val;
79 u32 ret;
80
81 struct kunit *test = xe_cur_kunit();
82
83 xe_device_mem_access_get(gt_to_xe(gt));
84 ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
85 KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");
86 mocs_dbg(>_to_xe(gt)->drm, "Global MOCS entries:%d\n", info->n_entries);
87 drm_WARN_ONCE(&xe->drm, !info->unused_entries_index,
88 "Unused entries index should have been defined\n");
89 for (i = 0;
90 i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
91 i++) {
92 if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1250)
93 reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
94 else
95 reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
96 mocs_dbg(>_to_xe(gt)->drm, "%d 0x%x 0x%x 0x%x\n", i,
97 XELP_GLOBAL_MOCS(i).addr, reg_val, mocs);
98 if (reg_val != mocs)
99 KUNIT_FAIL(test, "mocs reg 0x%x has incorrect val.\n",
100 XELP_GLOBAL_MOCS(i).addr);
101 }
102 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
103 xe_device_mem_access_put(gt_to_xe(gt));
104 }
105
mocs_kernel_test_run_device(struct xe_device * xe)106 static int mocs_kernel_test_run_device(struct xe_device *xe)
107 {
108 /* Basic check the system is configured with the expected mocs table */
109
110 struct live_mocs mocs;
111 struct xe_gt *gt;
112
113 unsigned int flags;
114 int id;
115
116 for_each_gt(gt, xe, id) {
117 flags = live_mocs_init(&mocs, gt);
118 if (flags & HAS_GLOBAL_MOCS)
119 read_mocs_table(gt, &mocs.table);
120 if (flags & HAS_LNCF_MOCS)
121 read_l3cc_table(gt, &mocs.table);
122 }
123 return 0;
124 }
125
xe_live_mocs_kernel_kunit(struct kunit * test)126 void xe_live_mocs_kernel_kunit(struct kunit *test)
127 {
128 xe_call_for_each_device(mocs_kernel_test_run_device);
129 }
130 EXPORT_SYMBOL_IF_KUNIT(xe_live_mocs_kernel_kunit);
131