xref: /qemu/target/loongarch/internals.h (revision d9bf9713239945a5d4187593599de49da3351416)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * QEMU LoongArch CPU -- internal functions and types
4  *
5  * Copyright (c) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef LOONGARCH_INTERNALS_H
9 #define LOONGARCH_INTERNALS_H
10 
11 #define FCMP_LT   0b0001  /* fp0 < fp1 */
12 #define FCMP_EQ   0b0010  /* fp0 = fp1 */
13 #define FCMP_UN   0b0100  /* unordered */
14 #define FCMP_GT   0b1000  /* fp0 > fp1 */
15 
16 #define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
17 #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
18 
19 void loongarch_translate_init(void);
20 void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
21                               int *max_insns, vaddr pc, void *host_pc);
22 
23 void G_NORETURN do_raise_exception(CPULoongArchState *env,
24                                    uint32_t exception,
25                                    uintptr_t pc);
26 
27 const char *loongarch_exception_name(int32_t exception);
28 
29 #ifdef CONFIG_TCG
30 int ieee_ex_to_loongarch(int xcpt);
31 void restore_fp_status(CPULoongArchState *env);
32 #endif
33 
34 #ifndef CONFIG_USER_ONLY
35 enum {
36     TLBRET_MATCH = 0,
37     TLBRET_BADADDR = 1,
38     TLBRET_NOMATCH = 2,
39     TLBRET_INVALID = 3,
40     TLBRET_DIRTY = 4,
41     TLBRET_RI = 5,
42     TLBRET_XI = 6,
43     TLBRET_PE = 7,
44 };
45 
46 bool check_ps(CPULoongArchState *ent, uint8_t ps);
47 
48 extern const VMStateDescription vmstate_loongarch_cpu;
49 
50 void loongarch_cpu_set_irq(void *opaque, int irq, int level);
51 
52 void loongarch_constant_timer_cb(void *opaque);
53 uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
54 uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
55 void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
56                                                uint64_t value);
57 int get_physical_address(CPULoongArchState *env, hwaddr *physical,
58                          int *prot, target_ulong address,
59                          MMUAccessType access_type, int mmu_idx, int is_debug);
60 void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
61                                uint64_t *dir_width, target_ulong level);
62 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
63 
64 #endif /* !CONFIG_USER_ONLY */
65 
66 uint64_t read_fcc(CPULoongArchState *env);
67 void write_fcc(CPULoongArchState *env, uint64_t val);
68 
69 int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
70 int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
71 void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
72 int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
73                                    int cpuid, DumpState *s);
74 
75 #endif
76