1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8112 "M2" SoC 4 * 5 * Other names: H14G 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 compatible = "apple,t8112", "apple,arm-platform"; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu_e0>; 30 }; 31 core1 { 32 cpu = <&cpu_e1>; 33 }; 34 core2 { 35 cpu = <&cpu_e2>; 36 }; 37 core3 { 38 cpu = <&cpu_e3>; 39 }; 40 }; 41 42 cluster1 { 43 core0 { 44 cpu = <&cpu_p0>; 45 }; 46 core1 { 47 cpu = <&cpu_p1>; 48 }; 49 core2 { 50 cpu = <&cpu_p2>; 51 }; 52 core3 { 53 cpu = <&cpu_p3>; 54 }; 55 }; 56 }; 57 58 cpu_e0: cpu@0 { 59 compatible = "apple,blizzard"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "spin-table"; 63 cpu-release-addr = <0 0>; /* To be filled by loader */ 64 operating-points-v2 = <&ecluster_opp>; 65 capacity-dmips-mhz = <756>; 66 performance-domains = <&cpufreq_e>; 67 next-level-cache = <&l2_cache_0>; 68 i-cache-size = <0x20000>; 69 d-cache-size = <0x10000>; 70 }; 71 72 cpu_e1: cpu@1 { 73 compatible = "apple,blizzard"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 operating-points-v2 = <&ecluster_opp>; 79 capacity-dmips-mhz = <756>; 80 performance-domains = <&cpufreq_e>; 81 next-level-cache = <&l2_cache_0>; 82 i-cache-size = <0x20000>; 83 d-cache-size = <0x10000>; 84 }; 85 86 cpu_e2: cpu@2 { 87 compatible = "apple,blizzard"; 88 device_type = "cpu"; 89 reg = <0x0 0x2>; 90 enable-method = "spin-table"; 91 cpu-release-addr = <0 0>; /* To be filled by loader */ 92 operating-points-v2 = <&ecluster_opp>; 93 capacity-dmips-mhz = <756>; 94 performance-domains = <&cpufreq_e>; 95 next-level-cache = <&l2_cache_0>; 96 i-cache-size = <0x20000>; 97 d-cache-size = <0x10000>; 98 }; 99 100 cpu_e3: cpu@3 { 101 compatible = "apple,blizzard"; 102 device_type = "cpu"; 103 reg = <0x0 0x3>; 104 enable-method = "spin-table"; 105 cpu-release-addr = <0 0>; /* To be filled by loader */ 106 operating-points-v2 = <&ecluster_opp>; 107 capacity-dmips-mhz = <756>; 108 performance-domains = <&cpufreq_e>; 109 next-level-cache = <&l2_cache_0>; 110 i-cache-size = <0x20000>; 111 d-cache-size = <0x10000>; 112 }; 113 114 cpu_p0: cpu@10100 { 115 compatible = "apple,avalanche"; 116 device_type = "cpu"; 117 reg = <0x0 0x10100>; 118 enable-method = "spin-table"; 119 cpu-release-addr = <0 0>; /* To be filled by loader */ 120 operating-points-v2 = <&pcluster_opp>; 121 capacity-dmips-mhz = <1024>; 122 performance-domains = <&cpufreq_p>; 123 next-level-cache = <&l2_cache_1>; 124 i-cache-size = <0x30000>; 125 d-cache-size = <0x20000>; 126 }; 127 128 cpu_p1: cpu@10101 { 129 compatible = "apple,avalanche"; 130 device_type = "cpu"; 131 reg = <0x0 0x10101>; 132 enable-method = "spin-table"; 133 cpu-release-addr = <0 0>; /* To be filled by loader */ 134 operating-points-v2 = <&pcluster_opp>; 135 capacity-dmips-mhz = <1024>; 136 performance-domains = <&cpufreq_p>; 137 next-level-cache = <&l2_cache_1>; 138 i-cache-size = <0x30000>; 139 d-cache-size = <0x20000>; 140 }; 141 142 cpu_p2: cpu@10102 { 143 compatible = "apple,avalanche"; 144 device_type = "cpu"; 145 reg = <0x0 0x10102>; 146 enable-method = "spin-table"; 147 cpu-release-addr = <0 0>; /* To be filled by loader */ 148 operating-points-v2 = <&pcluster_opp>; 149 capacity-dmips-mhz = <1024>; 150 performance-domains = <&cpufreq_p>; 151 next-level-cache = <&l2_cache_1>; 152 i-cache-size = <0x30000>; 153 d-cache-size = <0x20000>; 154 }; 155 156 cpu_p3: cpu@10103 { 157 compatible = "apple,avalanche"; 158 device_type = "cpu"; 159 reg = <0x0 0x10103>; 160 enable-method = "spin-table"; 161 cpu-release-addr = <0 0>; /* To be filled by loader */ 162 operating-points-v2 = <&pcluster_opp>; 163 capacity-dmips-mhz = <1024>; 164 performance-domains = <&cpufreq_p>; 165 next-level-cache = <&l2_cache_1>; 166 i-cache-size = <0x30000>; 167 d-cache-size = <0x20000>; 168 }; 169 170 l2_cache_0: l2-cache-0 { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 cache-size = <0x400000>; 175 }; 176 177 l2_cache_1: l2-cache-1 { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 cache-size = <0x1000000>; 182 }; 183 }; 184 185 ecluster_opp: opp-table-0 { 186 compatible = "operating-points-v2"; 187 opp-shared; 188 189 opp01 { 190 opp-hz = /bits/ 64 <600000000>; 191 opp-level = <1>; 192 clock-latency-ns = <7500>; 193 }; 194 opp02 { 195 opp-hz = /bits/ 64 <912000000>; 196 opp-level = <2>; 197 clock-latency-ns = <20000>; 198 }; 199 opp03 { 200 opp-hz = /bits/ 64 <1284000000>; 201 opp-level = <3>; 202 clock-latency-ns = <22000>; 203 }; 204 opp04 { 205 opp-hz = /bits/ 64 <1752000000>; 206 opp-level = <4>; 207 clock-latency-ns = <30000>; 208 }; 209 opp05 { 210 opp-hz = /bits/ 64 <2004000000>; 211 opp-level = <5>; 212 clock-latency-ns = <35000>; 213 }; 214 opp06 { 215 opp-hz = /bits/ 64 <2256000000>; 216 opp-level = <6>; 217 clock-latency-ns = <39000>; 218 }; 219 opp07 { 220 opp-hz = /bits/ 64 <2424000000>; 221 opp-level = <7>; 222 clock-latency-ns = <53000>; 223 }; 224 }; 225 226 pcluster_opp: opp-table-1 { 227 compatible = "operating-points-v2"; 228 opp-shared; 229 230 opp01 { 231 opp-hz = /bits/ 64 <660000000>; 232 opp-level = <1>; 233 clock-latency-ns = <9000>; 234 }; 235 opp02 { 236 opp-hz = /bits/ 64 <924000000>; 237 opp-level = <2>; 238 clock-latency-ns = <19000>; 239 }; 240 opp03 { 241 opp-hz = /bits/ 64 <1188000000>; 242 opp-level = <3>; 243 clock-latency-ns = <22000>; 244 }; 245 opp04 { 246 opp-hz = /bits/ 64 <1452000000>; 247 opp-level = <4>; 248 clock-latency-ns = <24000>; 249 }; 250 opp05 { 251 opp-hz = /bits/ 64 <1704000000>; 252 opp-level = <5>; 253 clock-latency-ns = <26000>; 254 }; 255 opp06 { 256 opp-hz = /bits/ 64 <1968000000>; 257 opp-level = <6>; 258 clock-latency-ns = <28000>; 259 }; 260 opp07 { 261 opp-hz = /bits/ 64 <2208000000>; 262 opp-level = <7>; 263 clock-latency-ns = <30000>; 264 }; 265 opp08 { 266 opp-hz = /bits/ 64 <2400000000>; 267 opp-level = <8>; 268 clock-latency-ns = <33000>; 269 }; 270 opp09 { 271 opp-hz = /bits/ 64 <2568000000>; 272 opp-level = <9>; 273 clock-latency-ns = <34000>; 274 }; 275 opp10 { 276 opp-hz = /bits/ 64 <2724000000>; 277 opp-level = <10>; 278 clock-latency-ns = <36000>; 279 }; 280 opp11 { 281 opp-hz = /bits/ 64 <2868000000>; 282 opp-level = <11>; 283 clock-latency-ns = <41000>; 284 }; 285 opp12 { 286 opp-hz = /bits/ 64 <2988000000>; 287 opp-level = <12>; 288 clock-latency-ns = <42000>; 289 }; 290 opp13 { 291 opp-hz = /bits/ 64 <3096000000>; 292 opp-level = <13>; 293 clock-latency-ns = <44000>; 294 }; 295 opp14 { 296 opp-hz = /bits/ 64 <3204000000>; 297 opp-level = <14>; 298 clock-latency-ns = <46000>; 299 }; 300 /* Not available until CPU deep sleep is implemented */ 301#if 0 302 opp15 { 303 opp-hz = /bits/ 64 <3324000000>; 304 opp-level = <15>; 305 clock-latency-ns = <62000>; 306 turbo-mode; 307 }; 308 opp16 { 309 opp-hz = /bits/ 64 <3408000000>; 310 opp-level = <16>; 311 clock-latency-ns = <62000>; 312 turbo-mode; 313 }; 314 opp17 { 315 opp-hz = /bits/ 64 <3504000000>; 316 opp-level = <17>; 317 clock-latency-ns = <62000>; 318 turbo-mode; 319 }; 320#endif 321 }; 322 323 timer { 324 compatible = "arm,armv8-timer"; 325 interrupt-parent = <&aic>; 326 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 327 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 328 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 329 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 330 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 331 }; 332 333 pmu-e { 334 compatible = "apple,blizzard-pmu"; 335 interrupt-parent = <&aic>; 336 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 337 }; 338 339 pmu-p { 340 compatible = "apple,avalanche-pmu"; 341 interrupt-parent = <&aic>; 342 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 343 }; 344 345 clkref: clock-ref { 346 compatible = "fixed-clock"; 347 #clock-cells = <0>; 348 clock-frequency = <24000000>; 349 clock-output-names = "clkref"; 350 }; 351 352 clk_200m: clock-200m { 353 compatible = "fixed-clock"; 354 #clock-cells = <0>; 355 clock-frequency = <200000000>; 356 clock-output-names = "clk_200m"; 357 }; 358 359 /* 360 * This is a fabulated representation of the input clock 361 * to NCO since we don't know the true clock tree. 362 */ 363 nco_clkref: clock-ref-nco { 364 compatible = "fixed-clock"; 365 #clock-cells = <0>; 366 clock-output-names = "nco_ref"; 367 }; 368 369 soc { 370 compatible = "simple-bus"; 371 #address-cells = <2>; 372 #size-cells = <2>; 373 374 ranges; 375 nonposted-mmio; 376 377 cpufreq_e: cpufreq@210e20000 { 378 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 379 reg = <0x2 0x10e20000 0 0x1000>; 380 #performance-domain-cells = <0>; 381 }; 382 383 cpufreq_p: cpufreq@211e20000 { 384 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 385 reg = <0x2 0x11e20000 0 0x1000>; 386 #performance-domain-cells = <0>; 387 }; 388 389 display_dfr: display-pipe@228200000 { 390 compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe"; 391 reg = <0x2 0x28200000 0x0 0xc000>, 392 <0x2 0x28400000 0x0 0x4000>; 393 reg-names = "be", "fe"; 394 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; 395 interrupt-parent = <&aic>; 396 interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>, 397 <AIC_IRQ 618 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "be", "fe"; 399 iommus = <&displaydfr_dart 0>; 400 status = "disabled"; 401 402 port { 403 dfr_adp_out_mipi: endpoint { 404 remote-endpoint = <&dfr_mipi_in_adp>; 405 }; 406 }; 407 }; 408 409 displaydfr_dart: iommu@228304000 { 410 compatible = "apple,t8110-dart"; 411 reg = <0x2 0x28304000 0x0 0x4000>; 412 interrupt-parent = <&aic>; 413 interrupts = <AIC_IRQ 616 IRQ_TYPE_LEVEL_HIGH>; 414 #iommu-cells = <1>; 415 power-domains = <&ps_dispdfr_fe>; 416 status = "disabled"; 417 }; 418 419 displaydfr_mipi: dsi@228600000 { 420 compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi"; 421 reg = <0x2 0x28600000 0x0 0x100000>; 422 power-domains = <&ps_mipi_dsi>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 427 ports { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 dfr_mipi_in: port@0 { 432 reg = <0>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 dfr_mipi_in_adp: endpoint@0 { 437 reg = <0>; 438 remote-endpoint = <&dfr_adp_out_mipi>; 439 }; 440 }; 441 442 dfr_mipi_out: port@1 { 443 reg = <1>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 }; 448 }; 449 450 sio_dart: iommu@235004000 { 451 compatible = "apple,t8110-dart"; 452 reg = <0x2 0x35004000 0x0 0x4000>; 453 interrupt-parent = <&aic>; 454 interrupts = <AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH>; 455 #iommu-cells = <1>; 456 power-domains = <&ps_sio_cpu>; 457 }; 458 459 i2c0: i2c@235010000 { 460 compatible = "apple,t8112-i2c", "apple,i2c"; 461 reg = <0x2 0x35010000 0x0 0x4000>; 462 clocks = <&clkref>; 463 interrupt-parent = <&aic>; 464 interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>; 465 pinctrl-0 = <&i2c0_pins>; 466 pinctrl-names = "default"; 467 #address-cells = <0x1>; 468 #size-cells = <0x0>; 469 power-domains = <&ps_i2c0>; 470 status = "disabled"; 471 }; 472 473 i2c1: i2c@235014000 { 474 compatible = "apple,t8112-i2c", "apple,i2c"; 475 reg = <0x2 0x35014000 0x0 0x4000>; 476 clocks = <&clkref>; 477 interrupt-parent = <&aic>; 478 interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>; 479 pinctrl-0 = <&i2c1_pins>; 480 pinctrl-names = "default"; 481 #address-cells = <0x1>; 482 #size-cells = <0x0>; 483 power-domains = <&ps_i2c1>; 484 status = "disabled"; 485 }; 486 487 i2c2: i2c@235018000 { 488 compatible = "apple,t8112-i2c", "apple,i2c"; 489 reg = <0x2 0x35018000 0x0 0x4000>; 490 clocks = <&clkref>; 491 interrupt-parent = <&aic>; 492 interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>; 493 pinctrl-0 = <&i2c2_pins>; 494 pinctrl-names = "default"; 495 #address-cells = <0x1>; 496 #size-cells = <0x0>; 497 power-domains = <&ps_i2c2>; 498 status = "disabled"; 499 }; 500 501 i2c3: i2c@23501c000 { 502 compatible = "apple,t8112-i2c", "apple,i2c"; 503 reg = <0x2 0x3501c000 0x0 0x4000>; 504 clocks = <&clkref>; 505 interrupt-parent = <&aic>; 506 interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>; 507 pinctrl-0 = <&i2c3_pins>; 508 pinctrl-names = "default"; 509 #address-cells = <0x1>; 510 #size-cells = <0x0>; 511 power-domains = <&ps_i2c3>; 512 status = "disabled"; 513 }; 514 515 i2c4: i2c@235020000 { 516 compatible = "apple,t8112-i2c", "apple,i2c"; 517 reg = <0x2 0x35020000 0x0 0x4000>; 518 clocks = <&clkref>; 519 interrupt-parent = <&aic>; 520 interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>; 521 pinctrl-0 = <&i2c4_pins>; 522 pinctrl-names = "default"; 523 #address-cells = <0x1>; 524 #size-cells = <0x0>; 525 power-domains = <&ps_i2c4>; 526 status = "disabled"; 527 }; 528 529 fpwm1: pwm@235044000 { 530 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm"; 531 reg = <0x2 0x35044000 0x0 0x4000>; 532 power-domains = <&ps_fpwm1>; 533 clocks = <&clkref>; 534 #pwm-cells = <2>; 535 status = "disabled"; 536 }; 537 538 spi1: spi@235104000 { 539 compatible = "apple,t8112-spi", "apple,spi"; 540 reg = <0x2 0x35104000 0x0 0x4000>; 541 interrupt-parent = <&aic>; 542 interrupts = <AIC_IRQ 749 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clk_200m>; 544 pinctrl-0 = <&spi1_pins>; 545 pinctrl-names = "default"; 546 power-domains = <&ps_spi1>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 spi3: spi@23510c000 { 553 compatible = "apple,t8112-spi", "apple,spi"; 554 reg = <0x2 0x3510c000 0x0 0x4000>; 555 interrupt-parent = <&aic>; 556 interrupts = <AIC_IRQ 751 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&clkref>; 558 pinctrl-0 = <&spi3_pins>; 559 pinctrl-names = "default"; 560 power-domains = <&ps_spi3>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; /* only used in J493 */ 564 }; 565 566 serial0: serial@235200000 { 567 compatible = "apple,s5l-uart"; 568 reg = <0x2 0x35200000 0x0 0x1000>; 569 reg-io-width = <4>; 570 interrupt-parent = <&aic>; 571 interrupts = <AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH>; 572 /* 573 * TODO: figure out the clocking properly, there may 574 * be a third selectable clock. 575 */ 576 clocks = <&clkref>, <&clkref>; 577 clock-names = "uart", "clk_uart_baud0"; 578 power-domains = <&ps_uart0>; 579 status = "disabled"; 580 }; 581 582 serial2: serial@235208000 { 583 compatible = "apple,s5l-uart"; 584 reg = <0x2 0x35208000 0x0 0x1000>; 585 reg-io-width = <4>; 586 interrupt-parent = <&aic>; 587 interrupts = <AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clkref>, <&clkref>; 589 clock-names = "uart", "clk_uart_baud0"; 590 power-domains = <&ps_uart2>; 591 status = "disabled"; 592 }; 593 594 admac: dma-controller@238200000 { 595 compatible = "apple,t8112-admac", "apple,admac"; 596 reg = <0x2 0x38200000 0x0 0x34000>; 597 dma-channels = <24>; 598 interrupts-extended = <0>, 599 <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>, 600 <0>, 601 <0>; 602 #dma-cells = <1>; 603 iommus = <&sio_dart 2>; 604 power-domains = <&ps_sio_adma>; 605 resets = <&ps_audio_p>; 606 }; 607 608 mca: i2s@238400000 { 609 compatible = "apple,t8112-mca", "apple,mca"; 610 reg = <0x2 0x38400000 0x0 0x18000>, 611 <0x2 0x38300000 0x0 0x30000>; 612 613 interrupt-parent = <&aic>; 614 interrupts = <AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH>, 615 <AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH>, 616 <AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH>, 617 <AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH>, 618 <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>, 619 <AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH>; 620 621 resets = <&ps_audio_p>; 622 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 623 <&nco 3>, <&nco 4>, <&nco 4>; 624 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 625 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 626 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 627 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 628 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 629 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 630 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 631 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 632 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 633 "tx1a", "rx1a", "tx1b", "rx1b", 634 "tx2a", "rx2a", "tx2b", "rx2b", 635 "tx3a", "rx3a", "tx3b", "rx3b", 636 "tx4a", "rx4a", "tx4b", "rx4b", 637 "tx5a", "rx5a", "tx5b", "rx5b"; 638 639 #sound-dai-cells = <1>; 640 }; 641 642 nco: clock-controller@23b044000 { 643 compatible = "apple,t8112-nco", "apple,nco"; 644 reg = <0x2 0x3b044000 0x0 0x14000>; 645 clocks = <&nco_clkref>; 646 #clock-cells = <1>; 647 }; 648 649 aic: interrupt-controller@23b0c0000 { 650 compatible = "apple,t8112-aic", "apple,aic2"; 651 #interrupt-cells = <3>; 652 interrupt-controller; 653 reg = <0x2 0x3b0c0000 0x0 0x8000>, 654 <0x2 0x3b0c8000 0x0 0x4>; 655 reg-names = "core", "event"; 656 power-domains = <&ps_aic>; 657 658 affinities { 659 e-core-pmu-affinity { 660 apple,fiq-index = <AIC_CPU_PMU_E>; 661 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 662 }; 663 664 p-core-pmu-affinity { 665 apple,fiq-index = <AIC_CPU_PMU_P>; 666 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 667 }; 668 }; 669 }; 670 671 pmgr: power-management@23b700000 { 672 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 reg = <0x2 0x3b700000 0 0x14000>; 676 /* child nodes are added in t8103-pmgr.dtsi */ 677 }; 678 679 pinctrl_ap: pinctrl@23c100000 { 680 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 681 reg = <0x2 0x3c100000 0x0 0x100000>; 682 power-domains = <&ps_gpio>; 683 684 gpio-controller; 685 #gpio-cells = <2>; 686 gpio-ranges = <&pinctrl_ap 0 0 213>; 687 apple,npins = <213>; 688 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 interrupt-parent = <&aic>; 692 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 693 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 694 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 695 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 696 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 697 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 698 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 699 700 i2c0_pins: i2c0-pins { 701 pinmux = <APPLE_PINMUX(111, 1)>, 702 <APPLE_PINMUX(110, 1)>; 703 }; 704 705 i2c1_pins: i2c1-pins { 706 pinmux = <APPLE_PINMUX(113, 1)>, 707 <APPLE_PINMUX(112, 1)>; 708 }; 709 710 i2c2_pins: i2c2-pins { 711 pinmux = <APPLE_PINMUX(87, 1)>, 712 <APPLE_PINMUX(86, 1)>; 713 }; 714 715 i2c3_pins: i2c3-pins { 716 pinmux = <APPLE_PINMUX(54, 1)>, 717 <APPLE_PINMUX(53, 1)>; 718 }; 719 720 i2c4_pins: i2c4-pins { 721 pinmux = <APPLE_PINMUX(131, 1)>, 722 <APPLE_PINMUX(130, 1)>; 723 }; 724 725 spi1_pins: spi1-pins { 726 pinmux = <APPLE_PINMUX(46, 1)>, 727 <APPLE_PINMUX(47, 1)>, 728 <APPLE_PINMUX(48, 1)>, 729 <APPLE_PINMUX(49, 1)>; 730 }; 731 732 spi3_pins: spi3-pins { 733 pinmux = <APPLE_PINMUX(93, 1)>, 734 <APPLE_PINMUX(94, 1)>, 735 <APPLE_PINMUX(95, 1)>, 736 <APPLE_PINMUX(96, 1)>; 737 }; 738 739 pcie_pins: pcie-pins { 740 pinmux = <APPLE_PINMUX(162, 1)>, 741 <APPLE_PINMUX(163, 1)>, 742 <APPLE_PINMUX(164, 1)>; 743 // TODO: 1 more CLKREQs 744 }; 745 }; 746 747 pinctrl_nub: pinctrl@23d1f0000 { 748 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 749 reg = <0x2 0x3d1f0000 0x0 0x4000>; 750 power-domains = <&ps_nub_gpio>; 751 752 gpio-controller; 753 #gpio-cells = <2>; 754 gpio-ranges = <&pinctrl_nub 0 0 24>; 755 apple,npins = <24>; 756 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 interrupt-parent = <&aic>; 760 interrupts = <AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH>, 761 <AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH>, 762 <AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH>, 763 <AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH>, 764 <AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH>, 765 <AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH>, 766 <AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH>; 767 }; 768 769 pmgr_mini: power-management@23d280000 { 770 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 771 #address-cells = <1>; 772 #size-cells = <1>; 773 reg = <0x2 0x3d280000 0 0x4000>; 774 /* child nodes are added in t8103-pmgr.dtsi */ 775 }; 776 777 wdt: watchdog@23d2b0000 { 778 compatible = "apple,t8112-wdt", "apple,wdt"; 779 reg = <0x2 0x3d2b0000 0x0 0x4000>; 780 clocks = <&clkref>; 781 interrupt-parent = <&aic>; 782 interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>; 783 }; 784 785 pinctrl_smc: pinctrl@23e820000 { 786 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 787 reg = <0x2 0x3e820000 0x0 0x4000>; 788 789 gpio-controller; 790 #gpio-cells = <2>; 791 gpio-ranges = <&pinctrl_smc 0 0 18>; 792 apple,npins = <18>; 793 794 interrupt-controller; 795 #interrupt-cells = <2>; 796 interrupt-parent = <&aic>; 797 interrupts = <AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH>, 798 <AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH>, 799 <AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH>, 800 <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>, 801 <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>, 802 <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>, 803 <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>; 804 }; 805 806 pinctrl_aop: pinctrl@24a820000 { 807 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 808 reg = <0x2 0x4a820000 0x0 0x4000>; 809 810 gpio-controller; 811 #gpio-cells = <2>; 812 gpio-ranges = <&pinctrl_aop 0 0 54>; 813 apple,npins = <54>; 814 815 interrupt-controller; 816 #interrupt-cells = <2>; 817 interrupt-parent = <&aic>; 818 interrupts = <AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH>, 819 <AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH>, 820 <AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH>, 821 <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>, 822 <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>, 823 <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>, 824 <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; 825 }; 826 827 ans_mbox: mbox@277408000 { 828 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; 829 reg = <0x2 0x77408000 0x0 0x4000>; 830 interrupt-parent = <&aic>; 831 interrupts = <AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH>, 832 <AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH>, 833 <AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH>, 834 <AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-names = "send-empty", "send-not-empty", 836 "recv-empty", "recv-not-empty"; 837 #mbox-cells = <0>; 838 power-domains = <&ps_ans>; 839 }; 840 841 sart: sart@27bc50000 { 842 compatible = "apple,t8112-sart", "apple,t6000-sart"; 843 reg = <0x2 0x7bc50000 0x0 0x10000>; 844 power-domains = <&ps_ans>; 845 }; 846 847 nvme@27bcc0000 { 848 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2"; 849 reg = <0x2 0x7bcc0000 0x0 0x40000>, 850 <0x2 0x77400000 0x0 0x4000>; 851 reg-names = "nvme", "ans"; 852 interrupt-parent = <&aic>; 853 interrupts = <AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH>; 854 mboxes = <&ans_mbox>; 855 apple,sart = <&sart>; 856 power-domains = <&ps_ans>, <&ps_apcie_st>; 857 power-domain-names = "ans", "apcie0"; 858 resets = <&ps_ans>; 859 }; 860 861 pcie0_dart: iommu@681008000 { 862 compatible = "apple,t8110-dart"; 863 reg = <0x6 0x81008000 0x0 0x4000>; 864 #iommu-cells = <1>; 865 interrupt-parent = <&aic>; 866 interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>; 867 power-domains = <&ps_apcie_gp>; 868 }; 869 870 pcie1_dart: iommu@682008000 { 871 compatible = "apple,t8110-dart"; 872 reg = <0x6 0x82008000 0x0 0x4000>; 873 #iommu-cells = <1>; 874 interrupt-parent = <&aic>; 875 interrupts = <AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH>; 876 power-domains = <&ps_apcie_gp>; 877 status = "disabled"; 878 }; 879 880 pcie2_dart: iommu@683008000 { 881 compatible = "apple,t8110-dart"; 882 reg = <0x6 0x83008000 0x0 0x4000>; 883 #iommu-cells = <1>; 884 interrupt-parent = <&aic>; 885 interrupts = <AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&ps_apcie_gp>; 887 status = "disabled"; 888 }; 889 890 pcie3_dart: iommu@684008000 { 891 compatible = "apple,t8110-dart"; 892 reg = <0x6 0x84008000 0x0 0x4000>; 893 #iommu-cells = <1>; 894 interrupt-parent = <&aic>; 895 interrupts = <AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH>; 896 power-domains = <&ps_apcie_gp>; 897 status = "disabled"; 898 }; 899 900 pcie0: pcie@690000000 { 901 compatible = "apple,t8112-pcie", "apple,pcie"; 902 device_type = "pci"; 903 904 reg = <0x6 0x90000000 0x0 0x1000000>, 905 <0x6 0x80000000 0x0 0x100000>, 906 <0x6 0x81000000 0x0 0x4000>, 907 <0x6 0x82000000 0x0 0x4000>, 908 <0x6 0x83000000 0x0 0x4000>, 909 <0x6 0x84000000 0x0 0x4000>; 910 reg-names = "config", "rc", "port0", "port1", "port2", "port3"; 911 912 interrupt-parent = <&aic>; 913 interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>, 914 <AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>, 915 <AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH>, 916 <AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>; 917 918 msi-controller; 919 msi-parent = <&pcie0>; 920 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>; 921 922 iommu-map = <0x100 &pcie0_dart 0 1>, 923 <0x200 &pcie1_dart 1 1>, 924 <0x300 &pcie2_dart 2 1>, 925 <0x400 &pcie3_dart 3 1>; 926 iommu-map-mask = <0xff00>; 927 928 bus-range = <0 4>; 929 #address-cells = <3>; 930 #size-cells = <2>; 931 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 932 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 933 934 power-domains = <&ps_apcie_gp>; 935 pinctrl-0 = <&pcie_pins>; 936 pinctrl-names = "default"; 937 938 port00: pci@0,0 { 939 device_type = "pci"; 940 reg = <0x0 0x0 0x0 0x0 0x0>; 941 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>; 942 943 #address-cells = <3>; 944 #size-cells = <2>; 945 ranges; 946 947 interrupt-controller; 948 #interrupt-cells = <1>; 949 950 interrupt-map-mask = <0 0 0 7>; 951 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 952 <0 0 0 2 &port00 0 0 0 1>, 953 <0 0 0 3 &port00 0 0 0 2>, 954 <0 0 0 4 &port00 0 0 0 3>; 955 }; 956 957 port01: pci@1,0 { 958 device_type = "pci"; 959 reg = <0x800 0x0 0x0 0x0 0x0>; 960 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>; 961 962 #address-cells = <3>; 963 #size-cells = <2>; 964 ranges; 965 966 interrupt-controller; 967 #interrupt-cells = <1>; 968 969 interrupt-map-mask = <0 0 0 7>; 970 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 971 <0 0 0 2 &port01 0 0 0 1>, 972 <0 0 0 3 &port01 0 0 0 2>, 973 <0 0 0 4 &port01 0 0 0 3>; 974 975 status = "disabled"; 976 }; 977 978 port02: pci@2,0 { 979 device_type = "pci"; 980 reg = <0x1000 0x0 0x0 0x0 0x0>; 981 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>; 982 983 #address-cells = <3>; 984 #size-cells = <2>; 985 ranges; 986 987 interrupt-controller; 988 #interrupt-cells = <1>; 989 990 interrupt-map-mask = <0 0 0 7>; 991 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 992 <0 0 0 2 &port02 0 0 0 1>, 993 <0 0 0 3 &port02 0 0 0 2>, 994 <0 0 0 4 &port02 0 0 0 3>; 995 996 status = "disabled"; 997 }; 998 999 /* TODO: GPIO unknown */ 1000 port03: pci@3,0 { 1001 device_type = "pci"; 1002 reg = <0x1800 0x0 0x0 0x0 0x0>; 1003 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 1004 1005 #address-cells = <3>; 1006 #size-cells = <2>; 1007 ranges; 1008 1009 interrupt-controller; 1010 #interrupt-cells = <1>; 1011 1012 interrupt-map-mask = <0 0 0 7>; 1013 interrupt-map = <0 0 0 1 &port03 0 0 0 0>, 1014 <0 0 0 2 &port03 0 0 0 1>, 1015 <0 0 0 3 &port03 0 0 0 2>, 1016 <0 0 0 4 &port03 0 0 0 3>; 1017 1018 status = "disabled"; 1019 }; 1020 }; 1021 }; 1022}; 1023 1024#include "t8112-pmgr.dtsi" 1025