1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T7000 "A8" SoC 4 * 5 * Other names: H7P, "Fiji" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/apple-aic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/apple.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "apple,typhoon"; 34 reg = <0x0 0x0>; 35 cpu-release-addr = <0 0>; /* To be filled in by loader */ 36 performance-domains = <&cpufreq>; 37 operating-points-v2 = <&typhoon_opp>; 38 enable-method = "spin-table"; 39 device_type = "cpu"; 40 }; 41 42 cpu1: cpu@1 { 43 compatible = "apple,typhoon"; 44 reg = <0x0 0x1>; 45 cpu-release-addr = <0 0>; /* To be filled in by loader */ 46 performance-domains = <&cpufreq>; 47 operating-points-v2 = <&typhoon_opp>; 48 enable-method = "spin-table"; 49 device_type = "cpu"; 50 }; 51 }; 52 53 typhoon_opp: opp-table { 54 compatible = "operating-points-v2"; 55 56 opp01 { 57 opp-hz = /bits/ 64 <300000000>; 58 opp-level = <1>; 59 clock-latency-ns = <300>; 60 }; 61 opp02 { 62 opp-hz = /bits/ 64 <396000000>; 63 opp-level = <2>; 64 clock-latency-ns = <50000>; 65 }; 66 opp03 { 67 opp-hz = /bits/ 64 <600000000>; 68 opp-level = <3>; 69 clock-latency-ns = <29000>; 70 }; 71 opp04 { 72 opp-hz = /bits/ 64 <840000000>; 73 opp-level = <4>; 74 clock-latency-ns = <29000>; 75 }; 76 opp05 { 77 opp-hz = /bits/ 64 <1128000000>; 78 opp-level = <5>; 79 clock-latency-ns = <36000>; 80 }; 81 typhoon_opp06: opp06 { 82 opp-hz = /bits/ 64 <1392000000>; 83 opp-level = <6>; 84 clock-latency-ns = <42000>; 85 status = "disabled"; /* Not available on N102 */ 86 }; 87 typhoon_opp07: opp07 { 88 opp-hz = /bits/ 64 <1512000000>; 89 opp-level = <7>; 90 clock-latency-ns = <49000>; 91 status = "disabled"; /* J96 and J97 only */ 92 }; 93 }; 94 95 soc { 96 compatible = "simple-bus"; 97 #address-cells = <2>; 98 #size-cells = <2>; 99 nonposted-mmio; 100 ranges; 101 102 cpufreq: performance-controller@202220000 { 103 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; 104 reg = <0x2 0x02220000 0 0x1000>; 105 #performance-domain-cells = <0>; 106 }; 107 108 serial0: serial@20a0c0000 { 109 compatible = "apple,s5l-uart"; 110 reg = <0x2 0x0a0c0000 0x0 0x4000>; 111 reg-io-width = <4>; 112 interrupt-parent = <&aic>; 113 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; 114 /* Use the bootloader-enabled clocks for now. */ 115 clocks = <&clkref>, <&clkref>; 116 clock-names = "uart", "clk_uart_baud0"; 117 power-domains = <&ps_uart0>; 118 status = "disabled"; 119 }; 120 121 serial6: serial@20a0d8000 { 122 compatible = "apple,s5l-uart"; 123 reg = <0x2 0x0a0d8000 0x0 0x4000>; 124 reg-io-width = <4>; 125 interrupt-parent = <&aic>; 126 interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>; 127 /* Use the bootloader-enabled clocks for now. */ 128 clocks = <&clkref>, <&clkref>; 129 clock-names = "uart", "clk_uart_baud0"; 130 power-domains = <&ps_uart6>; 131 status = "disabled"; 132 }; 133 134 pmgr: power-management@20e000000 { 135 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 139 reg = <0x2 0xe000000 0 0x24000>; 140 }; 141 142 wdt: watchdog@20e027000 { 143 compatible = "apple,t7000-wdt", "apple,wdt"; 144 reg = <0x2 0x0e027000 0x0 0x1000>; 145 clocks = <&clkref>; 146 interrupt-parent = <&aic>; 147 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 148 }; 149 150 aic: interrupt-controller@20e100000 { 151 compatible = "apple,t7000-aic", "apple,aic"; 152 reg = <0x2 0x0e100000 0x0 0x100000>; 153 #interrupt-cells = <3>; 154 interrupt-controller; 155 power-domains = <&ps_aic>; 156 }; 157 158 dwi_bl: backlight@20e200010 { 159 compatible = "apple,t7000-dwi-bl", "apple,dwi-bl"; 160 reg = <0x2 0x0e200010 0x0 0x8>; 161 power-domains = <&ps_dwi>; 162 status = "disabled"; 163 }; 164 165 pinctrl: pinctrl@20e300000 { 166 compatible = "apple,t7000-pinctrl", "apple,pinctrl"; 167 reg = <0x2 0x0e300000 0x0 0x100000>; 168 power-domains = <&ps_gpio>; 169 170 gpio-controller; 171 #gpio-cells = <2>; 172 gpio-ranges = <&pinctrl 0 0 208>; 173 apple,npins = <208>; 174 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 interrupt-parent = <&aic>; 178 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, 179 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, 180 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, 181 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, 182 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, 183 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, 184 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; 185 }; 186 }; 187 188 timer { 189 compatible = "arm,armv8-timer"; 190 interrupt-parent = <&aic>; 191 interrupt-names = "phys", "virt"; 192 /* Note that A8 doesn't actually have a hypervisor (EL2 is not implemented). */ 193 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 195 }; 196}; 197 198#include "t7000-pmgr.dtsi" 199