1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu/datadir.h"
29 #include "cpu.h"
30 #include "exec/target_page.h"
31 #include "hw/sysbus.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/sparc/sun4m_iommu.h"
35 #include "hw/rtc/m48t59.h"
36 #include "migration/vmstate.h"
37 #include "hw/sparc/sparc32_dma.h"
38 #include "hw/block/fdc.h"
39 #include "system/reset.h"
40 #include "system/runstate.h"
41 #include "system/system.h"
42 #include "net/net.h"
43 #include "hw/boards.h"
44 #include "hw/scsi/esp.h"
45 #include "hw/nvram/sun_nvram.h"
46 #include "hw/qdev-properties.h"
47 #include "hw/nvram/chrp_nvram.h"
48 #include "hw/nvram/fw_cfg.h"
49 #include "hw/char/escc.h"
50 #include "hw/misc/empty_slot.h"
51 #include "hw/misc/unimp.h"
52 #include "hw/irq.h"
53 #include "hw/or-irq.h"
54 #include "hw/loader.h"
55 #include "elf.h"
56 #include "trace.h"
57 #include "qom/object.h"
58
59 /*
60 * Sun4m architecture was used in the following machines:
61 *
62 * SPARCserver 6xxMP/xx
63 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
64 * SPARCclassic X (4/10)
65 * SPARCstation LX/ZX (4/30)
66 * SPARCstation Voyager
67 * SPARCstation 10/xx, SPARCserver 10/xx
68 * SPARCstation 5, SPARCserver 5
69 * SPARCstation 20/xx, SPARCserver 20
70 * SPARCstation 4
71 *
72 * See for example: http://www.sunhelp.org/faq/sunref1.html
73 */
74
75 #define KERNEL_LOAD_ADDR 0x00004000
76 #define CMDLINE_ADDR 0x007ff000
77 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_SIZE_MAX (1 * MiB)
79 #define PROM_VADDR 0xffd00000
80 #define PROM_FILENAME "openbios-sparc32"
81 #define CFG_ADDR 0xd00000510ULL
82 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
83 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
84 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88 #define MAX_VSIMMS 4
89
90 #define ESCC_CLOCK 4915200
91
92 struct sun4m_hwdef {
93 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
94 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
95 hwaddr serial_base, fd_base;
96 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
97 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
98 hwaddr bpp_base, dbri_base, sx_base;
99 struct {
100 hwaddr reg_base, vram_base;
101 } vsimm[MAX_VSIMMS];
102 hwaddr ecc_base;
103 uint64_t max_mem;
104 uint32_t ecc_version;
105 uint32_t iommu_version;
106 uint16_t machine_id;
107 uint8_t nvram_machine_id;
108 };
109
110 struct Sun4mMachineClass {
111 /*< private >*/
112 MachineClass parent_obj;
113 /*< public >*/
114 const struct sun4m_hwdef *hwdef;
115 };
116 typedef struct Sun4mMachineClass Sun4mMachineClass;
117
118 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common")
DECLARE_CLASS_CHECKERS(Sun4mMachineClass,SUN4M_MACHINE,TYPE_SUN4M_MACHINE)119 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE)
120
121 const char *fw_cfg_arch_key_name(uint16_t key)
122 {
123 static const struct {
124 uint16_t key;
125 const char *name;
126 } fw_cfg_arch_wellknown_keys[] = {
127 {FW_CFG_SUN4M_DEPTH, "depth"},
128 {FW_CFG_SUN4M_WIDTH, "width"},
129 {FW_CFG_SUN4M_HEIGHT, "height"},
130 };
131
132 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
133 if (fw_cfg_arch_wellknown_keys[i].key == key) {
134 return fw_cfg_arch_wellknown_keys[i].name;
135 }
136 }
137 return NULL;
138 }
139
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)140 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
141 Error **errp)
142 {
143 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
144 }
145
nvram_init(Nvram * nvram,uint8_t * macaddr,const char * cmdline,const char * boot_devices,ram_addr_t RAM_size,uint32_t kernel_size,int width,int height,int depth,int nvram_machine_id,const char * arch)146 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
147 const char *cmdline, const char *boot_devices,
148 ram_addr_t RAM_size, uint32_t kernel_size,
149 int width, int height, int depth,
150 int nvram_machine_id, const char *arch)
151 {
152 unsigned int i;
153 int sysp_end;
154 uint8_t image[0x1ff0];
155 NvramClass *k = NVRAM_GET_CLASS(nvram);
156
157 memset(image, '\0', sizeof(image));
158
159 /* OpenBIOS nvram variables partition */
160 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
161
162 /* Free space partition */
163 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
164
165 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
166 nvram_machine_id);
167
168 for (i = 0; i < sizeof(image); i++) {
169 (k->write)(nvram, i, image[i]);
170 }
171 }
172
cpu_kick_irq(SPARCCPU * cpu)173 static void cpu_kick_irq(SPARCCPU *cpu)
174 {
175 CPUSPARCState *env = &cpu->env;
176 CPUState *cs = CPU(cpu);
177
178 cs->halted = 0;
179 cpu_check_irqs(env);
180 qemu_cpu_kick(cs);
181 }
182
cpu_set_irq(void * opaque,int irq,int level)183 static void cpu_set_irq(void *opaque, int irq, int level)
184 {
185 SPARCCPU *cpu = opaque;
186 CPUSPARCState *env = &cpu->env;
187
188 if (level) {
189 trace_sun4m_cpu_set_irq_raise(irq);
190 env->pil_in |= 1 << irq;
191 cpu_kick_irq(cpu);
192 } else {
193 trace_sun4m_cpu_set_irq_lower(irq);
194 env->pil_in &= ~(1 << irq);
195 cpu_check_irqs(env);
196 }
197 }
198
dummy_cpu_set_irq(void * opaque,int irq,int level)199 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
200 {
201 }
202
sun4m_cpu_reset(void * opaque)203 static void sun4m_cpu_reset(void *opaque)
204 {
205 SPARCCPU *cpu = opaque;
206 CPUState *cs = CPU(cpu);
207
208 cpu_reset(cs);
209 }
210
cpu_halt_signal(void * opaque,int irq,int level)211 static void cpu_halt_signal(void *opaque, int irq, int level)
212 {
213 if (level && current_cpu) {
214 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
215 }
216 }
217
translate_kernel_address(void * opaque,uint64_t addr)218 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
219 {
220 return addr - 0xf0000000ULL;
221 }
222
sun4m_load_kernel(const char * kernel_filename,const char * initrd_filename,ram_addr_t RAM_size,uint32_t * initrd_size)223 static unsigned long sun4m_load_kernel(const char *kernel_filename,
224 const char *initrd_filename,
225 ram_addr_t RAM_size,
226 uint32_t *initrd_size)
227 {
228 int linux_boot;
229 unsigned int i;
230 long kernel_size;
231 uint8_t *ptr;
232
233 linux_boot = (kernel_filename != NULL);
234
235 kernel_size = 0;
236 if (linux_boot) {
237 kernel_size = load_elf(kernel_filename, NULL,
238 translate_kernel_address, NULL,
239 NULL, NULL, NULL, NULL,
240 ELFDATA2MSB, EM_SPARC, 0, 0);
241 if (kernel_size < 0)
242 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
243 RAM_size - KERNEL_LOAD_ADDR, true,
244 TARGET_PAGE_SIZE);
245 if (kernel_size < 0)
246 kernel_size = load_image_targphys(kernel_filename,
247 KERNEL_LOAD_ADDR,
248 RAM_size - KERNEL_LOAD_ADDR);
249 if (kernel_size < 0) {
250 error_report("could not load kernel '%s'", kernel_filename);
251 exit(1);
252 }
253
254 /* load initrd */
255 *initrd_size = 0;
256 if (initrd_filename) {
257 *initrd_size = load_image_targphys(initrd_filename,
258 INITRD_LOAD_ADDR,
259 RAM_size - INITRD_LOAD_ADDR);
260 if ((int)*initrd_size < 0) {
261 error_report("could not load initial ram disk '%s'",
262 initrd_filename);
263 exit(1);
264 }
265 }
266 if (*initrd_size > 0) {
267 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
268 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
269 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
270 stl_p(ptr + 16, INITRD_LOAD_ADDR);
271 stl_p(ptr + 20, *initrd_size);
272 break;
273 }
274 }
275 }
276 }
277 return kernel_size;
278 }
279
iommu_init(hwaddr addr,uint32_t version,qemu_irq irq)280 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
281 {
282 DeviceState *dev;
283 SysBusDevice *s;
284
285 dev = qdev_new(TYPE_SUN4M_IOMMU);
286 qdev_prop_set_uint32(dev, "version", version);
287 s = SYS_BUS_DEVICE(dev);
288 sysbus_realize_and_unref(s, &error_fatal);
289 sysbus_connect_irq(s, 0, irq);
290 sysbus_mmio_map(s, 0, addr);
291
292 return s;
293 }
294
sparc32_dma_init(hwaddr dma_base,hwaddr esp_base,qemu_irq espdma_irq,hwaddr le_base,qemu_irq ledma_irq,MACAddr * mac)295 static void *sparc32_dma_init(hwaddr dma_base,
296 hwaddr esp_base, qemu_irq espdma_irq,
297 hwaddr le_base, qemu_irq ledma_irq,
298 MACAddr *mac)
299 {
300 DeviceState *dma;
301 ESPDMADeviceState *espdma;
302 LEDMADeviceState *ledma;
303 SysBusESPState *esp;
304 SysBusPCNetState *lance;
305 NICInfo *nd = qemu_find_nic_info("lance", true, NULL);
306
307 dma = qdev_new(TYPE_SPARC32_DMA);
308 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
309 OBJECT(dma), "espdma"));
310
311 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
312
313 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
314 OBJECT(dma), "ledma"));
315
316 lance = SYSBUS_PCNET(object_resolve_path_component(
317 OBJECT(ledma), "lance"));
318
319 if (nd) {
320 qdev_set_nic_properties(DEVICE(lance), nd);
321 memcpy(mac->a, nd->macaddr.a, sizeof(mac->a));
322 } else {
323 qemu_macaddr_default_if_unset(mac);
324 qdev_prop_set_macaddr(DEVICE(lance), "mac", mac->a);
325 }
326
327 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
328
329 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
330
331 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
332
333 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
334
335 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
336 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
337
338 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
339
340 return dma;
341 }
342
slavio_intctl_init(hwaddr addr,hwaddr addrg,qemu_irq ** parent_irq)343 static DeviceState *slavio_intctl_init(hwaddr addr,
344 hwaddr addrg,
345 qemu_irq **parent_irq)
346 {
347 DeviceState *dev;
348 SysBusDevice *s;
349 unsigned int i, j;
350
351 dev = qdev_new("slavio_intctl");
352
353 s = SYS_BUS_DEVICE(dev);
354 sysbus_realize_and_unref(s, &error_fatal);
355
356 for (i = 0; i < MAX_CPUS; i++) {
357 for (j = 0; j < MAX_PILS; j++) {
358 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
359 }
360 }
361 sysbus_mmio_map(s, 0, addrg);
362 for (i = 0; i < MAX_CPUS; i++) {
363 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
364 }
365
366 return dev;
367 }
368
369 #define SYS_TIMER_OFFSET 0x10000ULL
370 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
371
slavio_timer_init_all(hwaddr addr,qemu_irq master_irq,qemu_irq * cpu_irqs,unsigned int num_cpus)372 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
373 qemu_irq *cpu_irqs, unsigned int num_cpus)
374 {
375 DeviceState *dev;
376 SysBusDevice *s;
377 unsigned int i;
378
379 dev = qdev_new("slavio_timer");
380 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
381 s = SYS_BUS_DEVICE(dev);
382 sysbus_realize_and_unref(s, &error_fatal);
383 sysbus_connect_irq(s, 0, master_irq);
384 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
385
386 for (i = 0; i < MAX_CPUS; i++) {
387 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
388 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
389 }
390 }
391
392 static qemu_irq slavio_system_powerdown;
393
slavio_powerdown_req(Notifier * n,void * opaque)394 static void slavio_powerdown_req(Notifier *n, void *opaque)
395 {
396 qemu_irq_raise(slavio_system_powerdown);
397 }
398
399 static Notifier slavio_system_powerdown_notifier = {
400 .notify = slavio_powerdown_req
401 };
402
403 #define MISC_LEDS 0x01600000
404 #define MISC_CFG 0x01800000
405 #define MISC_DIAG 0x01a00000
406 #define MISC_MDM 0x01b00000
407 #define MISC_SYS 0x01f00000
408
slavio_misc_init(hwaddr base,hwaddr aux1_base,hwaddr aux2_base,qemu_irq irq,qemu_irq fdc_tc)409 static void slavio_misc_init(hwaddr base,
410 hwaddr aux1_base,
411 hwaddr aux2_base, qemu_irq irq,
412 qemu_irq fdc_tc)
413 {
414 DeviceState *dev;
415 SysBusDevice *s;
416
417 dev = qdev_new("slavio_misc");
418 s = SYS_BUS_DEVICE(dev);
419 sysbus_realize_and_unref(s, &error_fatal);
420 if (base) {
421 /* 8 bit registers */
422 /* Slavio control */
423 sysbus_mmio_map(s, 0, base + MISC_CFG);
424 /* Diagnostics */
425 sysbus_mmio_map(s, 1, base + MISC_DIAG);
426 /* Modem control */
427 sysbus_mmio_map(s, 2, base + MISC_MDM);
428 /* 16 bit registers */
429 /* ss600mp diag LEDs */
430 sysbus_mmio_map(s, 3, base + MISC_LEDS);
431 /* 32 bit registers */
432 /* System control */
433 sysbus_mmio_map(s, 4, base + MISC_SYS);
434 }
435 if (aux1_base) {
436 /* AUX 1 (Misc System Functions) */
437 sysbus_mmio_map(s, 5, aux1_base);
438 }
439 if (aux2_base) {
440 /* AUX 2 (Software Powerdown Control) */
441 sysbus_mmio_map(s, 6, aux2_base);
442 }
443 sysbus_connect_irq(s, 0, irq);
444 sysbus_connect_irq(s, 1, fdc_tc);
445 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
446 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
447 }
448
ecc_init(hwaddr base,qemu_irq irq,uint32_t version)449 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
450 {
451 DeviceState *dev;
452 SysBusDevice *s;
453
454 dev = qdev_new("eccmemctl");
455 qdev_prop_set_uint32(dev, "version", version);
456 s = SYS_BUS_DEVICE(dev);
457 sysbus_realize_and_unref(s, &error_fatal);
458 sysbus_connect_irq(s, 0, irq);
459 sysbus_mmio_map(s, 0, base);
460 if (version == 0) { // SS-600MP only
461 sysbus_mmio_map(s, 1, base + 0x1000);
462 }
463 }
464
apc_init(hwaddr power_base,qemu_irq cpu_halt)465 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
466 {
467 DeviceState *dev;
468 SysBusDevice *s;
469
470 dev = qdev_new("apc");
471 s = SYS_BUS_DEVICE(dev);
472 sysbus_realize_and_unref(s, &error_fatal);
473 /* Power management (APC) XXX: not a Slavio device */
474 sysbus_mmio_map(s, 0, power_base);
475 sysbus_connect_irq(s, 0, cpu_halt);
476 }
477
tcx_init(hwaddr addr,qemu_irq irq,int vram_size,int width,int height,int depth)478 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
479 int height, int depth)
480 {
481 DeviceState *dev;
482 SysBusDevice *s;
483
484 dev = qdev_new("sun-tcx");
485 qdev_prop_set_uint32(dev, "vram_size", vram_size);
486 qdev_prop_set_uint16(dev, "width", width);
487 qdev_prop_set_uint16(dev, "height", height);
488 qdev_prop_set_uint16(dev, "depth", depth);
489 s = SYS_BUS_DEVICE(dev);
490 sysbus_realize_and_unref(s, &error_fatal);
491
492 /* 10/ROM : FCode ROM */
493 sysbus_mmio_map(s, 0, addr);
494 /* 2/STIP : Stipple */
495 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
496 /* 3/BLIT : Blitter */
497 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
498 /* 5/RSTIP : Raw Stipple */
499 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
500 /* 6/RBLIT : Raw Blitter */
501 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
502 /* 7/TEC : Transform Engine */
503 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
504 /* 8/CMAP : DAC */
505 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
506 /* 9/THC : */
507 if (depth == 8) {
508 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
509 } else {
510 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
511 }
512 /* 11/DHC : */
513 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
514 /* 12/ALT : */
515 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
516 /* 0/DFB8 : 8-bit plane */
517 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
518 /* 1/DFB24 : 24bit plane */
519 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
520 /* 4/RDFB32: Raw framebuffer. Control plane */
521 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
522 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
523 if (depth == 8) {
524 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
525 }
526
527 sysbus_connect_irq(s, 0, irq);
528 }
529
cg3_init(hwaddr addr,qemu_irq irq,int vram_size,int width,int height,int depth)530 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
531 int height, int depth)
532 {
533 DeviceState *dev;
534 SysBusDevice *s;
535
536 dev = qdev_new("cgthree");
537 qdev_prop_set_uint32(dev, "vram-size", vram_size);
538 qdev_prop_set_uint16(dev, "width", width);
539 qdev_prop_set_uint16(dev, "height", height);
540 qdev_prop_set_uint16(dev, "depth", depth);
541 s = SYS_BUS_DEVICE(dev);
542 sysbus_realize_and_unref(s, &error_fatal);
543
544 /* FCode ROM */
545 sysbus_mmio_map(s, 0, addr);
546 /* DAC */
547 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
548 /* 8-bit plane */
549 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
550
551 sysbus_connect_irq(s, 0, irq);
552 }
553
554 /* NCR89C100/MACIO Internal ID register */
555
556 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
557
558 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
559
idreg_init(hwaddr addr)560 static void idreg_init(hwaddr addr)
561 {
562 DeviceState *dev;
563 SysBusDevice *s;
564
565 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
566 s = SYS_BUS_DEVICE(dev);
567 sysbus_realize_and_unref(s, &error_fatal);
568
569 sysbus_mmio_map(s, 0, addr);
570 address_space_write_rom(&address_space_memory, addr,
571 MEMTXATTRS_UNSPECIFIED,
572 idreg_data, sizeof(idreg_data));
573 }
574
575 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
576
577 struct IDRegState {
578 SysBusDevice parent_obj;
579
580 MemoryRegion mem;
581 };
582
idreg_realize(DeviceState * ds,Error ** errp)583 static void idreg_realize(DeviceState *ds, Error **errp)
584 {
585 IDRegState *s = MACIO_ID_REGISTER(ds);
586 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
587
588 if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
589 sizeof(idreg_data), errp)) {
590 return;
591 }
592
593 vmstate_register_ram_global(&s->mem);
594 memory_region_set_readonly(&s->mem, true);
595 sysbus_init_mmio(dev, &s->mem);
596 }
597
idreg_class_init(ObjectClass * oc,const void * data)598 static void idreg_class_init(ObjectClass *oc, const void *data)
599 {
600 DeviceClass *dc = DEVICE_CLASS(oc);
601
602 dc->realize = idreg_realize;
603 }
604
605 static const TypeInfo idreg_info = {
606 .name = TYPE_MACIO_ID_REGISTER,
607 .parent = TYPE_SYS_BUS_DEVICE,
608 .instance_size = sizeof(IDRegState),
609 .class_init = idreg_class_init,
610 };
611
612 #define TYPE_TCX_AFX "tcx_afx"
613 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
614
615 struct AFXState {
616 SysBusDevice parent_obj;
617
618 MemoryRegion mem;
619 };
620
621 /* SS-5 TCX AFX register */
afx_init(hwaddr addr)622 static void afx_init(hwaddr addr)
623 {
624 DeviceState *dev;
625 SysBusDevice *s;
626
627 dev = qdev_new(TYPE_TCX_AFX);
628 s = SYS_BUS_DEVICE(dev);
629 sysbus_realize_and_unref(s, &error_fatal);
630
631 sysbus_mmio_map(s, 0, addr);
632 }
633
afx_realize(DeviceState * ds,Error ** errp)634 static void afx_realize(DeviceState *ds, Error **errp)
635 {
636 AFXState *s = TCX_AFX(ds);
637 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
638
639 if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx",
640 4, errp)) {
641 return;
642 }
643
644 vmstate_register_ram_global(&s->mem);
645 sysbus_init_mmio(dev, &s->mem);
646 }
647
afx_class_init(ObjectClass * oc,const void * data)648 static void afx_class_init(ObjectClass *oc, const void *data)
649 {
650 DeviceClass *dc = DEVICE_CLASS(oc);
651
652 dc->realize = afx_realize;
653 }
654
655 static const TypeInfo afx_info = {
656 .name = TYPE_TCX_AFX,
657 .parent = TYPE_SYS_BUS_DEVICE,
658 .instance_size = sizeof(AFXState),
659 .class_init = afx_class_init,
660 };
661
662 #define TYPE_OPENPROM "openprom"
663 typedef struct PROMState PROMState;
664 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
665 TYPE_OPENPROM)
666
667 struct PROMState {
668 SysBusDevice parent_obj;
669
670 MemoryRegion prom;
671 };
672
673 /* Boot PROM (OpenBIOS) */
translate_prom_address(void * opaque,uint64_t addr)674 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
675 {
676 hwaddr *base_addr = (hwaddr *)opaque;
677 return addr + *base_addr - PROM_VADDR;
678 }
679
prom_init(hwaddr addr,const char * bios_name)680 static void prom_init(hwaddr addr, const char *bios_name)
681 {
682 DeviceState *dev;
683 SysBusDevice *s;
684 char *filename;
685 int ret;
686
687 dev = qdev_new(TYPE_OPENPROM);
688 s = SYS_BUS_DEVICE(dev);
689 sysbus_realize_and_unref(s, &error_fatal);
690
691 sysbus_mmio_map(s, 0, addr);
692
693 /* load boot prom */
694 if (bios_name == NULL) {
695 bios_name = PROM_FILENAME;
696 }
697 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
698 if (filename) {
699 ret = load_elf(filename, NULL,
700 translate_prom_address, &addr, NULL,
701 NULL, NULL, NULL, ELFDATA2MSB, EM_SPARC, 0, 0);
702 if (ret < 0 || ret > PROM_SIZE_MAX) {
703 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
704 }
705 g_free(filename);
706 } else {
707 ret = -1;
708 }
709 if (ret < 0 || ret > PROM_SIZE_MAX) {
710 error_report("could not load prom '%s'", bios_name);
711 exit(1);
712 }
713 }
714
prom_realize(DeviceState * ds,Error ** errp)715 static void prom_realize(DeviceState *ds, Error **errp)
716 {
717 PROMState *s = OPENPROM(ds);
718 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
719
720 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
721 PROM_SIZE_MAX, errp)) {
722 return;
723 }
724
725 vmstate_register_ram_global(&s->prom);
726 memory_region_set_readonly(&s->prom, true);
727 sysbus_init_mmio(dev, &s->prom);
728 }
729
prom_class_init(ObjectClass * klass,const void * data)730 static void prom_class_init(ObjectClass *klass, const void *data)
731 {
732 DeviceClass *dc = DEVICE_CLASS(klass);
733
734 dc->realize = prom_realize;
735 }
736
737 static const TypeInfo prom_info = {
738 .name = TYPE_OPENPROM,
739 .parent = TYPE_SYS_BUS_DEVICE,
740 .instance_size = sizeof(PROMState),
741 .class_init = prom_class_init,
742 };
743
744 #define TYPE_SUN4M_MEMORY "memory"
745 typedef struct RamDevice RamDevice;
746 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
747 TYPE_SUN4M_MEMORY)
748
749 struct RamDevice {
750 SysBusDevice parent_obj;
751 HostMemoryBackend *memdev;
752 };
753
754 /* System RAM */
ram_realize(DeviceState * dev,Error ** errp)755 static void ram_realize(DeviceState *dev, Error **errp)
756 {
757 RamDevice *d = SUN4M_RAM(dev);
758 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
759
760 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
761 }
762
ram_initfn(Object * obj)763 static void ram_initfn(Object *obj)
764 {
765 RamDevice *d = SUN4M_RAM(obj);
766 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
767 (Object **)&d->memdev,
768 object_property_allow_set_link,
769 OBJ_PROP_LINK_STRONG);
770 object_property_set_description(obj, "memdev", "Set RAM backend"
771 "Valid value is ID of a hostmem backend");
772 }
773
ram_class_init(ObjectClass * klass,const void * data)774 static void ram_class_init(ObjectClass *klass, const void *data)
775 {
776 DeviceClass *dc = DEVICE_CLASS(klass);
777
778 dc->realize = ram_realize;
779 }
780
781 static const TypeInfo ram_info = {
782 .name = TYPE_SUN4M_MEMORY,
783 .parent = TYPE_SYS_BUS_DEVICE,
784 .instance_size = sizeof(RamDevice),
785 .instance_init = ram_initfn,
786 .class_init = ram_class_init,
787 };
788
cpu_devinit(const char * cpu_type,unsigned int id,uint64_t prom_addr,qemu_irq ** cpu_irqs)789 static void cpu_devinit(const char *cpu_type, unsigned int id,
790 uint64_t prom_addr, qemu_irq **cpu_irqs)
791 {
792 SPARCCPU *cpu;
793 CPUSPARCState *env;
794
795 cpu = SPARC_CPU(object_new(cpu_type));
796 env = &cpu->env;
797
798 qemu_register_reset(sun4m_cpu_reset, cpu);
799 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
800 &error_abort);
801 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
802 cpu_sparc_set_id(env, id);
803 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
804 env->prom_addr = prom_addr;
805 }
806
dummy_fdc_tc(void * opaque,int irq,int level)807 static void dummy_fdc_tc(void *opaque, int irq, int level)
808 {
809 }
810
sun4m_hw_init(MachineState * machine)811 static void sun4m_hw_init(MachineState *machine)
812 {
813 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef;
814 DeviceState *slavio_intctl;
815 unsigned int i;
816 Nvram *nvram;
817 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
818 qemu_irq fdc_tc;
819 unsigned long kernel_size;
820 uint32_t initrd_size;
821 DriveInfo *fd[MAX_FD];
822 FWCfgState *fw_cfg;
823 DeviceState *dev, *ms_kb_orgate, *serial_orgate;
824 SysBusDevice *s;
825 unsigned int smp_cpus = machine->smp.cpus;
826 unsigned int max_cpus = machine->smp.max_cpus;
827 HostMemoryBackend *ram_memdev = machine->memdev;
828 MACAddr hostid;
829
830 if (machine->ram_size > hwdef->max_mem) {
831 error_report("Too much memory for this machine: %" PRId64 ","
832 " maximum %" PRId64,
833 machine->ram_size / MiB, hwdef->max_mem / MiB);
834 exit(1);
835 }
836
837 /* init CPUs */
838 for(i = 0; i < smp_cpus; i++) {
839 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
840 }
841
842 for (i = smp_cpus; i < MAX_CPUS; i++)
843 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
844
845 /* Create and map RAM frontend */
846 dev = qdev_new("memory");
847 object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal);
848 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
849 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
850
851 /* models without ECC don't trap when missing ram is accessed */
852 if (!hwdef->ecc_base) {
853 empty_slot_init("ecc", machine->ram_size,
854 hwdef->max_mem - machine->ram_size);
855 }
856
857 prom_init(hwdef->slavio_base, machine->firmware);
858
859 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
860 hwdef->intctl_base + 0x10000ULL,
861 cpu_irqs);
862
863 for (i = 0; i < 32; i++) {
864 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
865 }
866 for (i = 0; i < MAX_CPUS; i++) {
867 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
868 }
869
870 if (hwdef->idreg_base) {
871 idreg_init(hwdef->idreg_base);
872 }
873
874 if (hwdef->afx_base) {
875 afx_init(hwdef->afx_base);
876 }
877
878 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
879
880 if (hwdef->iommu_pad_base) {
881 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
882 Software shouldn't use aliased addresses, neither should it crash
883 when does. Using empty_slot instead of aliasing can help with
884 debugging such accesses */
885 empty_slot_init("iommu.alias",
886 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
887 }
888
889 sparc32_dma_init(hwdef->dma_base,
890 hwdef->esp_base, slavio_irq[18],
891 hwdef->le_base, slavio_irq[16], &hostid);
892
893 if (graphic_depth != 8 && graphic_depth != 24) {
894 error_report("Unsupported depth: %d", graphic_depth);
895 exit (1);
896 }
897 if (vga_interface_type != VGA_NONE) {
898 if (vga_interface_type == VGA_CG3) {
899 if (graphic_depth != 8) {
900 error_report("Unsupported depth: %d", graphic_depth);
901 exit(1);
902 }
903
904 if (!(graphic_width == 1024 && graphic_height == 768) &&
905 !(graphic_width == 1152 && graphic_height == 900)) {
906 error_report("Unsupported resolution: %d x %d", graphic_width,
907 graphic_height);
908 exit(1);
909 }
910
911 /* sbus irq 5 */
912 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
913 graphic_width, graphic_height, graphic_depth);
914 vga_interface_created = true;
915 } else {
916 /* If no display specified, default to TCX */
917 if (graphic_depth != 8 && graphic_depth != 24) {
918 error_report("Unsupported depth: %d", graphic_depth);
919 exit(1);
920 }
921
922 if (!(graphic_width == 1024 && graphic_height == 768)) {
923 error_report("Unsupported resolution: %d x %d",
924 graphic_width, graphic_height);
925 exit(1);
926 }
927
928 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
929 graphic_width, graphic_height, graphic_depth);
930 vga_interface_created = true;
931 }
932 }
933
934 for (i = 0; i < MAX_VSIMMS; i++) {
935 /* vsimm registers probed by OBP */
936 if (hwdef->vsimm[i].reg_base) {
937 char *name = g_strdup_printf("vsimm[%d]", i);
938 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
939 g_free(name);
940 }
941 }
942
943 if (hwdef->sx_base) {
944 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000);
945 }
946
947 dev = qdev_new("sysbus-m48t08");
948 qdev_prop_set_int32(dev, "base-year", 1968);
949 s = SYS_BUS_DEVICE(dev);
950 sysbus_realize_and_unref(s, &error_fatal);
951 sysbus_connect_irq(s, 0, slavio_irq[0]);
952 sysbus_mmio_map(s, 0, hwdef->nvram_base);
953 nvram = NVRAM(dev);
954
955 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
956
957 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
958 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
959 dev = qdev_new(TYPE_ESCC);
960 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
961 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
962 qdev_prop_set_uint32(dev, "it_shift", 1);
963 qdev_prop_set_chr(dev, "chrB", NULL);
964 qdev_prop_set_chr(dev, "chrA", NULL);
965 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
966 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
967 s = SYS_BUS_DEVICE(dev);
968 sysbus_realize_and_unref(s, &error_fatal);
969 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
970
971 /* Logically OR both its IRQs together */
972 ms_kb_orgate = qdev_new(TYPE_OR_IRQ);
973 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal);
974 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal);
975 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0));
976 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1));
977 qdev_connect_gpio_out(ms_kb_orgate, 0, slavio_irq[14]);
978
979 dev = qdev_new(TYPE_ESCC);
980 qdev_prop_set_uint32(dev, "disabled", 0);
981 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
982 qdev_prop_set_uint32(dev, "it_shift", 1);
983 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
984 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
985 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
986 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
987
988 s = SYS_BUS_DEVICE(dev);
989 sysbus_realize_and_unref(s, &error_fatal);
990 sysbus_mmio_map(s, 0, hwdef->serial_base);
991
992 /* Logically OR both its IRQs together */
993 serial_orgate = qdev_new(TYPE_OR_IRQ);
994 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2,
995 &error_fatal);
996 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal);
997 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0));
998 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1));
999 qdev_connect_gpio_out(serial_orgate, 0, slavio_irq[15]);
1000
1001 if (hwdef->apc_base) {
1002 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1003 }
1004
1005 if (hwdef->fd_base) {
1006 /* there is zero or one floppy drive */
1007 memset(fd, 0, sizeof(fd));
1008 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1009 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1010 &fdc_tc);
1011 } else {
1012 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1013 }
1014
1015 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1016 slavio_irq[30], fdc_tc);
1017
1018 if (hwdef->cs_base) {
1019 sysbus_create_simple("sun-CS4231", hwdef->cs_base,
1020 slavio_irq[5]);
1021 }
1022
1023 if (hwdef->dbri_base) {
1024 /* ISDN chip with attached CS4215 audio codec */
1025 /* prom space */
1026 create_unimplemented_device("sun-DBRI.prom",
1027 hwdef->dbri_base + 0x1000, 0x30);
1028 /* reg space */
1029 create_unimplemented_device("sun-DBRI",
1030 hwdef->dbri_base + 0x10000, 0x100);
1031 }
1032
1033 if (hwdef->bpp_base) {
1034 /* parallel port */
1035 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20);
1036 }
1037
1038 initrd_size = 0;
1039 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1040 machine->initrd_filename,
1041 machine->ram_size, &initrd_size);
1042
1043 nvram_init(nvram, hostid.a, machine->kernel_cmdline,
1044 machine->boot_config.order, machine->ram_size, kernel_size,
1045 graphic_width, graphic_height, graphic_depth,
1046 hwdef->nvram_machine_id, "Sun4m");
1047
1048 if (hwdef->ecc_base)
1049 ecc_init(hwdef->ecc_base, slavio_irq[28],
1050 hwdef->ecc_version);
1051
1052 dev = qdev_new(TYPE_FW_CFG_MEM);
1053 fw_cfg = FW_CFG(dev);
1054 qdev_prop_set_uint32(dev, "data_width", 1);
1055 qdev_prop_set_bit(dev, "dma_enabled", false);
1056 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1057 OBJECT(fw_cfg));
1058 s = SYS_BUS_DEVICE(dev);
1059 sysbus_realize_and_unref(s, &error_fatal);
1060 sysbus_mmio_map(s, 0, CFG_ADDR);
1061 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1062
1063 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1064 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1065 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1066 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1067 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1068 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1069 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1070 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1071 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1072 if (machine->kernel_cmdline) {
1073 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1074 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1075 machine->kernel_cmdline);
1076 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1077 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1078 strlen(machine->kernel_cmdline) + 1);
1079 } else {
1080 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1081 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1082 }
1083 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1084 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1085 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]);
1086 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1087 }
1088
1089 enum {
1090 ss5_id = 32,
1091 vger_id,
1092 lx_id,
1093 ss4_id,
1094 scls_id,
1095 sbook_id,
1096 ss10_id = 64,
1097 ss20_id,
1098 ss600mp_id,
1099 };
1100
sun4m_machine_class_init(ObjectClass * oc,const void * data)1101 static void sun4m_machine_class_init(ObjectClass *oc, const void *data)
1102 {
1103 MachineClass *mc = MACHINE_CLASS(oc);
1104
1105 mc->init = sun4m_hw_init;
1106 mc->block_default_type = IF_SCSI;
1107 mc->default_boot_order = "c";
1108 mc->default_display = "tcx";
1109 mc->default_ram_id = "sun4m.ram";
1110 }
1111
ss5_class_init(ObjectClass * oc,const void * data)1112 static void ss5_class_init(ObjectClass *oc, const void *data)
1113 {
1114 MachineClass *mc = MACHINE_CLASS(oc);
1115 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1116 static const struct sun4m_hwdef ss5_hwdef = {
1117 .iommu_base = 0x10000000,
1118 .iommu_pad_base = 0x10004000,
1119 .iommu_pad_len = 0x0fffb000,
1120 .tcx_base = 0x50000000,
1121 .cs_base = 0x6c000000,
1122 .slavio_base = 0x70000000,
1123 .ms_kb_base = 0x71000000,
1124 .serial_base = 0x71100000,
1125 .nvram_base = 0x71200000,
1126 .fd_base = 0x71400000,
1127 .counter_base = 0x71d00000,
1128 .intctl_base = 0x71e00000,
1129 .idreg_base = 0x78000000,
1130 .dma_base = 0x78400000,
1131 .esp_base = 0x78800000,
1132 .le_base = 0x78c00000,
1133 .apc_base = 0x6a000000,
1134 .afx_base = 0x6e000000,
1135 .aux1_base = 0x71900000,
1136 .aux2_base = 0x71910000,
1137 .nvram_machine_id = 0x80,
1138 .machine_id = ss5_id,
1139 .iommu_version = 0x05000000,
1140 .max_mem = 0x10000000,
1141 };
1142
1143 mc->desc = "Sun4m platform, SPARCstation 5";
1144 mc->is_default = true;
1145 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1146 smc->hwdef = &ss5_hwdef;
1147 }
1148
ss10_class_init(ObjectClass * oc,const void * data)1149 static void ss10_class_init(ObjectClass *oc, const void *data)
1150 {
1151 MachineClass *mc = MACHINE_CLASS(oc);
1152 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1153 static const struct sun4m_hwdef ss10_hwdef = {
1154 .iommu_base = 0xfe0000000ULL,
1155 .tcx_base = 0xe20000000ULL,
1156 .slavio_base = 0xff0000000ULL,
1157 .ms_kb_base = 0xff1000000ULL,
1158 .serial_base = 0xff1100000ULL,
1159 .nvram_base = 0xff1200000ULL,
1160 .fd_base = 0xff1700000ULL,
1161 .counter_base = 0xff1300000ULL,
1162 .intctl_base = 0xff1400000ULL,
1163 .idreg_base = 0xef0000000ULL,
1164 .dma_base = 0xef0400000ULL,
1165 .esp_base = 0xef0800000ULL,
1166 .le_base = 0xef0c00000ULL,
1167 .apc_base = 0xefa000000ULL, /* XXX should not exist */
1168 .aux1_base = 0xff1800000ULL,
1169 .aux2_base = 0xff1a01000ULL,
1170 .ecc_base = 0xf00000000ULL,
1171 .ecc_version = 0x10000000, /* version 0, implementation 1 */
1172 .nvram_machine_id = 0x72,
1173 .machine_id = ss10_id,
1174 .iommu_version = 0x03000000,
1175 .max_mem = 0xf00000000ULL,
1176 };
1177
1178 mc->desc = "Sun4m platform, SPARCstation 10";
1179 mc->max_cpus = 4;
1180 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1181 smc->hwdef = &ss10_hwdef;
1182 }
1183
ss600mp_class_init(ObjectClass * oc,const void * data)1184 static void ss600mp_class_init(ObjectClass *oc, const void *data)
1185 {
1186 MachineClass *mc = MACHINE_CLASS(oc);
1187 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1188 static const struct sun4m_hwdef ss600mp_hwdef = {
1189 .iommu_base = 0xfe0000000ULL,
1190 .tcx_base = 0xe20000000ULL,
1191 .slavio_base = 0xff0000000ULL,
1192 .ms_kb_base = 0xff1000000ULL,
1193 .serial_base = 0xff1100000ULL,
1194 .nvram_base = 0xff1200000ULL,
1195 .counter_base = 0xff1300000ULL,
1196 .intctl_base = 0xff1400000ULL,
1197 .dma_base = 0xef0081000ULL,
1198 .esp_base = 0xef0080000ULL,
1199 .le_base = 0xef0060000ULL,
1200 .apc_base = 0xefa000000ULL, /* XXX should not exist */
1201 .aux1_base = 0xff1800000ULL,
1202 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */
1203 .ecc_base = 0xf00000000ULL,
1204 .ecc_version = 0x00000000, /* version 0, implementation 0 */
1205 .nvram_machine_id = 0x71,
1206 .machine_id = ss600mp_id,
1207 .iommu_version = 0x01000000,
1208 .max_mem = 0xf00000000ULL,
1209 };
1210
1211 mc->desc = "Sun4m platform, SPARCserver 600MP";
1212 mc->max_cpus = 4;
1213 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1214 smc->hwdef = &ss600mp_hwdef;
1215 }
1216
ss20_class_init(ObjectClass * oc,const void * data)1217 static void ss20_class_init(ObjectClass *oc, const void *data)
1218 {
1219 MachineClass *mc = MACHINE_CLASS(oc);
1220 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1221 static const struct sun4m_hwdef ss20_hwdef = {
1222 .iommu_base = 0xfe0000000ULL,
1223 .tcx_base = 0xe20000000ULL,
1224 .slavio_base = 0xff0000000ULL,
1225 .ms_kb_base = 0xff1000000ULL,
1226 .serial_base = 0xff1100000ULL,
1227 .nvram_base = 0xff1200000ULL,
1228 .fd_base = 0xff1700000ULL,
1229 .counter_base = 0xff1300000ULL,
1230 .intctl_base = 0xff1400000ULL,
1231 .idreg_base = 0xef0000000ULL,
1232 .dma_base = 0xef0400000ULL,
1233 .esp_base = 0xef0800000ULL,
1234 .le_base = 0xef0c00000ULL,
1235 .bpp_base = 0xef4800000ULL,
1236 .apc_base = 0xefa000000ULL, /* XXX should not exist */
1237 .aux1_base = 0xff1800000ULL,
1238 .aux2_base = 0xff1a01000ULL,
1239 .dbri_base = 0xee0000000ULL,
1240 .sx_base = 0xf80000000ULL,
1241 .vsimm = {
1242 {
1243 .reg_base = 0x9c000000ULL,
1244 .vram_base = 0xfc000000ULL
1245 }, {
1246 .reg_base = 0x90000000ULL,
1247 .vram_base = 0xf0000000ULL
1248 }, {
1249 .reg_base = 0x94000000ULL
1250 }, {
1251 .reg_base = 0x98000000ULL
1252 }
1253 },
1254 .ecc_base = 0xf00000000ULL,
1255 .ecc_version = 0x20000000, /* version 0, implementation 2 */
1256 .nvram_machine_id = 0x72,
1257 .machine_id = ss20_id,
1258 .iommu_version = 0x13000000,
1259 .max_mem = 0xf00000000ULL,
1260 };
1261
1262 mc->desc = "Sun4m platform, SPARCstation 20";
1263 mc->max_cpus = 4;
1264 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1265 smc->hwdef = &ss20_hwdef;
1266 }
1267
voyager_class_init(ObjectClass * oc,const void * data)1268 static void voyager_class_init(ObjectClass *oc, const void *data)
1269 {
1270 MachineClass *mc = MACHINE_CLASS(oc);
1271 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1272 static const struct sun4m_hwdef voyager_hwdef = {
1273 .iommu_base = 0x10000000,
1274 .tcx_base = 0x50000000,
1275 .slavio_base = 0x70000000,
1276 .ms_kb_base = 0x71000000,
1277 .serial_base = 0x71100000,
1278 .nvram_base = 0x71200000,
1279 .fd_base = 0x71400000,
1280 .counter_base = 0x71d00000,
1281 .intctl_base = 0x71e00000,
1282 .idreg_base = 0x78000000,
1283 .dma_base = 0x78400000,
1284 .esp_base = 0x78800000,
1285 .le_base = 0x78c00000,
1286 .apc_base = 0x71300000, /* pmc */
1287 .aux1_base = 0x71900000,
1288 .aux2_base = 0x71910000,
1289 .nvram_machine_id = 0x80,
1290 .machine_id = vger_id,
1291 .iommu_version = 0x05000000,
1292 .max_mem = 0x10000000,
1293 };
1294
1295 mc->desc = "Sun4m platform, SPARCstation Voyager";
1296 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1297 smc->hwdef = &voyager_hwdef;
1298 }
1299
ss_lx_class_init(ObjectClass * oc,const void * data)1300 static void ss_lx_class_init(ObjectClass *oc, const void *data)
1301 {
1302 MachineClass *mc = MACHINE_CLASS(oc);
1303 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1304 static const struct sun4m_hwdef ss_lx_hwdef = {
1305 .iommu_base = 0x10000000,
1306 .iommu_pad_base = 0x10004000,
1307 .iommu_pad_len = 0x0fffb000,
1308 .tcx_base = 0x50000000,
1309 .slavio_base = 0x70000000,
1310 .ms_kb_base = 0x71000000,
1311 .serial_base = 0x71100000,
1312 .nvram_base = 0x71200000,
1313 .fd_base = 0x71400000,
1314 .counter_base = 0x71d00000,
1315 .intctl_base = 0x71e00000,
1316 .idreg_base = 0x78000000,
1317 .dma_base = 0x78400000,
1318 .esp_base = 0x78800000,
1319 .le_base = 0x78c00000,
1320 .aux1_base = 0x71900000,
1321 .aux2_base = 0x71910000,
1322 .nvram_machine_id = 0x80,
1323 .machine_id = lx_id,
1324 .iommu_version = 0x04000000,
1325 .max_mem = 0x10000000,
1326 };
1327
1328 mc->desc = "Sun4m platform, SPARCstation LX";
1329 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1330 smc->hwdef = &ss_lx_hwdef;
1331 }
1332
ss4_class_init(ObjectClass * oc,const void * data)1333 static void ss4_class_init(ObjectClass *oc, const void *data)
1334 {
1335 MachineClass *mc = MACHINE_CLASS(oc);
1336 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1337 static const struct sun4m_hwdef ss4_hwdef = {
1338 .iommu_base = 0x10000000,
1339 .tcx_base = 0x50000000,
1340 .cs_base = 0x6c000000,
1341 .slavio_base = 0x70000000,
1342 .ms_kb_base = 0x71000000,
1343 .serial_base = 0x71100000,
1344 .nvram_base = 0x71200000,
1345 .fd_base = 0x71400000,
1346 .counter_base = 0x71d00000,
1347 .intctl_base = 0x71e00000,
1348 .idreg_base = 0x78000000,
1349 .dma_base = 0x78400000,
1350 .esp_base = 0x78800000,
1351 .le_base = 0x78c00000,
1352 .apc_base = 0x6a000000,
1353 .aux1_base = 0x71900000,
1354 .aux2_base = 0x71910000,
1355 .nvram_machine_id = 0x80,
1356 .machine_id = ss4_id,
1357 .iommu_version = 0x05000000,
1358 .max_mem = 0x10000000,
1359 };
1360
1361 mc->desc = "Sun4m platform, SPARCstation 4";
1362 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1363 smc->hwdef = &ss4_hwdef;
1364 }
1365
scls_class_init(ObjectClass * oc,const void * data)1366 static void scls_class_init(ObjectClass *oc, const void *data)
1367 {
1368 MachineClass *mc = MACHINE_CLASS(oc);
1369 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1370 static const struct sun4m_hwdef scls_hwdef = {
1371 .iommu_base = 0x10000000,
1372 .tcx_base = 0x50000000,
1373 .slavio_base = 0x70000000,
1374 .ms_kb_base = 0x71000000,
1375 .serial_base = 0x71100000,
1376 .nvram_base = 0x71200000,
1377 .fd_base = 0x71400000,
1378 .counter_base = 0x71d00000,
1379 .intctl_base = 0x71e00000,
1380 .idreg_base = 0x78000000,
1381 .dma_base = 0x78400000,
1382 .esp_base = 0x78800000,
1383 .le_base = 0x78c00000,
1384 .apc_base = 0x6a000000,
1385 .aux1_base = 0x71900000,
1386 .aux2_base = 0x71910000,
1387 .nvram_machine_id = 0x80,
1388 .machine_id = scls_id,
1389 .iommu_version = 0x05000000,
1390 .max_mem = 0x10000000,
1391 };
1392
1393 mc->desc = "Sun4m platform, SPARCClassic";
1394 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1395 smc->hwdef = &scls_hwdef;
1396 }
1397
sbook_class_init(ObjectClass * oc,const void * data)1398 static void sbook_class_init(ObjectClass *oc, const void *data)
1399 {
1400 MachineClass *mc = MACHINE_CLASS(oc);
1401 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
1402 static const struct sun4m_hwdef sbook_hwdef = {
1403 .iommu_base = 0x10000000,
1404 .tcx_base = 0x50000000, /* XXX */
1405 .slavio_base = 0x70000000,
1406 .ms_kb_base = 0x71000000,
1407 .serial_base = 0x71100000,
1408 .nvram_base = 0x71200000,
1409 .fd_base = 0x71400000,
1410 .counter_base = 0x71d00000,
1411 .intctl_base = 0x71e00000,
1412 .idreg_base = 0x78000000,
1413 .dma_base = 0x78400000,
1414 .esp_base = 0x78800000,
1415 .le_base = 0x78c00000,
1416 .apc_base = 0x6a000000,
1417 .aux1_base = 0x71900000,
1418 .aux2_base = 0x71910000,
1419 .nvram_machine_id = 0x80,
1420 .machine_id = sbook_id,
1421 .iommu_version = 0x05000000,
1422 .max_mem = 0x10000000,
1423 };
1424
1425 mc->desc = "Sun4m platform, SPARCbook";
1426 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1427 smc->hwdef = &sbook_hwdef;
1428 }
1429
1430 static const TypeInfo sun4m_machine_types[] = {
1431 {
1432 .name = MACHINE_TYPE_NAME("SS-5"),
1433 .parent = TYPE_SUN4M_MACHINE,
1434 .class_init = ss5_class_init,
1435 }, {
1436 .name = MACHINE_TYPE_NAME("SS-10"),
1437 .parent = TYPE_SUN4M_MACHINE,
1438 .class_init = ss10_class_init,
1439 }, {
1440 .name = MACHINE_TYPE_NAME("SS-600MP"),
1441 .parent = TYPE_SUN4M_MACHINE,
1442 .class_init = ss600mp_class_init,
1443 }, {
1444 .name = MACHINE_TYPE_NAME("SS-20"),
1445 .parent = TYPE_SUN4M_MACHINE,
1446 .class_init = ss20_class_init,
1447 }, {
1448 .name = MACHINE_TYPE_NAME("Voyager"),
1449 .parent = TYPE_SUN4M_MACHINE,
1450 .class_init = voyager_class_init,
1451 }, {
1452 .name = MACHINE_TYPE_NAME("LX"),
1453 .parent = TYPE_SUN4M_MACHINE,
1454 .class_init = ss_lx_class_init,
1455 }, {
1456 .name = MACHINE_TYPE_NAME("SS-4"),
1457 .parent = TYPE_SUN4M_MACHINE,
1458 .class_init = ss4_class_init,
1459 }, {
1460 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1461 .parent = TYPE_SUN4M_MACHINE,
1462 .class_init = scls_class_init,
1463 }, {
1464 .name = MACHINE_TYPE_NAME("SPARCbook"),
1465 .parent = TYPE_SUN4M_MACHINE,
1466 .class_init = sbook_class_init,
1467 }, {
1468 .name = TYPE_SUN4M_MACHINE,
1469 .parent = TYPE_MACHINE,
1470 .class_size = sizeof(Sun4mMachineClass),
1471 .class_init = sun4m_machine_class_init,
1472 .abstract = true,
1473 }
1474 };
1475
DEFINE_TYPES(sun4m_machine_types)1476 DEFINE_TYPES(sun4m_machine_types)
1477
1478 static void sun4m_register_types(void)
1479 {
1480 type_register_static(&idreg_info);
1481 type_register_static(&afx_info);
1482 type_register_static(&prom_info);
1483 type_register_static(&ram_info);
1484 }
1485
1486 type_init(sun4m_register_types)
1487