1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp25-rcc.h> 9#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 10#include <dt-bindings/phy/phy.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 power-domains = <&CPU_PD0>; 26 power-domain-names = "psci"; 27 }; 28 }; 29 30 arm-pmu { 31 compatible = "arm,cortex-a35-pmu"; 32 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 33 interrupt-affinity = <&cpu0>; 34 interrupt-parent = <&intc>; 35 }; 36 37 arm_wdt: watchdog { 38 compatible = "arm,smc-wdt"; 39 arm,smc-id = <0xb200005a>; 40 status = "disabled"; 41 }; 42 43 clocks { 44 clk_dsi_txbyte: txbyteclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <0>; 48 }; 49 50 clk_rcbsec: clk-rcbsec { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 }; 56 57 firmware { 58 optee: optee { 59 compatible = "linaro,optee-tz"; 60 method = "smc"; 61 interrupt-parent = <&intc>; 62 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 scmi { 66 compatible = "linaro,scmi-optee"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 linaro,optee-channel-id = <0>; 70 71 scmi_clk: protocol@14 { 72 reg = <0x14>; 73 #clock-cells = <1>; 74 }; 75 76 scmi_reset: protocol@16 { 77 reg = <0x16>; 78 #reset-cells = <1>; 79 }; 80 81 scmi_voltd: protocol@17 { 82 reg = <0x17>; 83 84 scmi_regu: regulators { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 scmi_vddio1: regulator@0 { 89 reg = <VOLTD_SCMI_VDDIO1>; 90 regulator-name = "vddio1"; 91 }; 92 scmi_vddio2: regulator@1 { 93 reg = <VOLTD_SCMI_VDDIO2>; 94 regulator-name = "vddio2"; 95 }; 96 scmi_vddio3: regulator@2 { 97 reg = <VOLTD_SCMI_VDDIO3>; 98 regulator-name = "vddio3"; 99 }; 100 scmi_vddio4: regulator@3 { 101 reg = <VOLTD_SCMI_VDDIO4>; 102 regulator-name = "vddio4"; 103 }; 104 scmi_vdd33ucpd: regulator@5 { 105 reg = <VOLTD_SCMI_UCPD>; 106 regulator-name = "vdd33ucpd"; 107 }; 108 scmi_vdda18adc: regulator@7 { 109 reg = <VOLTD_SCMI_ADC>; 110 regulator-name = "vdda18adc"; 111 }; 112 }; 113 }; 114 }; 115 }; 116 117 intc: interrupt-controller@4ac00000 { 118 compatible = "arm,gic-400"; 119 #interrupt-cells = <3>; 120 interrupt-controller; 121 reg = <0x0 0x4ac10000 0x0 0x1000>, 122 <0x0 0x4ac20000 0x0 0x20000>, 123 <0x0 0x4ac40000 0x0 0x20000>, 124 <0x0 0x4ac60000 0x0 0x20000>; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 131 CPU_PD0: power-domain-cpu0 { 132 #power-domain-cells = <0>; 133 power-domains = <&CLUSTER_PD>; 134 }; 135 136 CLUSTER_PD: power-domain-cluster { 137 #power-domain-cells = <0>; 138 power-domains = <&RET_PD>; 139 }; 140 141 RET_PD: power-domain-retention { 142 #power-domain-cells = <0>; 143 }; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupt-parent = <&intc>; 149 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 153 always-on; 154 }; 155 156 soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 interrupt-parent = <&intc>; 161 ranges = <0x0 0x0 0x0 0x80000000>; 162 163 hpdma: dma-controller@40400000 { 164 compatible = "st,stm32mp25-dma3"; 165 reg = <0x40400000 0x1000>; 166 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 183 #dma-cells = <3>; 184 }; 185 186 hpdma2: dma-controller@40410000 { 187 compatible = "st,stm32mp25-dma3"; 188 reg = <0x40410000 0x1000>; 189 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 206 #dma-cells = <3>; 207 }; 208 209 hpdma3: dma-controller@40420000 { 210 compatible = "st,stm32mp25-dma3"; 211 reg = <0x40420000 0x1000>; 212 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 229 #dma-cells = <3>; 230 }; 231 232 rifsc: bus@42080000 { 233 compatible = "st,stm32mp25-rifsc", "simple-bus"; 234 reg = <0x42080000 0x1000>; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 #access-controller-cells = <1>; 238 ranges; 239 240 i2s2: audio-controller@400b0000 { 241 compatible = "st,stm32mp25-i2s"; 242 reg = <0x400b0000 0x400>; 243 #sound-dai-cells = <0>; 244 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 246 clock-names = "pclk", "i2sclk"; 247 resets = <&rcc SPI2_R>; 248 dmas = <&hpdma 51 0x43 0x12>, 249 <&hpdma 52 0x43 0x21>; 250 dma-names = "rx", "tx"; 251 access-controllers = <&rifsc 23>; 252 status = "disabled"; 253 }; 254 255 spi2: spi@400b0000 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "st,stm32mp25-spi"; 259 reg = <0x400b0000 0x400>; 260 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&rcc CK_KER_SPI2>; 262 resets = <&rcc SPI2_R>; 263 dmas = <&hpdma 51 0x20 0x3012>, 264 <&hpdma 52 0x20 0x3021>; 265 dma-names = "rx", "tx"; 266 access-controllers = <&rifsc 23>; 267 status = "disabled"; 268 }; 269 270 i2s3: audio-controller@400c0000 { 271 compatible = "st,stm32mp25-i2s"; 272 reg = <0x400c0000 0x400>; 273 #sound-dai-cells = <0>; 274 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 276 clock-names = "pclk", "i2sclk"; 277 resets = <&rcc SPI3_R>; 278 dmas = <&hpdma 53 0x43 0x12>, 279 <&hpdma 54 0x43 0x21>; 280 dma-names = "rx", "tx"; 281 access-controllers = <&rifsc 24>; 282 status = "disabled"; 283 }; 284 285 spi3: spi@400c0000 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 compatible = "st,stm32mp25-spi"; 289 reg = <0x400c0000 0x400>; 290 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&rcc CK_KER_SPI3>; 292 resets = <&rcc SPI3_R>; 293 dmas = <&hpdma 53 0x20 0x3012>, 294 <&hpdma 54 0x20 0x3021>; 295 dma-names = "rx", "tx"; 296 access-controllers = <&rifsc 24>; 297 status = "disabled"; 298 }; 299 300 spdifrx: audio-controller@400d0000 { 301 compatible = "st,stm32h7-spdifrx"; 302 #sound-dai-cells = <0>; 303 reg = <0x400d0000 0x400>; 304 clocks = <&rcc CK_KER_SPDIFRX>; 305 clock-names = "kclk"; 306 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 307 dmas = <&hpdma 71 0x43 0x212>, 308 <&hpdma 72 0x43 0x212>; 309 dma-names = "rx", "rx-ctrl"; 310 access-controllers = <&rifsc 30>; 311 status = "disabled"; 312 }; 313 314 usart2: serial@400e0000 { 315 compatible = "st,stm32h7-uart"; 316 reg = <0x400e0000 0x400>; 317 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&rcc CK_KER_USART2>; 319 dmas = <&hpdma 11 0x20 0x10012>, 320 <&hpdma 12 0x20 0x3021>; 321 dma-names = "rx", "tx"; 322 access-controllers = <&rifsc 32>; 323 status = "disabled"; 324 }; 325 326 usart3: serial@400f0000 { 327 compatible = "st,stm32h7-uart"; 328 reg = <0x400f0000 0x400>; 329 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&rcc CK_KER_USART3>; 331 dmas = <&hpdma 13 0x20 0x10012>, 332 <&hpdma 14 0x20 0x3021>; 333 dma-names = "rx", "tx"; 334 access-controllers = <&rifsc 33>; 335 status = "disabled"; 336 }; 337 338 uart4: serial@40100000 { 339 compatible = "st,stm32h7-uart"; 340 reg = <0x40100000 0x400>; 341 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&rcc CK_KER_UART4>; 343 dmas = <&hpdma 15 0x20 0x10012>, 344 <&hpdma 16 0x20 0x3021>; 345 dma-names = "rx", "tx"; 346 access-controllers = <&rifsc 34>; 347 status = "disabled"; 348 }; 349 350 uart5: serial@40110000 { 351 compatible = "st,stm32h7-uart"; 352 reg = <0x40110000 0x400>; 353 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&rcc CK_KER_UART5>; 355 dmas = <&hpdma 17 0x20 0x10012>, 356 <&hpdma 18 0x20 0x3021>; 357 dma-names = "rx", "tx"; 358 access-controllers = <&rifsc 35>; 359 status = "disabled"; 360 }; 361 362 i2c1: i2c@40120000 { 363 compatible = "st,stm32mp25-i2c"; 364 reg = <0x40120000 0x400>; 365 interrupt-names = "event"; 366 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&rcc CK_KER_I2C1>; 368 resets = <&rcc I2C1_R>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 dmas = <&hpdma 27 0x20 0x3012>, 372 <&hpdma 28 0x20 0x3021>; 373 dma-names = "rx", "tx"; 374 access-controllers = <&rifsc 41>; 375 status = "disabled"; 376 }; 377 378 i2c2: i2c@40130000 { 379 compatible = "st,stm32mp25-i2c"; 380 reg = <0x40130000 0x400>; 381 interrupt-names = "event"; 382 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&rcc CK_KER_I2C2>; 384 resets = <&rcc I2C2_R>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 dmas = <&hpdma 30 0x20 0x3012>, 388 <&hpdma 31 0x20 0x3021>; 389 dma-names = "rx", "tx"; 390 access-controllers = <&rifsc 42>; 391 status = "disabled"; 392 }; 393 394 i2c3: i2c@40140000 { 395 compatible = "st,stm32mp25-i2c"; 396 reg = <0x40140000 0x400>; 397 interrupt-names = "event"; 398 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&rcc CK_KER_I2C3>; 400 resets = <&rcc I2C3_R>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 dmas = <&hpdma 33 0x20 0x3012>, 404 <&hpdma 34 0x20 0x3021>; 405 dma-names = "rx", "tx"; 406 access-controllers = <&rifsc 43>; 407 status = "disabled"; 408 }; 409 410 i2c4: i2c@40150000 { 411 compatible = "st,stm32mp25-i2c"; 412 reg = <0x40150000 0x400>; 413 interrupt-names = "event"; 414 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&rcc CK_KER_I2C4>; 416 resets = <&rcc I2C4_R>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 dmas = <&hpdma 36 0x20 0x3012>, 420 <&hpdma 37 0x20 0x3021>; 421 dma-names = "rx", "tx"; 422 access-controllers = <&rifsc 44>; 423 status = "disabled"; 424 }; 425 426 i2c5: i2c@40160000 { 427 compatible = "st,stm32mp25-i2c"; 428 reg = <0x40160000 0x400>; 429 interrupt-names = "event"; 430 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&rcc CK_KER_I2C5>; 432 resets = <&rcc I2C5_R>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 dmas = <&hpdma 39 0x20 0x3012>, 436 <&hpdma 40 0x20 0x3021>; 437 dma-names = "rx", "tx"; 438 access-controllers = <&rifsc 45>; 439 status = "disabled"; 440 }; 441 442 i2c6: i2c@40170000 { 443 compatible = "st,stm32mp25-i2c"; 444 reg = <0x40170000 0x400>; 445 interrupt-names = "event"; 446 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&rcc CK_KER_I2C6>; 448 resets = <&rcc I2C6_R>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 dmas = <&hpdma 42 0x20 0x3012>, 452 <&hpdma 43 0x20 0x3021>; 453 dma-names = "rx", "tx"; 454 access-controllers = <&rifsc 46>; 455 status = "disabled"; 456 }; 457 458 i2c7: i2c@40180000 { 459 compatible = "st,stm32mp25-i2c"; 460 reg = <0x40180000 0x400>; 461 interrupt-names = "event"; 462 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&rcc CK_KER_I2C7>; 464 resets = <&rcc I2C7_R>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 dmas = <&hpdma 45 0x20 0x3012>, 468 <&hpdma 46 0x20 0x3021>; 469 dma-names = "rx", "tx"; 470 access-controllers = <&rifsc 47>; 471 status = "disabled"; 472 }; 473 474 usart6: serial@40220000 { 475 compatible = "st,stm32h7-uart"; 476 reg = <0x40220000 0x400>; 477 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&rcc CK_KER_USART6>; 479 dmas = <&hpdma 19 0x20 0x10012>, 480 <&hpdma 20 0x20 0x3021>; 481 dma-names = "rx", "tx"; 482 access-controllers = <&rifsc 36>; 483 status = "disabled"; 484 }; 485 486 i2s1: audio-controller@40230000 { 487 compatible = "st,stm32mp25-i2s"; 488 reg = <0x40230000 0x400>; 489 #sound-dai-cells = <0>; 490 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 492 clock-names = "pclk", "i2sclk"; 493 resets = <&rcc SPI1_R>; 494 dmas = <&hpdma 49 0x43 0x12>, 495 <&hpdma 50 0x43 0x21>; 496 dma-names = "rx", "tx"; 497 access-controllers = <&rifsc 22>; 498 status = "disabled"; 499 }; 500 501 spi1: spi@40230000 { 502 #address-cells = <1>; 503 #size-cells = <0>; 504 compatible = "st,stm32mp25-spi"; 505 reg = <0x40230000 0x400>; 506 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&rcc CK_KER_SPI1>; 508 resets = <&rcc SPI1_R>; 509 dmas = <&hpdma 49 0x20 0x3012>, 510 <&hpdma 50 0x20 0x3021>; 511 dma-names = "rx", "tx"; 512 access-controllers = <&rifsc 22>; 513 status = "disabled"; 514 }; 515 516 spi4: spi@40240000 { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 compatible = "st,stm32mp25-spi"; 520 reg = <0x40240000 0x400>; 521 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&rcc CK_KER_SPI4>; 523 resets = <&rcc SPI4_R>; 524 dmas = <&hpdma 55 0x20 0x3012>, 525 <&hpdma 56 0x20 0x3021>; 526 dma-names = "rx", "tx"; 527 access-controllers = <&rifsc 25>; 528 status = "disabled"; 529 }; 530 531 spi5: spi@40280000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "st,stm32mp25-spi"; 535 reg = <0x40280000 0x400>; 536 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&rcc CK_KER_SPI5>; 538 resets = <&rcc SPI5_R>; 539 dmas = <&hpdma 57 0x20 0x3012>, 540 <&hpdma 58 0x20 0x3021>; 541 dma-names = "rx", "tx"; 542 access-controllers = <&rifsc 26>; 543 status = "disabled"; 544 }; 545 546 sai1: sai@40290000 { 547 compatible = "st,stm32mp25-sai"; 548 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 549 ranges = <0 0x40290000 0x400>; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 clocks = <&rcc CK_BUS_SAI1>; 553 clock-names = "pclk"; 554 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 555 resets = <&rcc SAI1_R>; 556 access-controllers = <&rifsc 49>; 557 status = "disabled"; 558 559 sai1a: audio-controller@40290004 { 560 compatible = "st,stm32-sai-sub-a"; 561 reg = <0x4 0x20>; 562 #sound-dai-cells = <0>; 563 clocks = <&rcc CK_KER_SAI1>; 564 clock-names = "sai_ck"; 565 dmas = <&hpdma 73 0x43 0x21>; 566 status = "disabled"; 567 }; 568 569 sai1b: audio-controller@40290024 { 570 compatible = "st,stm32-sai-sub-b"; 571 reg = <0x24 0x20>; 572 #sound-dai-cells = <0>; 573 clocks = <&rcc CK_KER_SAI1>; 574 clock-names = "sai_ck"; 575 dmas = <&hpdma 74 0x43 0x12>; 576 status = "disabled"; 577 }; 578 }; 579 580 sai2: sai@402a0000 { 581 compatible = "st,stm32mp25-sai"; 582 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 583 ranges = <0 0x402a0000 0x400>; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 clocks = <&rcc CK_BUS_SAI2>; 587 clock-names = "pclk"; 588 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 589 resets = <&rcc SAI2_R>; 590 access-controllers = <&rifsc 50>; 591 status = "disabled"; 592 593 sai2a: audio-controller@402a0004 { 594 compatible = "st,stm32-sai-sub-a"; 595 reg = <0x4 0x20>; 596 #sound-dai-cells = <0>; 597 clocks = <&rcc CK_KER_SAI2>; 598 clock-names = "sai_ck"; 599 dmas = <&hpdma 75 0x43 0x21>; 600 status = "disabled"; 601 }; 602 603 sai2b: audio-controller@402a0024 { 604 compatible = "st,stm32-sai-sub-b"; 605 reg = <0x24 0x20>; 606 #sound-dai-cells = <0>; 607 clocks = <&rcc CK_KER_SAI2>; 608 clock-names = "sai_ck"; 609 dmas = <&hpdma 76 0x43 0x12>; 610 status = "disabled"; 611 }; 612 }; 613 614 sai3: sai@402b0000 { 615 compatible = "st,stm32mp25-sai"; 616 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 617 ranges = <0 0x402b0000 0x400>; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 clocks = <&rcc CK_BUS_SAI3>; 621 clock-names = "pclk"; 622 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 623 resets = <&rcc SAI3_R>; 624 access-controllers = <&rifsc 51>; 625 status = "disabled"; 626 627 sai3a: audio-controller@402b0004 { 628 compatible = "st,stm32-sai-sub-a"; 629 reg = <0x4 0x20>; 630 #sound-dai-cells = <0>; 631 clocks = <&rcc CK_KER_SAI3>; 632 clock-names = "sai_ck"; 633 dmas = <&hpdma 77 0x43 0x21>; 634 status = "disabled"; 635 }; 636 637 sai3b: audio-controller@502b0024 { 638 compatible = "st,stm32-sai-sub-b"; 639 reg = <0x24 0x20>; 640 #sound-dai-cells = <0>; 641 clocks = <&rcc CK_KER_SAI3>; 642 clock-names = "sai_ck"; 643 dmas = <&hpdma 78 0x43 0x12>; 644 status = "disabled"; 645 }; 646 }; 647 648 uart9: serial@402c0000 { 649 compatible = "st,stm32h7-uart"; 650 reg = <0x402c0000 0x400>; 651 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&rcc CK_KER_UART9>; 653 dmas = <&hpdma 25 0x20 0x10012>, 654 <&hpdma 26 0x20 0x3021>; 655 dma-names = "rx", "tx"; 656 access-controllers = <&rifsc 39>; 657 status = "disabled"; 658 }; 659 660 usart1: serial@40330000 { 661 compatible = "st,stm32h7-uart"; 662 reg = <0x40330000 0x400>; 663 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&rcc CK_KER_USART1>; 665 dmas = <&hpdma 9 0x20 0x10012>, 666 <&hpdma 10 0x20 0x3021>; 667 dma-names = "rx", "tx"; 668 access-controllers = <&rifsc 31>; 669 status = "disabled"; 670 }; 671 672 sai4: sai@40340000 { 673 compatible = "st,stm32mp25-sai"; 674 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 675 ranges = <0 0x40340000 0x400>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 clocks = <&rcc CK_BUS_SAI4>; 679 clock-names = "pclk"; 680 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681 resets = <&rcc SAI4_R>; 682 access-controllers = <&rifsc 52>; 683 status = "disabled"; 684 685 sai4a: audio-controller@40340004 { 686 compatible = "st,stm32-sai-sub-a"; 687 reg = <0x4 0x20>; 688 #sound-dai-cells = <0>; 689 clocks = <&rcc CK_KER_SAI4>; 690 clock-names = "sai_ck"; 691 dmas = <&hpdma 79 0x63 0x21>; 692 status = "disabled"; 693 }; 694 695 sai4b: audio-controller@40340024 { 696 compatible = "st,stm32-sai-sub-b"; 697 reg = <0x24 0x20>; 698 #sound-dai-cells = <0>; 699 clocks = <&rcc CK_KER_SAI4>; 700 clock-names = "sai_ck"; 701 dmas = <&hpdma 80 0x43 0x12>; 702 status = "disabled"; 703 }; 704 }; 705 706 spi6: spi@40350000 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 compatible = "st,stm32mp25-spi"; 710 reg = <0x40350000 0x400>; 711 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&rcc CK_KER_SPI6>; 713 resets = <&rcc SPI6_R>; 714 dmas = <&hpdma 59 0x20 0x3012>, 715 <&hpdma 60 0x20 0x3021>; 716 dma-names = "rx", "tx"; 717 access-controllers = <&rifsc 27>; 718 status = "disabled"; 719 }; 720 721 spi7: spi@40360000 { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 compatible = "st,stm32mp25-spi"; 725 reg = <0x40360000 0x400>; 726 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&rcc CK_KER_SPI7>; 728 resets = <&rcc SPI7_R>; 729 dmas = <&hpdma 61 0x20 0x3012>, 730 <&hpdma 62 0x20 0x3021>; 731 dma-names = "rx", "tx"; 732 access-controllers = <&rifsc 28>; 733 status = "disabled"; 734 }; 735 736 uart7: serial@40370000 { 737 compatible = "st,stm32h7-uart"; 738 reg = <0x40370000 0x400>; 739 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&rcc CK_KER_UART7>; 741 dmas = <&hpdma 21 0x20 0x10012>, 742 <&hpdma 22 0x20 0x3021>; 743 dma-names = "rx", "tx"; 744 access-controllers = <&rifsc 37>; 745 status = "disabled"; 746 }; 747 748 uart8: serial@40380000 { 749 compatible = "st,stm32h7-uart"; 750 reg = <0x40380000 0x400>; 751 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&rcc CK_KER_UART8>; 753 dmas = <&hpdma 23 0x20 0x10012>, 754 <&hpdma 24 0x20 0x3021>; 755 dma-names = "rx", "tx"; 756 access-controllers = <&rifsc 38>; 757 status = "disabled"; 758 }; 759 760 rng: rng@42020000 { 761 compatible = "st,stm32mp25-rng"; 762 reg = <0x42020000 0x400>; 763 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 764 clock-names = "core", "bus"; 765 resets = <&rcc RNG_R>; 766 access-controllers = <&rifsc 92>; 767 status = "disabled"; 768 }; 769 770 spi8: spi@46020000 { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 compatible = "st,stm32mp25-spi"; 774 reg = <0x46020000 0x400>; 775 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&rcc CK_KER_SPI8>; 777 resets = <&rcc SPI8_R>; 778 dmas = <&hpdma 171 0x20 0x3012>, 779 <&hpdma 172 0x20 0x3021>; 780 dma-names = "rx", "tx"; 781 access-controllers = <&rifsc 29>; 782 status = "disabled"; 783 }; 784 785 i2c8: i2c@46040000 { 786 compatible = "st,stm32mp25-i2c"; 787 reg = <0x46040000 0x400>; 788 interrupt-names = "event"; 789 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&rcc CK_KER_I2C8>; 791 resets = <&rcc I2C8_R>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 dmas = <&hpdma 168 0x20 0x3012>, 795 <&hpdma 169 0x20 0x3021>; 796 dma-names = "rx", "tx"; 797 access-controllers = <&rifsc 48>; 798 status = "disabled"; 799 }; 800 801 csi: csi@48020000 { 802 compatible = "st,stm32mp25-csi"; 803 reg = <0x48020000 0x2000>; 804 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 805 resets = <&rcc CSI_R>; 806 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 807 <&rcc CK_KER_CSIPHY>; 808 clock-names = "pclk", "txesc", "csi2phy"; 809 access-controllers = <&rifsc 86>; 810 status = "disabled"; 811 }; 812 813 dcmipp: dcmipp@48030000 { 814 compatible = "st,stm32mp25-dcmipp"; 815 reg = <0x48030000 0x1000>; 816 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 817 resets = <&rcc DCMIPP_R>; 818 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 819 clock-names = "kclk", "mclk"; 820 access-controllers = <&rifsc 87>; 821 status = "disabled"; 822 }; 823 824 combophy: phy@480c0000 { 825 compatible = "st,stm32mp25-combophy"; 826 reg = <0x480c0000 0x1000>; 827 #phy-cells = <1>; 828 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; 829 clock-names = "apb", "ker"; 830 resets = <&rcc USB3PCIEPHY_R>; 831 reset-names = "phy"; 832 access-controllers = <&rifsc 67>; 833 power-domains = <&CLUSTER_PD>; 834 wakeup-source; 835 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>; 836 status = "disabled"; 837 }; 838 839 sdmmc1: mmc@48220000 { 840 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 841 arm,primecell-periphid = <0x00353180>; 842 reg = <0x48220000 0x400>, <0x44230400 0x8>; 843 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&rcc CK_KER_SDMMC1 >; 845 clock-names = "apb_pclk"; 846 resets = <&rcc SDMMC1_R>; 847 cap-sd-highspeed; 848 cap-mmc-highspeed; 849 max-frequency = <120000000>; 850 access-controllers = <&rifsc 76>; 851 status = "disabled"; 852 }; 853 854 ethernet1: ethernet@482c0000 { 855 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 856 reg = <0x482c0000 0x4000>; 857 reg-names = "stmmaceth"; 858 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "macirq"; 860 clock-names = "stmmaceth", 861 "mac-clk-tx", 862 "mac-clk-rx", 863 "ptp_ref", 864 "ethstp", 865 "eth-ck"; 866 clocks = <&rcc CK_ETH1_MAC>, 867 <&rcc CK_ETH1_TX>, 868 <&rcc CK_ETH1_RX>, 869 <&rcc CK_KER_ETH1PTP>, 870 <&rcc CK_ETH1_STP>, 871 <&rcc CK_KER_ETH1>; 872 snps,axi-config = <&stmmac_axi_config_1>; 873 snps,mixed-burst; 874 snps,mtl-rx-config = <&mtl_rx_setup_1>; 875 snps,mtl-tx-config = <&mtl_tx_setup_1>; 876 snps,pbl = <2>; 877 snps,tso; 878 st,syscon = <&syscfg 0x3000>; 879 access-controllers = <&rifsc 60>; 880 status = "disabled"; 881 882 mtl_rx_setup_1: rx-queues-config { 883 snps,rx-queues-to-use = <2>; 884 queue0 {}; 885 queue1 {}; 886 }; 887 888 mtl_tx_setup_1: tx-queues-config { 889 snps,tx-queues-to-use = <4>; 890 queue0 {}; 891 queue1 {}; 892 queue2 {}; 893 queue3 {}; 894 }; 895 896 stmmac_axi_config_1: stmmac-axi-config { 897 snps,blen = <0 0 0 0 16 8 4>; 898 snps,rd_osr_lmt = <0x7>; 899 snps,wr_osr_lmt = <0x7>; 900 }; 901 }; 902 }; 903 904 bsec: efuse@44000000 { 905 compatible = "st,stm32mp25-bsec"; 906 reg = <0x44000000 0x1000>; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 910 part_number_otp@24 { 911 reg = <0x24 0x4>; 912 }; 913 914 package_otp@1e8 { 915 reg = <0x1e8 0x1>; 916 bits = <0 3>; 917 }; 918 }; 919 920 rcc: clock-controller@44200000 { 921 compatible = "st,stm32mp25-rcc"; 922 reg = <0x44200000 0x10000>; 923 #clock-cells = <1>; 924 #reset-cells = <1>; 925 clocks = <&scmi_clk CK_SCMI_HSE>, 926 <&scmi_clk CK_SCMI_HSI>, 927 <&scmi_clk CK_SCMI_MSI>, 928 <&scmi_clk CK_SCMI_LSE>, 929 <&scmi_clk CK_SCMI_LSI>, 930 <&scmi_clk CK_SCMI_HSE_DIV2>, 931 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 932 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 933 <&scmi_clk CK_SCMI_ICN_SDMMC>, 934 <&scmi_clk CK_SCMI_ICN_DDR>, 935 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 936 <&scmi_clk CK_SCMI_ICN_HSL>, 937 <&scmi_clk CK_SCMI_ICN_NIC>, 938 <&scmi_clk CK_SCMI_ICN_VID>, 939 <&scmi_clk CK_SCMI_FLEXGEN_07>, 940 <&scmi_clk CK_SCMI_FLEXGEN_08>, 941 <&scmi_clk CK_SCMI_FLEXGEN_09>, 942 <&scmi_clk CK_SCMI_FLEXGEN_10>, 943 <&scmi_clk CK_SCMI_FLEXGEN_11>, 944 <&scmi_clk CK_SCMI_FLEXGEN_12>, 945 <&scmi_clk CK_SCMI_FLEXGEN_13>, 946 <&scmi_clk CK_SCMI_FLEXGEN_14>, 947 <&scmi_clk CK_SCMI_FLEXGEN_15>, 948 <&scmi_clk CK_SCMI_FLEXGEN_16>, 949 <&scmi_clk CK_SCMI_FLEXGEN_17>, 950 <&scmi_clk CK_SCMI_FLEXGEN_18>, 951 <&scmi_clk CK_SCMI_FLEXGEN_19>, 952 <&scmi_clk CK_SCMI_FLEXGEN_20>, 953 <&scmi_clk CK_SCMI_FLEXGEN_21>, 954 <&scmi_clk CK_SCMI_FLEXGEN_22>, 955 <&scmi_clk CK_SCMI_FLEXGEN_23>, 956 <&scmi_clk CK_SCMI_FLEXGEN_24>, 957 <&scmi_clk CK_SCMI_FLEXGEN_25>, 958 <&scmi_clk CK_SCMI_FLEXGEN_26>, 959 <&scmi_clk CK_SCMI_FLEXGEN_27>, 960 <&scmi_clk CK_SCMI_FLEXGEN_28>, 961 <&scmi_clk CK_SCMI_FLEXGEN_29>, 962 <&scmi_clk CK_SCMI_FLEXGEN_30>, 963 <&scmi_clk CK_SCMI_FLEXGEN_31>, 964 <&scmi_clk CK_SCMI_FLEXGEN_32>, 965 <&scmi_clk CK_SCMI_FLEXGEN_33>, 966 <&scmi_clk CK_SCMI_FLEXGEN_34>, 967 <&scmi_clk CK_SCMI_FLEXGEN_35>, 968 <&scmi_clk CK_SCMI_FLEXGEN_36>, 969 <&scmi_clk CK_SCMI_FLEXGEN_37>, 970 <&scmi_clk CK_SCMI_FLEXGEN_38>, 971 <&scmi_clk CK_SCMI_FLEXGEN_39>, 972 <&scmi_clk CK_SCMI_FLEXGEN_40>, 973 <&scmi_clk CK_SCMI_FLEXGEN_41>, 974 <&scmi_clk CK_SCMI_FLEXGEN_42>, 975 <&scmi_clk CK_SCMI_FLEXGEN_43>, 976 <&scmi_clk CK_SCMI_FLEXGEN_44>, 977 <&scmi_clk CK_SCMI_FLEXGEN_45>, 978 <&scmi_clk CK_SCMI_FLEXGEN_46>, 979 <&scmi_clk CK_SCMI_FLEXGEN_47>, 980 <&scmi_clk CK_SCMI_FLEXGEN_48>, 981 <&scmi_clk CK_SCMI_FLEXGEN_49>, 982 <&scmi_clk CK_SCMI_FLEXGEN_50>, 983 <&scmi_clk CK_SCMI_FLEXGEN_51>, 984 <&scmi_clk CK_SCMI_FLEXGEN_52>, 985 <&scmi_clk CK_SCMI_FLEXGEN_53>, 986 <&scmi_clk CK_SCMI_FLEXGEN_54>, 987 <&scmi_clk CK_SCMI_FLEXGEN_55>, 988 <&scmi_clk CK_SCMI_FLEXGEN_56>, 989 <&scmi_clk CK_SCMI_FLEXGEN_57>, 990 <&scmi_clk CK_SCMI_FLEXGEN_58>, 991 <&scmi_clk CK_SCMI_FLEXGEN_59>, 992 <&scmi_clk CK_SCMI_FLEXGEN_60>, 993 <&scmi_clk CK_SCMI_FLEXGEN_61>, 994 <&scmi_clk CK_SCMI_FLEXGEN_62>, 995 <&scmi_clk CK_SCMI_FLEXGEN_63>, 996 <&scmi_clk CK_SCMI_ICN_APB1>, 997 <&scmi_clk CK_SCMI_ICN_APB2>, 998 <&scmi_clk CK_SCMI_ICN_APB3>, 999 <&scmi_clk CK_SCMI_ICN_APB4>, 1000 <&scmi_clk CK_SCMI_ICN_APBDBG>, 1001 <&scmi_clk CK_SCMI_TIMG1>, 1002 <&scmi_clk CK_SCMI_TIMG2>, 1003 <&scmi_clk CK_SCMI_PLL3>, 1004 <&clk_dsi_txbyte>; 1005 access-controllers = <&rifsc 156>; 1006 }; 1007 1008 exti1: interrupt-controller@44220000 { 1009 compatible = "st,stm32mp1-exti", "syscon"; 1010 interrupt-controller; 1011 #interrupt-cells = <2>; 1012 reg = <0x44220000 0x400>; 1013 interrupts-extended = 1014 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1015 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 1016 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1017 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1018 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1019 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1020 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1021 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1022 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1023 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1024 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1025 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1026 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1027 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1028 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1029 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1030 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1031 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1032 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1033 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1034 <0>, /* EXTI_20 */ 1035 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1036 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1037 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1038 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1039 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1040 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1041 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1042 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1043 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1044 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1045 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1046 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1047 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1048 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1049 <0>, 1050 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1051 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1052 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1053 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1054 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1055 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1056 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1057 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1058 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1059 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1060 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1061 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1062 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1063 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1064 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1065 <0>, 1066 <0>, 1067 <0>, 1068 <0>, 1069 <0>, 1070 <0>, 1071 <0>, 1072 <0>, 1073 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1074 <0>, /* EXTI_60 */ 1075 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1076 <0>, 1077 <0>, 1078 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1079 <0>, 1080 <0>, 1081 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1082 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1083 <0>, 1084 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 1085 <0>, 1086 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1087 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1088 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1089 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1090 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1091 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1092 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1093 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1094 <0>, /* EXTI_80 */ 1095 <0>, 1096 <0>, 1097 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1098 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 1099 }; 1100 1101 syscfg: syscon@44230000 { 1102 compatible = "st,stm32mp25-syscfg", "syscon"; 1103 reg = <0x44230000 0x10000>; 1104 }; 1105 1106 pinctrl: pinctrl@44240000 { 1107 #address-cells = <1>; 1108 #size-cells = <1>; 1109 compatible = "st,stm32mp257-pinctrl"; 1110 ranges = <0 0x44240000 0xa0400>; 1111 interrupt-parent = <&exti1>; 1112 st,syscfg = <&exti1 0x60 0xff>; 1113 pins-are-numbered; 1114 1115 gpioa: gpio@44240000 { 1116 gpio-controller; 1117 #gpio-cells = <2>; 1118 interrupt-controller; 1119 #interrupt-cells = <2>; 1120 reg = <0x0 0x400>; 1121 clocks = <&scmi_clk CK_SCMI_GPIOA>; 1122 st,bank-name = "GPIOA"; 1123 status = "disabled"; 1124 }; 1125 1126 gpiob: gpio@44250000 { 1127 gpio-controller; 1128 #gpio-cells = <2>; 1129 interrupt-controller; 1130 #interrupt-cells = <2>; 1131 reg = <0x10000 0x400>; 1132 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1133 st,bank-name = "GPIOB"; 1134 status = "disabled"; 1135 }; 1136 1137 gpioc: gpio@44260000 { 1138 gpio-controller; 1139 #gpio-cells = <2>; 1140 interrupt-controller; 1141 #interrupt-cells = <2>; 1142 reg = <0x20000 0x400>; 1143 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1144 st,bank-name = "GPIOC"; 1145 status = "disabled"; 1146 }; 1147 1148 gpiod: gpio@44270000 { 1149 gpio-controller; 1150 #gpio-cells = <2>; 1151 interrupt-controller; 1152 #interrupt-cells = <2>; 1153 reg = <0x30000 0x400>; 1154 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1155 st,bank-name = "GPIOD"; 1156 status = "disabled"; 1157 }; 1158 1159 gpioe: gpio@44280000 { 1160 gpio-controller; 1161 #gpio-cells = <2>; 1162 interrupt-controller; 1163 #interrupt-cells = <2>; 1164 reg = <0x40000 0x400>; 1165 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1166 st,bank-name = "GPIOE"; 1167 status = "disabled"; 1168 }; 1169 1170 gpiof: gpio@44290000 { 1171 gpio-controller; 1172 #gpio-cells = <2>; 1173 interrupt-controller; 1174 #interrupt-cells = <2>; 1175 reg = <0x50000 0x400>; 1176 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1177 st,bank-name = "GPIOF"; 1178 status = "disabled"; 1179 }; 1180 1181 gpiog: gpio@442a0000 { 1182 gpio-controller; 1183 #gpio-cells = <2>; 1184 interrupt-controller; 1185 #interrupt-cells = <2>; 1186 reg = <0x60000 0x400>; 1187 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1188 st,bank-name = "GPIOG"; 1189 status = "disabled"; 1190 }; 1191 1192 gpioh: gpio@442b0000 { 1193 gpio-controller; 1194 #gpio-cells = <2>; 1195 interrupt-controller; 1196 #interrupt-cells = <2>; 1197 reg = <0x70000 0x400>; 1198 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1199 st,bank-name = "GPIOH"; 1200 status = "disabled"; 1201 }; 1202 1203 gpioi: gpio@442c0000 { 1204 gpio-controller; 1205 #gpio-cells = <2>; 1206 interrupt-controller; 1207 #interrupt-cells = <2>; 1208 reg = <0x80000 0x400>; 1209 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1210 st,bank-name = "GPIOI"; 1211 status = "disabled"; 1212 }; 1213 1214 gpioj: gpio@442d0000 { 1215 gpio-controller; 1216 #gpio-cells = <2>; 1217 interrupt-controller; 1218 #interrupt-cells = <2>; 1219 reg = <0x90000 0x400>; 1220 clocks = <&scmi_clk CK_SCMI_GPIOJ>; 1221 st,bank-name = "GPIOJ"; 1222 status = "disabled"; 1223 }; 1224 1225 gpiok: gpio@442e0000 { 1226 gpio-controller; 1227 #gpio-cells = <2>; 1228 interrupt-controller; 1229 #interrupt-cells = <2>; 1230 reg = <0xa0000 0x400>; 1231 clocks = <&scmi_clk CK_SCMI_GPIOK>; 1232 st,bank-name = "GPIOK"; 1233 status = "disabled"; 1234 }; 1235 }; 1236 1237 rtc: rtc@46000000 { 1238 compatible = "st,stm32mp25-rtc"; 1239 reg = <0x46000000 0x400>; 1240 clocks = <&scmi_clk CK_SCMI_RTC>, 1241 <&scmi_clk CK_SCMI_RTCCK>; 1242 clock-names = "pclk", "rtc_ck"; 1243 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1244 status = "disabled"; 1245 }; 1246 1247 pinctrl_z: pinctrl@46200000 { 1248 #address-cells = <1>; 1249 #size-cells = <1>; 1250 compatible = "st,stm32mp257-z-pinctrl"; 1251 ranges = <0 0x46200000 0x400>; 1252 interrupt-parent = <&exti1>; 1253 st,syscfg = <&exti1 0x60 0xff>; 1254 pins-are-numbered; 1255 1256 gpioz: gpio@46200000 { 1257 gpio-controller; 1258 #gpio-cells = <2>; 1259 interrupt-controller; 1260 #interrupt-cells = <2>; 1261 reg = <0 0x400>; 1262 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1263 st,bank-name = "GPIOZ"; 1264 st,bank-ioport = <11>; 1265 status = "disabled"; 1266 }; 1267 1268 }; 1269 1270 exti2: interrupt-controller@46230000 { 1271 compatible = "st,stm32mp1-exti", "syscon"; 1272 interrupt-controller; 1273 #interrupt-cells = <2>; 1274 reg = <0x46230000 0x400>; 1275 interrupts-extended = 1276 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1277 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1278 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1279 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1280 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1281 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1282 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1283 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1284 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1285 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1286 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1287 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1288 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1289 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1290 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1291 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1292 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1293 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1294 <0>, 1295 <0>, 1296 <0>, /* EXTI_20 */ 1297 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1298 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1299 <0>, 1300 <0>, 1301 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1302 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1303 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1304 <0>, 1305 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1306 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1307 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1308 <0>, 1309 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1310 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1311 <0>, 1312 <0>, 1313 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1314 <0>, 1315 <0>, 1316 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1317 <0>, 1318 <0>, 1319 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1320 <0>, 1321 <0>, 1322 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1323 <0>, 1324 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1325 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1326 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1327 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1328 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1329 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1330 <0>, 1331 <0>, 1332 <0>, 1333 <0>, 1334 <0>, 1335 <0>, 1336 <0>, /* EXTI_60 */ 1337 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1338 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1339 <0>, 1340 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1341 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1342 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1343 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1344 <0>, 1345 <0>, 1346 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1347 }; 1348 }; 1349}; 1350