xref: /linux/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce)
1 /*
2  *
3  * Copyright (C) 2016 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included
13  * in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #ifndef SMU_6_0_D_H
24 #define SMU_6_0_D_H
25 
26 #define ixLCAC_MC0_CNTL 0x011C
27 #define ixLCAC_MC0_OVR_SEL 0x011D
28 #define ixLCAC_MC0_OVR_VAL 0x011E
29 #define ixLCAC_MC1_CNTL 0x011F
30 #define ixLCAC_MC1_OVR_SEL 0x0120
31 #define ixLCAC_MC1_OVR_VAL 0x0121
32 #define ixLCAC_MC2_CNTL 0x0122
33 #define ixLCAC_MC2_OVR_SEL 0x0123
34 #define ixLCAC_MC2_OVR_VAL 0x0124
35 #define ixLCAC_MC3_CNTL 0x0125
36 #define ixLCAC_MC3_OVR_SEL 0x0126
37 #define ixLCAC_MC3_OVR_VAL 0x0127
38 #define ixLCAC_MC4_CNTL 0x0128
39 #define ixLCAC_MC4_OVR_SEL 0x0129
40 #define ixLCAC_MC4_OVR_VAL 0x012A
41 #define ixLCAC_MC5_CNTL 0x012B
42 #define ixLCAC_MC5_OVR_SEL 0x012C
43 #define ixLCAC_MC5_OVR_VAL 0x012D
44 
45 #define mmCG_SPLL_FUNC_CNTL				0x0180
46 #define mmCG_SPLL_FUNC_CNTL_2				0x0181
47 #define mmCG_SPLL_FUNC_CNTL_3				0x0182
48 #define mmCG_SPLL_FUNC_CNTL_4				0x0183
49 #define mmCG_SPLL_STATUS					0x0185
50 #define mmSPLL_CNTL_MODE					0x0186
51 #define mmCG_SPLL_SPREAD_SPECTRUM				0x0188
52 #define mmCG_SPLL_SPREAD_SPECTRUM_2			0x0189
53 #define mmCG_SPLL_AUTOSCALE_CNTL				0x018B
54 #define mmMPLL_BYPASSCLK_SEL				0x0197
55 #define mmCG_CLKPIN_CNTL                                    0x0198
56 #define mmCG_CLKPIN_CNTL_2                                  0x0199
57 #define mmTHM_CLK_CNTL					0x019B
58 #define mmMISC_CLK_CNTL					0x019C
59 #define mmCG_THERMAL_CTRL					0x01C0
60 #define mmCG_THERMAL_STATUS				0x01C1
61 #define mmCG_THERMAL_INT					0x01C2
62 #define mmCG_MULT_THERMAL_CTRL					0x01C4
63 #define mmCG_MULT_THERMAL_STATUS					0x01C5
64 #define mmCG_FDO_CTRL0					0x01D5
65 #define mmCG_FDO_CTRL1					0x01D6
66 #define mmCG_FDO_CTRL2					0x01D7
67 #define mmCG_TACH_CTRL                                    0x01DC
68 #define mmCG_TACH_STATUS                                  0x01DD
69 #define mmGENERAL_PWRMGT                                  0x1E0
70 #define mmCG_TPC                                            0x1E1
71 #define mmSCLK_PWRMGT_CNTL                                  0x1E2
72 #define mmTARGET_AND_CURRENT_PROFILE_INDEX                  0x01E6
73 #define mmCG_FTV                                            0x01EF
74 #define mmCG_FFCT_0                                         0x01F0
75 #define mmCG_BSP                                          0x01FF
76 #define mmCG_AT                                           0x0200
77 #define mmCG_GIT                                          0x0201
78 #define mmCG_SSP                                            0x0203
79 #define mmCG_DISPLAY_GAP_CNTL                               0x020A
80 #define mmCG_ULV_CONTROL					0x021E
81 #define mmCG_ULV_PARAMETER				0x021F
82 #define mmSMC_SCRATCH0					0x0221
83 #define mmCG_CAC_CTRL					0x022E
84 
85 #define ixSMC_PC_C 0x80000370
86 
87 #define ixTHM_TMON0_DEBUG 0x03F0
88 #define ixTHM_TMON0_INT_DATA 0x0380
89 #define ixTHM_TMON0_RDIL0_DATA 0x0300
90 #define ixTHM_TMON0_RDIL10_DATA 0x030A
91 #define ixTHM_TMON0_RDIL11_DATA 0x030B
92 #define ixTHM_TMON0_RDIL12_DATA 0x030C
93 #define ixTHM_TMON0_RDIL13_DATA 0x030D
94 #define ixTHM_TMON0_RDIL14_DATA 0x030E
95 #define ixTHM_TMON0_RDIL15_DATA 0x030F
96 #define ixTHM_TMON0_RDIL1_DATA 0x0301
97 #define ixTHM_TMON0_RDIL2_DATA 0x0302
98 #define ixTHM_TMON0_RDIL3_DATA 0x0303
99 #define ixTHM_TMON0_RDIL4_DATA 0x0304
100 #define ixTHM_TMON0_RDIL5_DATA 0x0305
101 #define ixTHM_TMON0_RDIL6_DATA 0x0306
102 #define ixTHM_TMON0_RDIL7_DATA 0x0307
103 #define ixTHM_TMON0_RDIL8_DATA 0x0308
104 #define ixTHM_TMON0_RDIL9_DATA 0x0309
105 #define ixTHM_TMON0_RDIR0_DATA 0x0310
106 #define ixTHM_TMON0_RDIR10_DATA 0x031A
107 #define ixTHM_TMON0_RDIR11_DATA 0x031B
108 #define ixTHM_TMON0_RDIR12_DATA 0x031C
109 #define ixTHM_TMON0_RDIR13_DATA 0x031D
110 #define ixTHM_TMON0_RDIR14_DATA 0x031E
111 #define ixTHM_TMON0_RDIR15_DATA 0x031F
112 #define ixTHM_TMON0_RDIR1_DATA 0x0311
113 #define ixTHM_TMON0_RDIR2_DATA 0x0312
114 #define ixTHM_TMON0_RDIR3_DATA 0x0313
115 #define ixTHM_TMON0_RDIR4_DATA 0x0314
116 #define ixTHM_TMON0_RDIR5_DATA 0x0315
117 #define ixTHM_TMON0_RDIR6_DATA 0x0316
118 #define ixTHM_TMON0_RDIR7_DATA 0x0317
119 #define ixTHM_TMON0_RDIR8_DATA 0x0318
120 #define ixTHM_TMON0_RDIR9_DATA 0x0319
121 #define ixTHM_TMON1_DEBUG 0x03F1
122 #define ixTHM_TMON1_INT_DATA 0x0381
123 #define ixTHM_TMON1_RDIL0_DATA 0x0320
124 #define ixTHM_TMON1_RDIL10_DATA 0x032A
125 #define ixTHM_TMON1_RDIL11_DATA 0x032B
126 #define ixTHM_TMON1_RDIL12_DATA 0x032C
127 #define ixTHM_TMON1_RDIL13_DATA 0x032D
128 #define ixTHM_TMON1_RDIL14_DATA 0x032E
129 #define ixTHM_TMON1_RDIL15_DATA 0x032F
130 #define ixTHM_TMON1_RDIL1_DATA 0x0321
131 #define ixTHM_TMON1_RDIL2_DATA 0x0322
132 #define ixTHM_TMON1_RDIL3_DATA 0x0323
133 #define ixTHM_TMON1_RDIL4_DATA 0x0324
134 #define ixTHM_TMON1_RDIL5_DATA 0x0325
135 #define ixTHM_TMON1_RDIL6_DATA 0x0326
136 #define ixTHM_TMON1_RDIL7_DATA 0x0327
137 #define ixTHM_TMON1_RDIL8_DATA 0x0328
138 #define ixTHM_TMON1_RDIL9_DATA 0x0329
139 #define ixTHM_TMON1_RDIR0_DATA 0x0330
140 #define ixTHM_TMON1_RDIR10_DATA 0x033A
141 #define ixTHM_TMON1_RDIR11_DATA 0x033B
142 #define ixTHM_TMON1_RDIR12_DATA 0x033C
143 #define ixTHM_TMON1_RDIR13_DATA 0x033D
144 #define ixTHM_TMON1_RDIR14_DATA 0x033E
145 #define ixTHM_TMON1_RDIR15_DATA 0x033F
146 #define ixTHM_TMON1_RDIR1_DATA 0x0331
147 #define ixTHM_TMON1_RDIR2_DATA 0x0332
148 #define ixTHM_TMON1_RDIR3_DATA 0x0333
149 #define ixTHM_TMON1_RDIR4_DATA 0x0334
150 #define ixTHM_TMON1_RDIR5_DATA 0x0335
151 #define ixTHM_TMON1_RDIR6_DATA 0x0336
152 #define ixTHM_TMON1_RDIR7_DATA 0x0337
153 #define ixTHM_TMON1_RDIR8_DATA 0x0338
154 #define ixTHM_TMON1_RDIR9_DATA 0x0339
155 
156 #define mmGPIOPAD_A 0x05E7
157 #define mmGPIOPAD_EN 0x05E8
158 #define mmGPIOPAD_EXTERN_TRIG_CNTL 0x05F1
159 #define mmGPIOPAD_INT_EN 0x05EE
160 #define mmGPIOPAD_INT_POLARITY 0x05F0
161 #define mmGPIOPAD_INT_STAT 0x05EC
162 #define mmGPIOPAD_INT_STAT_AK 0x05ED
163 #define mmGPIOPAD_INT_STAT_EN 0x05EB
164 #define mmGPIOPAD_INT_TYPE 0x05EF
165 #define mmGPIOPAD_MASK 0x05E6
166 #define mmGPIOPAD_PD_EN 0x05F4
167 #define mmGPIOPAD_PINSTRAPS 0x05EA
168 #define mmGPIOPAD_PU_EN 0x05F3
169 #define mmGPIOPAD_RCVR_SEL 0x05F2
170 #define mmGPIOPAD_STRENGTH 0x05E5
171 #define mmGPIOPAD_SW_INT_STAT 0x05E4
172 #define mmGPIOPAD_Y 0x05E9
173 
174 #define mmSMC_IND_ACCESS_CNTL 0x008A
175 #define mmSMC_IND_DATA_0 0x0081
176 #define mmSMC_IND_DATA 0x0081
177 #define mmSMC_IND_DATA_1 0x0083
178 #define mmSMC_IND_DATA_2 0x0085
179 #define mmSMC_IND_DATA_3 0x0087
180 #define mmSMC_IND_INDEX_0 0x0080
181 #define mmSMC_IND_INDEX 0x0080
182 #define mmSMC_IND_INDEX_1 0x0082
183 #define mmSMC_IND_INDEX_2 0x0084
184 #define mmSMC_IND_INDEX_3 0x0086
185 #define mmSMC_MESSAGE_0 0x008B
186 #define mmSMC_MESSAGE_1 0x008D
187 #define mmSMC_MESSAGE_2 0x008F
188 #define mmSMC_RESP_0 0x008C
189 #define mmSMC_RESP_1 0x008E
190 #define mmSMC_RESP_2 0x0090
191 
192 #endif
193