1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm6350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sm6350-camcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sm6350.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <76800000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32764>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo560"; 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 next-level-cache = <&l2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 63 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo560"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 93 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 95 power-domains = <&cpu_pd1>; 96 power-domain-names = "psci"; 97 #cooling-cells = <2>; 98 l2_100: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 next-level-cache = <&l3_0>; 103 }; 104 }; 105 106 cpu2: cpu@200 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo560"; 109 reg = <0x0 0x200>; 110 clocks = <&cpufreq_hw 0>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 dynamic-power-coefficient = <100>; 114 next-level-cache = <&l2_200>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 operating-points-v2 = <&cpu0_opp_table>; 117 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 118 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120 power-domains = <&cpu_pd2>; 121 power-domain-names = "psci"; 122 #cooling-cells = <2>; 123 l2_200: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 131 cpu3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo560"; 134 reg = <0x0 0x300>; 135 clocks = <&cpufreq_hw 0>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <100>; 139 next-level-cache = <&l2_300>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 143 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145 power-domains = <&cpu_pd3>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_300: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu4: cpu@400 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo560"; 159 reg = <0x0 0x400>; 160 clocks = <&cpufreq_hw 0>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <100>; 164 next-level-cache = <&l2_400>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 operating-points-v2 = <&cpu0_opp_table>; 167 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 168 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 power-domains = <&cpu_pd4>; 171 power-domain-names = "psci"; 172 #cooling-cells = <2>; 173 l2_400: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&l3_0>; 178 }; 179 }; 180 181 cpu5: cpu@500 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo560"; 184 reg = <0x0 0x500>; 185 clocks = <&cpufreq_hw 0>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1024>; 188 dynamic-power-coefficient = <100>; 189 next-level-cache = <&l2_500>; 190 qcom,freq-domain = <&cpufreq_hw 0>; 191 operating-points-v2 = <&cpu0_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 193 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 power-domains = <&cpu_pd5>; 196 power-domain-names = "psci"; 197 #cooling-cells = <2>; 198 l2_500: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu6: cpu@600 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo560"; 209 reg = <0x0 0x600>; 210 clocks = <&cpufreq_hw 1>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1894>; 213 dynamic-power-coefficient = <703>; 214 next-level-cache = <&l2_600>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu6_opp_table>; 217 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 218 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 power-domains = <&cpu_pd6>; 221 power-domain-names = "psci"; 222 #cooling-cells = <2>; 223 l2_600: l2-cache { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 next-level-cache = <&l3_0>; 228 }; 229 }; 230 231 cpu7: cpu@700 { 232 device_type = "cpu"; 233 compatible = "qcom,kryo560"; 234 reg = <0x0 0x700>; 235 clocks = <&cpufreq_hw 1>; 236 enable-method = "psci"; 237 capacity-dmips-mhz = <1894>; 238 dynamic-power-coefficient = <703>; 239 next-level-cache = <&l2_700>; 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 243 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 245 power-domains = <&cpu_pd7>; 246 power-domain-names = "psci"; 247 #cooling-cells = <2>; 248 l2_700: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-unified; 252 next-level-cache = <&l3_0>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&cpu0>; 260 }; 261 262 core1 { 263 cpu = <&cpu1>; 264 }; 265 266 core2 { 267 cpu = <&cpu2>; 268 }; 269 270 core3 { 271 cpu = <&cpu3>; 272 }; 273 274 core4 { 275 cpu = <&cpu4>; 276 }; 277 278 core5 { 279 cpu = <&cpu5>; 280 }; 281 282 core6 { 283 cpu = <&cpu6>; 284 }; 285 286 core7 { 287 cpu = <&cpu7>; 288 }; 289 }; 290 }; 291 292 domain-idle-states { 293 cluster_sleep_pc: cluster-sleep-0 { 294 compatible = "domain-idle-state"; 295 arm,psci-suspend-param = <0x41000044>; 296 entry-latency-us = <2752>; 297 exit-latency-us = <3048>; 298 min-residency-us = <6118>; 299 }; 300 301 cluster_sleep_cx_ret: cluster-sleep-1 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x41001244>; 304 entry-latency-us = <3638>; 305 exit-latency-us = <4562>; 306 min-residency-us = <8467>; 307 }; 308 309 cluster_aoss_sleep: cluster-sleep-2 { 310 compatible = "domain-idle-state"; 311 arm,psci-suspend-param = <0x4100b244>; 312 entry-latency-us = <3263>; 313 exit-latency-us = <6562>; 314 min-residency-us = <9987>; 315 }; 316 }; 317 318 cpu_idle_states: idle-states { 319 entry-method = "psci"; 320 321 little_cpu_sleep_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "little-power-collapse"; 324 arm,psci-suspend-param = <0x40000003>; 325 entry-latency-us = <549>; 326 exit-latency-us = <901>; 327 min-residency-us = <1774>; 328 local-timer-stop; 329 }; 330 331 little_cpu_sleep_1: cpu-sleep-0-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <702>; 336 exit-latency-us = <915>; 337 min-residency-us = <4001>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-power-collapse"; 344 arm,psci-suspend-param = <0x40000003>; 345 entry-latency-us = <523>; 346 exit-latency-us = <1244>; 347 min-residency-us = <2207>; 348 local-timer-stop; 349 }; 350 351 big_cpu_sleep_1: cpu-sleep-1-1 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "big-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <526>; 356 exit-latency-us = <1854>; 357 min-residency-us = <5555>; 358 local-timer-stop; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm: scm { 365 compatible = "qcom,scm-sm6350", "qcom,scm"; 366 #reset-cells = <1>; 367 }; 368 }; 369 370 memory@80000000 { 371 device_type = "memory"; 372 /* We expect the bootloader to fill in the size */ 373 reg = <0x0 0x80000000 0x0 0x0>; 374 }; 375 376 cpu0_opp_table: opp-table-cpu0 { 377 compatible = "operating-points-v2"; 378 opp-shared; 379 380 opp-300000000 { 381 opp-hz = /bits/ 64 <300000000>; 382 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 383 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 384 }; 385 386 opp-576000000 { 387 opp-hz = /bits/ 64 <576000000>; 388 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 389 }; 390 391 opp-768000000 { 392 opp-hz = /bits/ 64 <768000000>; 393 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 394 }; 395 396 opp-1017600000 { 397 opp-hz = /bits/ 64 <1017600000>; 398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 399 }; 400 401 opp-1248000000 { 402 opp-hz = /bits/ 64 <1248000000>; 403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 404 }; 405 406 opp-1324800000 { 407 opp-hz = /bits/ 64 <1324800000>; 408 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 409 }; 410 411 opp-1516800000 { 412 opp-hz = /bits/ 64 <1516800000>; 413 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 414 }; 415 416 opp-1612800000 { 417 opp-hz = /bits/ 64 <1612800000>; 418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 419 }; 420 421 opp-1708800000 { 422 opp-hz = /bits/ 64 <1708800000>; 423 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 424 }; 425 }; 426 427 cpu6_opp_table: opp-table-cpu6 { 428 compatible = "operating-points-v2"; 429 opp-shared; 430 431 opp-300000000 { 432 opp-hz = /bits/ 64 <300000000>; 433 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 434 }; 435 436 opp-787200000 { 437 opp-hz = /bits/ 64 <787200000>; 438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 439 }; 440 441 opp-979200000 { 442 opp-hz = /bits/ 64 <979200000>; 443 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 444 }; 445 446 opp-1036800000 { 447 opp-hz = /bits/ 64 <1036800000>; 448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 449 }; 450 451 opp-1248000000 { 452 opp-hz = /bits/ 64 <1248000000>; 453 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 454 }; 455 456 opp-1401600000 { 457 opp-hz = /bits/ 64 <1401600000>; 458 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 459 }; 460 461 opp-1555200000 { 462 opp-hz = /bits/ 64 <1555200000>; 463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464 }; 465 466 opp-1766400000 { 467 opp-hz = /bits/ 64 <1766400000>; 468 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 469 }; 470 471 opp-1900800000 { 472 opp-hz = /bits/ 64 <1900800000>; 473 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 474 }; 475 476 opp-2073600000 { 477 opp-hz = /bits/ 64 <2073600000>; 478 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 479 }; 480 }; 481 482 qup_opp_table: opp-table-qup { 483 compatible = "operating-points-v2"; 484 485 opp-75000000 { 486 opp-hz = /bits/ 64 <75000000>; 487 required-opps = <&rpmhpd_opp_low_svs>; 488 }; 489 490 opp-100000000 { 491 opp-hz = /bits/ 64 <100000000>; 492 required-opps = <&rpmhpd_opp_svs>; 493 }; 494 495 opp-128000000 { 496 opp-hz = /bits/ 64 <128000000>; 497 required-opps = <&rpmhpd_opp_nom>; 498 }; 499 }; 500 501 pmu { 502 compatible = "arm,armv8-pmuv3"; 503 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 504 }; 505 506 psci { 507 compatible = "arm,psci-1.0"; 508 method = "smc"; 509 510 cpu_pd0: power-domain-cpu0 { 511 #power-domain-cells = <0>; 512 power-domains = <&cluster_pd>; 513 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 514 }; 515 516 cpu_pd1: power-domain-cpu1 { 517 #power-domain-cells = <0>; 518 power-domains = <&cluster_pd>; 519 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 520 }; 521 522 cpu_pd2: power-domain-cpu2 { 523 #power-domain-cells = <0>; 524 power-domains = <&cluster_pd>; 525 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 526 }; 527 528 cpu_pd3: power-domain-cpu3 { 529 #power-domain-cells = <0>; 530 power-domains = <&cluster_pd>; 531 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 532 }; 533 534 cpu_pd4: power-domain-cpu4 { 535 #power-domain-cells = <0>; 536 power-domains = <&cluster_pd>; 537 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 538 }; 539 540 cpu_pd5: power-domain-cpu5 { 541 #power-domain-cells = <0>; 542 power-domains = <&cluster_pd>; 543 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 544 }; 545 546 cpu_pd6: power-domain-cpu6 { 547 #power-domain-cells = <0>; 548 power-domains = <&cluster_pd>; 549 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 550 }; 551 552 cpu_pd7: power-domain-cpu7 { 553 #power-domain-cells = <0>; 554 power-domains = <&cluster_pd>; 555 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 556 }; 557 558 cluster_pd: power-domain-cpu-cluster0 { 559 #power-domain-cells = <0>; 560 domain-idle-states = <&cluster_sleep_pc 561 &cluster_sleep_cx_ret 562 &cluster_aoss_sleep>; 563 }; 564 }; 565 566 reserved_memory: reserved-memory { 567 #address-cells = <2>; 568 #size-cells = <2>; 569 ranges; 570 571 hyp_mem: memory@80000000 { 572 reg = <0x0 0x80000000 0x0 0x600000>; 573 no-map; 574 }; 575 576 xbl_aop_mem: memory@80700000 { 577 reg = <0x0 0x80700000 0x0 0x160000>; 578 no-map; 579 }; 580 581 cmd_db: memory@80860000 { 582 compatible = "qcom,cmd-db"; 583 reg = <0x0 0x80860000 0x0 0x20000>; 584 no-map; 585 }; 586 587 sec_apps_mem: memory@808ff000 { 588 reg = <0x0 0x808ff000 0x0 0x1000>; 589 no-map; 590 }; 591 592 smem_mem: memory@80900000 { 593 reg = <0x0 0x80900000 0x0 0x200000>; 594 no-map; 595 }; 596 597 cdsp_sec_mem: memory@80b00000 { 598 reg = <0x0 0x80b00000 0x0 0x1e00000>; 599 no-map; 600 }; 601 602 pil_camera_mem: memory@86000000 { 603 reg = <0x0 0x86000000 0x0 0x500000>; 604 no-map; 605 }; 606 607 pil_npu_mem: memory@86500000 { 608 reg = <0x0 0x86500000 0x0 0x500000>; 609 no-map; 610 }; 611 612 pil_video_mem: memory@86a00000 { 613 reg = <0x0 0x86a00000 0x0 0x500000>; 614 no-map; 615 }; 616 617 pil_cdsp_mem: memory@86f00000 { 618 reg = <0x0 0x86f00000 0x0 0x1e00000>; 619 no-map; 620 }; 621 622 pil_adsp_mem: memory@88d00000 { 623 reg = <0x0 0x88d00000 0x0 0x2800000>; 624 no-map; 625 }; 626 627 wlan_fw_mem: memory@8b500000 { 628 reg = <0x0 0x8b500000 0x0 0x200000>; 629 no-map; 630 }; 631 632 pil_ipa_fw_mem: memory@8b700000 { 633 reg = <0x0 0x8b700000 0x0 0x10000>; 634 no-map; 635 }; 636 637 pil_ipa_gsi_mem: memory@8b710000 { 638 reg = <0x0 0x8b710000 0x0 0x5400>; 639 no-map; 640 }; 641 642 pil_modem_mem: memory@8b800000 { 643 reg = <0x0 0x8b800000 0x0 0xf800000>; 644 no-map; 645 }; 646 647 cont_splash_memory: memory@a0000000 { 648 reg = <0x0 0xa0000000 0x0 0x2300000>; 649 no-map; 650 }; 651 652 dfps_data_memory: memory@a2300000 { 653 reg = <0x0 0xa2300000 0x0 0x100000>; 654 no-map; 655 }; 656 657 removed_region: memory@c0000000 { 658 reg = <0x0 0xc0000000 0x0 0x3900000>; 659 no-map; 660 }; 661 662 pil_gpu_mem: memory@f0d00000 { 663 reg = <0x0 0xf0d00000 0x0 0x1000>; 664 no-map; 665 }; 666 667 debug_region: memory@ffb00000 { 668 reg = <0x0 0xffb00000 0x0 0xc0000>; 669 no-map; 670 }; 671 672 last_log_region: memory@ffbc0000 { 673 reg = <0x0 0xffbc0000 0x0 0x40000>; 674 no-map; 675 }; 676 677 ramoops: ramoops@ffc00000 { 678 compatible = "ramoops"; 679 reg = <0x0 0xffc00000 0x0 0x100000>; 680 record-size = <0x1000>; 681 console-size = <0x40000>; 682 pmsg-size = <0x20000>; 683 ecc-size = <16>; 684 no-map; 685 }; 686 687 cmdline_region: memory@ffd00000 { 688 reg = <0x0 0xffd00000 0x0 0x1000>; 689 no-map; 690 }; 691 }; 692 693 smem { 694 compatible = "qcom,smem"; 695 memory-region = <&smem_mem>; 696 hwlocks = <&tcsr_mutex 3>; 697 }; 698 699 smp2p-adsp { 700 compatible = "qcom,smp2p"; 701 qcom,smem = <443>, <429>; 702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P 704 IRQ_TYPE_EDGE_RISING>; 705 mboxes = <&ipcc IPCC_CLIENT_LPASS 706 IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <2>; 710 711 smp2p_adsp_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 smp2p_adsp_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 }; 721 }; 722 723 smp2p-cdsp { 724 compatible = "qcom,smp2p"; 725 qcom,smem = <94>, <432>; 726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 727 IPCC_MPROC_SIGNAL_SMP2P 728 IRQ_TYPE_EDGE_RISING>; 729 mboxes = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P>; 731 732 qcom,local-pid = <0>; 733 qcom,remote-pid = <5>; 734 735 smp2p_cdsp_out: master-kernel { 736 qcom,entry-name = "master-kernel"; 737 #qcom,smem-state-cells = <1>; 738 }; 739 740 smp2p_cdsp_in: slave-kernel { 741 qcom,entry-name = "slave-kernel"; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 }; 746 747 smp2p-mpss { 748 compatible = "qcom,smp2p"; 749 qcom,smem = <435>, <428>; 750 751 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 752 IPCC_MPROC_SIGNAL_SMP2P 753 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&ipcc IPCC_CLIENT_MPSS 755 IPCC_MPROC_SIGNAL_SMP2P>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <1>; 759 760 modem_smp2p_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 modem_smp2p_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 771 ipa_smp2p_out: ipa-ap-to-modem { 772 qcom,entry-name = "ipa"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 ipa_smp2p_in: ipa-modem-to-ap { 777 qcom,entry-name = "ipa"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 soc: soc@0 { 784 #address-cells = <2>; 785 #size-cells = <2>; 786 ranges = <0 0 0 0 0x10 0>; 787 dma-ranges = <0 0 0 0 0x10 0>; 788 compatible = "simple-bus"; 789 790 gcc: clock-controller@100000 { 791 compatible = "qcom,gcc-sm6350"; 792 reg = <0x0 0x00100000 0x0 0x1f0000>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 #power-domain-cells = <1>; 796 clock-names = "bi_tcxo", 797 "bi_tcxo_ao", 798 "sleep_clk"; 799 clocks = <&rpmhcc RPMH_CXO_CLK>, 800 <&rpmhcc RPMH_CXO_CLK_A>, 801 <&sleep_clk>; 802 }; 803 804 ipcc: mailbox@408000 { 805 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 806 reg = <0x0 0x00408000 0x0 0x1000>; 807 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-controller; 809 #interrupt-cells = <3>; 810 #mbox-cells = <2>; 811 }; 812 813 qfprom: qfprom@784000 { 814 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 815 reg = <0x0 0x00784000 0x0 0x3000>; 816 #address-cells = <1>; 817 #size-cells = <1>; 818 819 gpu_speed_bin: gpu-speed-bin@2015 { 820 reg = <0x2015 0x1>; 821 bits = <0 8>; 822 }; 823 }; 824 825 rng: rng@793000 { 826 compatible = "qcom,prng-ee"; 827 reg = <0x0 0x00793000 0x0 0x1000>; 828 clocks = <&gcc GCC_PRNG_AHB_CLK>; 829 clock-names = "core"; 830 }; 831 832 sdhc_1: mmc@7c4000 { 833 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 834 reg = <0x0 0x007c4000 0x0 0x1000>, 835 <0x0 0x007c5000 0x0 0x1000>, 836 <0x0 0x007c8000 0x0 0x8000>; 837 reg-names = "hc", "cqhci", "ice"; 838 839 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "hc_irq", "pwr_irq"; 842 iommus = <&apps_smmu 0x60 0x0>; 843 844 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 845 <&gcc GCC_SDCC1_APPS_CLK>, 846 <&rpmhcc RPMH_CXO_CLK>; 847 clock-names = "iface", "core", "xo"; 848 resets = <&gcc GCC_SDCC1_BCR>; 849 qcom,dll-config = <0x000f642c>; 850 qcom,ddr-config = <0x80040868>; 851 power-domains = <&rpmhpd SM6350_CX>; 852 operating-points-v2 = <&sdhc1_opp_table>; 853 bus-width = <8>; 854 non-removable; 855 supports-cqe; 856 857 status = "disabled"; 858 859 sdhc1_opp_table: opp-table { 860 compatible = "operating-points-v2"; 861 862 opp-19200000 { 863 opp-hz = /bits/ 64 <19200000>; 864 required-opps = <&rpmhpd_opp_min_svs>; 865 }; 866 867 opp-100000000 { 868 opp-hz = /bits/ 64 <100000000>; 869 required-opps = <&rpmhpd_opp_low_svs>; 870 }; 871 872 opp-384000000 { 873 opp-hz = /bits/ 64 <384000000>; 874 required-opps = <&rpmhpd_opp_svs_l1>; 875 }; 876 }; 877 }; 878 879 gpi_dma0: dma-controller@800000 { 880 compatible = "qcom,sm6350-gpi-dma"; 881 reg = <0x0 0x00800000 0x0 0x60000>; 882 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 892 dma-channels = <10>; 893 dma-channel-mask = <0x1f>; 894 iommus = <&apps_smmu 0x56 0x0>; 895 #dma-cells = <3>; 896 status = "disabled"; 897 }; 898 899 qupv3_id_0: geniqup@8c0000 { 900 compatible = "qcom,geni-se-qup"; 901 reg = <0x0 0x008c0000 0x0 0x2000>; 902 clock-names = "m-ahb", "s-ahb"; 903 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 904 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 905 #address-cells = <2>; 906 #size-cells = <2>; 907 iommus = <&apps_smmu 0x43 0x0>; 908 ranges; 909 status = "disabled"; 910 911 i2c0: i2c@880000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0x0 0x00880000 0x0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c0_default>; 918 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 919 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 920 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 921 dma-names = "tx", "rx"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 926 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 status = "disabled"; 929 }; 930 931 uart1: serial@884000 { 932 compatible = "qcom,geni-uart"; 933 reg = <0x0 0x00884000 0x0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 938 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 939 power-domains = <&rpmhpd SM6350_CX>; 940 operating-points-v2 = <&qup_opp_table>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 943 interconnect-names = "qup-core", "qup-config"; 944 status = "disabled"; 945 }; 946 947 i2c2: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x00888000 0x0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c2_default>; 954 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 955 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 956 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 957 dma-names = "tx", "rx"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 961 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 962 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 963 interconnect-names = "qup-core", "qup-config", "qup-memory"; 964 status = "disabled"; 965 }; 966 }; 967 968 gpi_dma1: dma-controller@900000 { 969 compatible = "qcom,sm6350-gpi-dma"; 970 reg = <0x0 0x00900000 0x0 0x60000>; 971 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 981 dma-channels = <10>; 982 dma-channel-mask = <0x3f>; 983 iommus = <&apps_smmu 0x4d6 0x0>; 984 #dma-cells = <3>; 985 status = "disabled"; 986 }; 987 988 qupv3_id_1: geniqup@9c0000 { 989 compatible = "qcom,geni-se-qup"; 990 reg = <0x0 0x009c0000 0x0 0x2000>; 991 clock-names = "m-ahb", "s-ahb"; 992 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 993 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 994 #address-cells = <2>; 995 #size-cells = <2>; 996 iommus = <&apps_smmu 0x4c3 0x0>; 997 ranges; 998 status = "disabled"; 999 1000 i2c6: i2c@980000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00980000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c6_default>; 1007 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1009 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1014 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1015 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c7: i2c@984000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0x0 0x00984000 0x0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c7_default>; 1027 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1028 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1029 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1035 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c8: i2c@988000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00988000 0x0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c8_default>; 1047 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1048 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1049 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1055 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 status = "disabled"; 1058 }; 1059 1060 uart9: serial@98c000 { 1061 compatible = "qcom,geni-debug-uart"; 1062 reg = <0x0 0x0098c000 0x0 0x4000>; 1063 clock-names = "se"; 1064 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_uart9_default>; 1067 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1069 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1070 interconnect-names = "qup-core", "qup-config"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c10: i2c@990000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0x0 0x00990000 0x0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_i2c10_default>; 1081 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1083 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1084 dma-names = "tx", "rx"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1088 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1089 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1090 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1091 status = "disabled"; 1092 }; 1093 }; 1094 1095 config_noc: interconnect@1500000 { 1096 compatible = "qcom,sm6350-config-noc"; 1097 reg = <0x0 0x01500000 0x0 0x28000>; 1098 #interconnect-cells = <2>; 1099 qcom,bcm-voters = <&apps_bcm_voter>; 1100 }; 1101 1102 system_noc: interconnect@1620000 { 1103 compatible = "qcom,sm6350-system-noc"; 1104 reg = <0x0 0x01620000 0x0 0x17080>; 1105 #interconnect-cells = <2>; 1106 qcom,bcm-voters = <&apps_bcm_voter>; 1107 1108 clk_virt: interconnect-clk-virt { 1109 compatible = "qcom,sm6350-clk-virt"; 1110 #interconnect-cells = <2>; 1111 qcom,bcm-voters = <&apps_bcm_voter>; 1112 }; 1113 }; 1114 1115 aggre1_noc: interconnect@16e0000 { 1116 compatible = "qcom,sm6350-aggre1-noc"; 1117 reg = <0x0 0x016e0000 0x0 0x15080>; 1118 #interconnect-cells = <2>; 1119 qcom,bcm-voters = <&apps_bcm_voter>; 1120 }; 1121 1122 aggre2_noc: interconnect@1700000 { 1123 compatible = "qcom,sm6350-aggre2-noc"; 1124 reg = <0x0 0x01700000 0x0 0x1f880>; 1125 #interconnect-cells = <2>; 1126 qcom,bcm-voters = <&apps_bcm_voter>; 1127 1128 compute_noc: interconnect-compute-noc { 1129 compatible = "qcom,sm6350-compute-noc"; 1130 #interconnect-cells = <2>; 1131 qcom,bcm-voters = <&apps_bcm_voter>; 1132 }; 1133 }; 1134 1135 mmss_noc: interconnect@1740000 { 1136 compatible = "qcom,sm6350-mmss-noc"; 1137 reg = <0x0 0x01740000 0x0 0x1c100>; 1138 #interconnect-cells = <2>; 1139 qcom,bcm-voters = <&apps_bcm_voter>; 1140 }; 1141 1142 ufs_mem_hc: ufshc@1d84000 { 1143 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1144 "jedec,ufs-2.0"; 1145 reg = <0x0 0x01d84000 0x0 0x3000>, 1146 <0x0 0x01d90000 0x0 0x8000>; 1147 reg-names = "std", "ice"; 1148 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1149 phys = <&ufs_mem_phy>; 1150 phy-names = "ufsphy"; 1151 lanes-per-direction = <2>; 1152 #reset-cells = <1>; 1153 resets = <&gcc GCC_UFS_PHY_BCR>; 1154 reset-names = "rst"; 1155 1156 power-domains = <&gcc UFS_PHY_GDSC>; 1157 1158 iommus = <&apps_smmu 0x80 0x0>; 1159 1160 clock-names = "core_clk", 1161 "bus_aggr_clk", 1162 "iface_clk", 1163 "core_clk_unipro", 1164 "ref_clk", 1165 "tx_lane0_sync_clk", 1166 "rx_lane0_sync_clk", 1167 "rx_lane1_sync_clk", 1168 "ice_core_clk"; 1169 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1170 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1171 <&gcc GCC_UFS_PHY_AHB_CLK>, 1172 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1173 <&rpmhcc RPMH_QLINK_CLK>, 1174 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1175 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1176 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1177 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1178 freq-table-hz = 1179 <50000000 200000000>, 1180 <0 0>, 1181 <0 0>, 1182 <37500000 150000000>, 1183 <75000000 300000000>, 1184 <0 0>, 1185 <0 0>, 1186 <0 0>, 1187 <0 0>; 1188 1189 status = "disabled"; 1190 }; 1191 1192 ufs_mem_phy: phy@1d87000 { 1193 compatible = "qcom,sm6350-qmp-ufs-phy"; 1194 reg = <0x0 0x01d87000 0x0 0x1000>; 1195 1196 clocks = <&rpmhcc RPMH_CXO_CLK>, 1197 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1198 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1199 clock-names = "ref", 1200 "ref_aux", 1201 "qref"; 1202 1203 power-domains = <&gcc UFS_PHY_GDSC>; 1204 1205 resets = <&ufs_mem_hc 0>; 1206 reset-names = "ufsphy"; 1207 1208 #phy-cells = <0>; 1209 1210 status = "disabled"; 1211 }; 1212 1213 cryptobam: dma-controller@1dc4000 { 1214 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1215 reg = <0x0 0x01dc4000 0x0 0x24000>; 1216 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1217 #dma-cells = <1>; 1218 qcom,ee = <0>; 1219 qcom,controlled-remotely; 1220 num-channels = <16>; 1221 qcom,num-ees = <4>; 1222 iommus = <&apps_smmu 0x426 0x11>, 1223 <&apps_smmu 0x432 0x0>, 1224 <&apps_smmu 0x436 0x11>, 1225 <&apps_smmu 0x438 0x1>, 1226 <&apps_smmu 0x43f 0x0>; 1227 }; 1228 1229 crypto: crypto@1dfa000 { 1230 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; 1231 reg = <0x0 0x01dfa000 0x0 0x6000>; 1232 dmas = <&cryptobam 4>, <&cryptobam 5>; 1233 dma-names = "rx", "tx"; 1234 iommus = <&apps_smmu 0x426 0x11>, 1235 <&apps_smmu 0x432 0x0>, 1236 <&apps_smmu 0x436 0x11>, 1237 <&apps_smmu 0x438 0x1>, 1238 <&apps_smmu 0x43f 0x0>; 1239 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS 1240 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; 1241 interconnect-names = "memory"; 1242 }; 1243 1244 ipa: ipa@1e40000 { 1245 compatible = "qcom,sm6350-ipa"; 1246 1247 iommus = <&apps_smmu 0x440 0x0>, 1248 <&apps_smmu 0x442 0x0>; 1249 reg = <0x0 0x01e40000 0x0 0x8000>, 1250 <0x0 0x01e50000 0x0 0x3000>, 1251 <0x0 0x01e04000 0x0 0x23000>; 1252 reg-names = "ipa-reg", 1253 "ipa-shared", 1254 "gsi"; 1255 1256 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1257 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1258 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1259 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1260 interrupt-names = "ipa", 1261 "gsi", 1262 "ipa-clock-query", 1263 "ipa-setup-ready"; 1264 1265 clocks = <&rpmhcc RPMH_IPA_CLK>; 1266 clock-names = "core"; 1267 1268 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1269 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1271 interconnect-names = "memory", "imem", "config"; 1272 1273 qcom,smem-states = <&ipa_smp2p_out 0>, 1274 <&ipa_smp2p_out 1>; 1275 qcom,smem-state-names = "ipa-clock-enabled-valid", 1276 "ipa-clock-enabled"; 1277 1278 status = "disabled"; 1279 }; 1280 1281 tcsr_mutex: hwlock@1f40000 { 1282 compatible = "qcom,tcsr-mutex"; 1283 reg = <0x0 0x01f40000 0x0 0x40000>; 1284 #hwlock-cells = <1>; 1285 }; 1286 1287 adsp: remoteproc@3000000 { 1288 compatible = "qcom,sm6350-adsp-pas"; 1289 reg = <0x0 0x03000000 0x0 0x10000>; 1290 1291 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1292 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1293 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1294 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1295 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1296 interrupt-names = "wdog", "fatal", "ready", 1297 "handover", "stop-ack"; 1298 1299 clocks = <&rpmhcc RPMH_CXO_CLK>; 1300 clock-names = "xo"; 1301 1302 power-domains = <&rpmhpd SM6350_LCX>, 1303 <&rpmhpd SM6350_LMX>; 1304 power-domain-names = "lcx", "lmx"; 1305 1306 memory-region = <&pil_adsp_mem>; 1307 1308 qcom,qmp = <&aoss_qmp>; 1309 1310 qcom,smem-states = <&smp2p_adsp_out 0>; 1311 qcom,smem-state-names = "stop"; 1312 1313 status = "disabled"; 1314 1315 glink-edge { 1316 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1317 IPCC_MPROC_SIGNAL_GLINK_QMP 1318 IRQ_TYPE_EDGE_RISING>; 1319 mboxes = <&ipcc IPCC_CLIENT_LPASS 1320 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1321 1322 label = "lpass"; 1323 qcom,remote-pid = <2>; 1324 1325 apr { 1326 compatible = "qcom,apr-v2"; 1327 qcom,glink-channels = "apr_audio_svc"; 1328 qcom,domain = <APR_DOMAIN_ADSP>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 1332 service@3 { 1333 reg = <APR_SVC_ADSP_CORE>; 1334 compatible = "qcom,q6core"; 1335 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1336 }; 1337 1338 q6afe: service@4 { 1339 compatible = "qcom,q6afe"; 1340 reg = <APR_SVC_AFE>; 1341 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1342 1343 q6afedai: dais { 1344 compatible = "qcom,q6afe-dais"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 #sound-dai-cells = <1>; 1348 }; 1349 1350 q6afecc: clock-controller { 1351 compatible = "qcom,q6afe-clocks"; 1352 #clock-cells = <2>; 1353 }; 1354 }; 1355 1356 q6asm: service@7 { 1357 compatible = "qcom,q6asm"; 1358 reg = <APR_SVC_ASM>; 1359 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1360 1361 q6asmdai: dais { 1362 compatible = "qcom,q6asm-dais"; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 #sound-dai-cells = <1>; 1366 iommus = <&apps_smmu 0x1001 0x0>; 1367 }; 1368 }; 1369 1370 q6adm: service@8 { 1371 compatible = "qcom,q6adm"; 1372 reg = <APR_SVC_ADM>; 1373 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1374 1375 q6routing: routing { 1376 compatible = "qcom,q6adm-routing"; 1377 #sound-dai-cells = <0>; 1378 }; 1379 }; 1380 }; 1381 1382 fastrpc { 1383 compatible = "qcom,fastrpc"; 1384 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1385 label = "adsp"; 1386 qcom,non-secure-domain; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 1390 compute-cb@3 { 1391 compatible = "qcom,fastrpc-compute-cb"; 1392 reg = <3>; 1393 iommus = <&apps_smmu 0x1003 0x0>; 1394 }; 1395 1396 compute-cb@4 { 1397 compatible = "qcom,fastrpc-compute-cb"; 1398 reg = <4>; 1399 iommus = <&apps_smmu 0x1004 0x0>; 1400 }; 1401 1402 compute-cb@5 { 1403 compatible = "qcom,fastrpc-compute-cb"; 1404 reg = <5>; 1405 iommus = <&apps_smmu 0x1005 0x0>; 1406 qcom,nsessions = <5>; 1407 }; 1408 }; 1409 }; 1410 }; 1411 1412 gpu: gpu@3d00000 { 1413 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1414 reg = <0x0 0x03d00000 0x0 0x40000>, 1415 <0x0 0x03d9e000 0x0 0x1000>; 1416 reg-names = "kgsl_3d0_reg_memory", 1417 "cx_mem"; 1418 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1419 1420 iommus = <&adreno_smmu 0>; 1421 operating-points-v2 = <&gpu_opp_table>; 1422 qcom,gmu = <&gmu>; 1423 nvmem-cells = <&gpu_speed_bin>; 1424 nvmem-cell-names = "speed_bin"; 1425 #cooling-cells = <2>; 1426 1427 status = "disabled"; 1428 1429 gpu_zap_shader: zap-shader { 1430 memory-region = <&pil_gpu_mem>; 1431 }; 1432 1433 gpu_opp_table: opp-table { 1434 compatible = "operating-points-v2"; 1435 1436 opp-850000000 { 1437 opp-hz = /bits/ 64 <850000000>; 1438 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1439 opp-supported-hw = <0x03>; 1440 }; 1441 1442 opp-800000000 { 1443 opp-hz = /bits/ 64 <800000000>; 1444 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1445 opp-supported-hw = <0x07>; 1446 }; 1447 1448 opp-650000000 { 1449 opp-hz = /bits/ 64 <650000000>; 1450 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1451 opp-supported-hw = <0x0f>; 1452 }; 1453 1454 opp-565000000 { 1455 opp-hz = /bits/ 64 <565000000>; 1456 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1457 opp-supported-hw = <0x1f>; 1458 }; 1459 1460 opp-430000000 { 1461 opp-hz = /bits/ 64 <430000000>; 1462 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1463 opp-supported-hw = <0x1f>; 1464 }; 1465 1466 opp-355000000 { 1467 opp-hz = /bits/ 64 <355000000>; 1468 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1469 opp-supported-hw = <0x1f>; 1470 }; 1471 1472 opp-253000000 { 1473 opp-hz = /bits/ 64 <253000000>; 1474 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1475 opp-supported-hw = <0x1f>; 1476 }; 1477 }; 1478 }; 1479 1480 adreno_smmu: iommu@3d40000 { 1481 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1482 reg = <0x0 0x03d40000 0x0 0x10000>; 1483 #iommu-cells = <1>; 1484 #global-interrupts = <2>; 1485 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1495 1496 clocks = <&gpucc GPU_CC_AHB_CLK>, 1497 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1498 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1499 clock-names = "ahb", 1500 "bus", 1501 "iface"; 1502 1503 power-domains = <&gpucc GPU_CX_GDSC>; 1504 }; 1505 1506 gmu: gmu@3d6a000 { 1507 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1508 reg = <0x0 0x03d6a000 0x0 0x31000>, 1509 <0x0 0x0b290000 0x0 0x10000>, 1510 <0x0 0x0b490000 0x0 0x10000>; 1511 reg-names = "gmu", 1512 "gmu_pdc", 1513 "gmu_pdc_seq"; 1514 1515 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1517 interrupt-names = "hfi", 1518 "gmu"; 1519 1520 clocks = <&gpucc GPU_CC_AHB_CLK>, 1521 <&gpucc GPU_CC_CX_GMU_CLK>, 1522 <&gpucc GPU_CC_CXO_CLK>, 1523 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1524 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1525 clock-names = "ahb", 1526 "gmu", 1527 "cxo", 1528 "axi", 1529 "memnoc"; 1530 1531 power-domains = <&gpucc GPU_CX_GDSC>, 1532 <&gpucc GPU_GX_GDSC>; 1533 power-domain-names = "cx", 1534 "gx"; 1535 1536 iommus = <&adreno_smmu 5>; 1537 1538 operating-points-v2 = <&gmu_opp_table>; 1539 1540 gmu_opp_table: opp-table { 1541 compatible = "operating-points-v2"; 1542 1543 opp-200000000 { 1544 opp-hz = /bits/ 64 <200000000>; 1545 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1546 }; 1547 }; 1548 }; 1549 1550 gpucc: clock-controller@3d90000 { 1551 compatible = "qcom,sm6350-gpucc"; 1552 reg = <0x0 0x03d90000 0x0 0x9000>; 1553 clocks = <&rpmhcc RPMH_CXO_CLK>, 1554 <&gcc GCC_GPU_GPLL0_CLK>, 1555 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1556 clock-names = "bi_tcxo", 1557 "gcc_gpu_gpll0_clk_src", 1558 "gcc_gpu_gpll0_div_clk_src"; 1559 #clock-cells = <1>; 1560 #reset-cells = <1>; 1561 #power-domain-cells = <1>; 1562 }; 1563 1564 mpss: remoteproc@4080000 { 1565 compatible = "qcom,sm6350-mpss-pas"; 1566 reg = <0x0 0x04080000 0x0 0x10000>; 1567 1568 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1569 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1570 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1571 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1572 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1573 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1574 interrupt-names = "wdog", "fatal", "ready", "handover", 1575 "stop-ack", "shutdown-ack"; 1576 1577 clocks = <&rpmhcc RPMH_CXO_CLK>; 1578 clock-names = "xo"; 1579 1580 power-domains = <&rpmhpd SM6350_CX>, 1581 <&rpmhpd SM6350_MSS>; 1582 power-domain-names = "cx", "mss"; 1583 1584 memory-region = <&pil_modem_mem>; 1585 1586 qcom,qmp = <&aoss_qmp>; 1587 1588 qcom,smem-states = <&modem_smp2p_out 0>; 1589 qcom,smem-state-names = "stop"; 1590 1591 status = "disabled"; 1592 1593 glink-edge { 1594 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1595 IPCC_MPROC_SIGNAL_GLINK_QMP 1596 IRQ_TYPE_EDGE_RISING>; 1597 mboxes = <&ipcc IPCC_CLIENT_MPSS 1598 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1599 label = "modem"; 1600 qcom,remote-pid = <1>; 1601 }; 1602 }; 1603 1604 cdsp: remoteproc@8300000 { 1605 compatible = "qcom,sm6350-cdsp-pas"; 1606 reg = <0x0 0x08300000 0x0 0x10000>; 1607 1608 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1609 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1610 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1611 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1612 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1613 interrupt-names = "wdog", "fatal", "ready", 1614 "handover", "stop-ack"; 1615 1616 clocks = <&rpmhcc RPMH_CXO_CLK>; 1617 clock-names = "xo"; 1618 1619 power-domains = <&rpmhpd SM6350_CX>, 1620 <&rpmhpd SM6350_MX>; 1621 power-domain-names = "cx", "mx"; 1622 1623 memory-region = <&pil_cdsp_mem>; 1624 1625 qcom,qmp = <&aoss_qmp>; 1626 1627 qcom,smem-states = <&smp2p_cdsp_out 0>; 1628 qcom,smem-state-names = "stop"; 1629 1630 status = "disabled"; 1631 1632 glink-edge { 1633 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1634 IPCC_MPROC_SIGNAL_GLINK_QMP 1635 IRQ_TYPE_EDGE_RISING>; 1636 mboxes = <&ipcc IPCC_CLIENT_CDSP 1637 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1638 1639 label = "cdsp"; 1640 qcom,remote-pid = <5>; 1641 1642 fastrpc { 1643 compatible = "qcom,fastrpc"; 1644 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1645 label = "cdsp"; 1646 qcom,non-secure-domain; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 1650 compute-cb@1 { 1651 compatible = "qcom,fastrpc-compute-cb"; 1652 reg = <1>; 1653 iommus = <&apps_smmu 0x1401 0x20>; 1654 }; 1655 1656 compute-cb@2 { 1657 compatible = "qcom,fastrpc-compute-cb"; 1658 reg = <2>; 1659 iommus = <&apps_smmu 0x1402 0x20>; 1660 }; 1661 1662 compute-cb@3 { 1663 compatible = "qcom,fastrpc-compute-cb"; 1664 reg = <3>; 1665 iommus = <&apps_smmu 0x1403 0x20>; 1666 }; 1667 1668 compute-cb@4 { 1669 compatible = "qcom,fastrpc-compute-cb"; 1670 reg = <4>; 1671 iommus = <&apps_smmu 0x1404 0x20>; 1672 }; 1673 1674 compute-cb@5 { 1675 compatible = "qcom,fastrpc-compute-cb"; 1676 reg = <5>; 1677 iommus = <&apps_smmu 0x1405 0x20>; 1678 }; 1679 1680 compute-cb@6 { 1681 compatible = "qcom,fastrpc-compute-cb"; 1682 reg = <6>; 1683 iommus = <&apps_smmu 0x1406 0x20>; 1684 }; 1685 1686 compute-cb@7 { 1687 compatible = "qcom,fastrpc-compute-cb"; 1688 reg = <7>; 1689 iommus = <&apps_smmu 0x1407 0x20>; 1690 }; 1691 1692 compute-cb@8 { 1693 compatible = "qcom,fastrpc-compute-cb"; 1694 reg = <8>; 1695 iommus = <&apps_smmu 0x1408 0x20>; 1696 }; 1697 1698 /* note: secure cb9 in downstream */ 1699 }; 1700 }; 1701 }; 1702 1703 sdhc_2: mmc@8804000 { 1704 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1705 reg = <0x0 0x08804000 0x0 0x1000>; 1706 1707 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1709 interrupt-names = "hc_irq", "pwr_irq"; 1710 iommus = <&apps_smmu 0x560 0x0>; 1711 1712 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1713 <&gcc GCC_SDCC2_APPS_CLK>, 1714 <&rpmhcc RPMH_CXO_CLK>; 1715 clock-names = "iface", "core", "xo"; 1716 resets = <&gcc GCC_SDCC2_BCR>; 1717 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1718 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1719 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1720 1721 pinctrl-0 = <&sdc2_on_state>; 1722 pinctrl-1 = <&sdc2_off_state>; 1723 pinctrl-names = "default", "sleep"; 1724 1725 qcom,dll-config = <0x0007642c>; 1726 qcom,ddr-config = <0x80040868>; 1727 power-domains = <&rpmhpd SM6350_CX>; 1728 operating-points-v2 = <&sdhc2_opp_table>; 1729 bus-width = <4>; 1730 1731 status = "disabled"; 1732 1733 sdhc2_opp_table: opp-table { 1734 compatible = "operating-points-v2"; 1735 1736 opp-100000000 { 1737 opp-hz = /bits/ 64 <100000000>; 1738 required-opps = <&rpmhpd_opp_svs_l1>; 1739 opp-peak-kBps = <790000 131000>; 1740 opp-avg-kBps = <50000 50000>; 1741 }; 1742 1743 opp-202000000 { 1744 opp-hz = /bits/ 64 <202000000>; 1745 required-opps = <&rpmhpd_opp_nom>; 1746 opp-peak-kBps = <3190000 294000>; 1747 opp-avg-kBps = <261438 300000>; 1748 }; 1749 }; 1750 }; 1751 1752 usb_1_hsphy: phy@88e3000 { 1753 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1754 reg = <0x0 0x088e3000 0x0 0x400>; 1755 status = "disabled"; 1756 #phy-cells = <0>; 1757 1758 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1759 clock-names = "cfg_ahb", "ref"; 1760 1761 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1762 }; 1763 1764 usb_1_qmpphy: phy@88e8000 { 1765 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1766 reg = <0x0 0x088e8000 0x0 0x3000>; 1767 1768 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1769 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1770 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1771 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1772 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1773 1774 power-domains = <&gcc USB30_PRIM_GDSC>; 1775 1776 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1777 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1778 reset-names = "phy", "common"; 1779 1780 orientation-switch; 1781 1782 #clock-cells = <1>; 1783 #phy-cells = <1>; 1784 1785 status = "disabled"; 1786 1787 ports { 1788 #address-cells = <1>; 1789 #size-cells = <0>; 1790 1791 port@0 { 1792 reg = <0>; 1793 1794 usb_1_qmpphy_out: endpoint { 1795 }; 1796 }; 1797 1798 port@1 { 1799 reg = <1>; 1800 1801 usb_1_qmpphy_usb_ss_in: endpoint { 1802 remote-endpoint = <&usb_1_dwc3_ss_out>; 1803 }; 1804 }; 1805 1806 port@2 { 1807 reg = <2>; 1808 1809 usb_1_qmpphy_dp_in: endpoint { 1810 }; 1811 }; 1812 }; 1813 }; 1814 1815 dc_noc: interconnect@9160000 { 1816 compatible = "qcom,sm6350-dc-noc"; 1817 reg = <0x0 0x09160000 0x0 0x3200>; 1818 #interconnect-cells = <2>; 1819 qcom,bcm-voters = <&apps_bcm_voter>; 1820 }; 1821 1822 system-cache-controller@9200000 { 1823 compatible = "qcom,sm6350-llcc"; 1824 reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; 1825 reg-names = "llcc0_base", "llcc_broadcast_base"; 1826 }; 1827 1828 gem_noc: interconnect@9680000 { 1829 compatible = "qcom,sm6350-gem-noc"; 1830 reg = <0x0 0x09680000 0x0 0x3e200>; 1831 #interconnect-cells = <2>; 1832 qcom,bcm-voters = <&apps_bcm_voter>; 1833 }; 1834 1835 npu_noc: interconnect@9990000 { 1836 compatible = "qcom,sm6350-npu-noc"; 1837 reg = <0x0 0x09990000 0x0 0x1600>; 1838 #interconnect-cells = <2>; 1839 qcom,bcm-voters = <&apps_bcm_voter>; 1840 }; 1841 1842 pmu@90b6300 { 1843 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1844 reg = <0x0 0x090b6300 0x0 0x600>; 1845 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 operating-points-v2 = <&llcc_bwmon_opp_table>; 1848 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1849 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1850 1851 llcc_bwmon_opp_table: opp-table { 1852 compatible = "operating-points-v2"; 1853 1854 opp-0 { 1855 opp-peak-kBps = <2288000>; 1856 }; 1857 1858 opp-1 { 1859 opp-peak-kBps = <4577000>; 1860 }; 1861 1862 opp-2 { 1863 opp-peak-kBps = <7110000>; 1864 }; 1865 1866 opp-3 { 1867 opp-peak-kBps = <9155000>; 1868 }; 1869 1870 opp-4 { 1871 opp-peak-kBps = <12298000>; 1872 }; 1873 1874 opp-5 { 1875 opp-peak-kBps = <14236000>; 1876 }; 1877 1878 }; 1879 }; 1880 1881 pmu@90cd000 { 1882 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1883 reg = <0x0 0x090cd000 0x0 0x1000>; 1884 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1885 1886 operating-points-v2 = <&cpu_bwmon_opp_table>; 1887 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1888 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1889 1890 cpu_bwmon_opp_table: opp-table { 1891 compatible = "operating-points-v2"; 1892 1893 opp-0 { 1894 opp-peak-kBps = <762000>; 1895 }; 1896 1897 opp-1 { 1898 opp-peak-kBps = <1144000>; 1899 }; 1900 1901 opp-2 { 1902 opp-peak-kBps = <1720000>; 1903 }; 1904 1905 opp-3 { 1906 opp-peak-kBps = <2086000>; 1907 }; 1908 1909 opp-4 { 1910 opp-peak-kBps = <2597000>; 1911 }; 1912 1913 opp-5 { 1914 opp-peak-kBps = <2929000>; 1915 }; 1916 1917 opp-6 { 1918 opp-peak-kBps = <3879000>; 1919 }; 1920 1921 opp-7 { 1922 opp-peak-kBps = <5161000>; 1923 }; 1924 1925 opp-8 { 1926 opp-peak-kBps = <5931000>; 1927 }; 1928 1929 opp-9 { 1930 opp-peak-kBps = <6881000>; 1931 }; 1932 1933 opp-10 { 1934 opp-peak-kBps = <7980000>; 1935 }; 1936 }; 1937 }; 1938 1939 usb_1: usb@a6f8800 { 1940 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1941 reg = <0x0 0x0a6f8800 0x0 0x400>; 1942 status = "disabled"; 1943 #address-cells = <2>; 1944 #size-cells = <2>; 1945 ranges; 1946 1947 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1948 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1949 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1950 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1951 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1952 clock-names = "cfg_noc", 1953 "core", 1954 "iface", 1955 "sleep", 1956 "mock_utmi"; 1957 1958 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1959 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1960 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1961 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1962 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1963 interrupt-names = "pwr_event", 1964 "hs_phy_irq", 1965 "dp_hs_phy_irq", 1966 "dm_hs_phy_irq", 1967 "ss_phy_irq"; 1968 1969 power-domains = <&gcc USB30_PRIM_GDSC>; 1970 1971 resets = <&gcc GCC_USB30_PRIM_BCR>; 1972 1973 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1974 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1975 interconnect-names = "usb-ddr", "apps-usb"; 1976 1977 usb_1_dwc3: usb@a600000 { 1978 compatible = "snps,dwc3"; 1979 reg = <0x0 0x0a600000 0x0 0xcd00>; 1980 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1981 iommus = <&apps_smmu 0x540 0x0>; 1982 snps,dis_u2_susphy_quirk; 1983 snps,dis_enblslpm_quirk; 1984 snps,has-lpm-erratum; 1985 snps,hird-threshold = /bits/ 8 <0x10>; 1986 snps,parkmode-disable-ss-quirk; 1987 snps,dis-u1-entry-quirk; 1988 snps,dis-u2-entry-quirk; 1989 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1990 phy-names = "usb2-phy", "usb3-phy"; 1991 usb-role-switch; 1992 1993 ports { 1994 #address-cells = <1>; 1995 #size-cells = <0>; 1996 1997 port@0 { 1998 reg = <0>; 1999 2000 usb_1_dwc3_hs_out: endpoint { 2001 }; 2002 }; 2003 2004 port@1 { 2005 reg = <1>; 2006 2007 usb_1_dwc3_ss_out: endpoint { 2008 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2009 }; 2010 }; 2011 }; 2012 }; 2013 }; 2014 2015 videocc: clock-controller@aaf0000 { 2016 compatible = "qcom,sm6350-videocc"; 2017 reg = <0x0 0x0aaf0000 0x0 0x10000>; 2018 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2019 <&rpmhcc RPMH_CXO_CLK>, 2020 <&sleep_clk>; 2021 clock-names = "iface", 2022 "bi_tcxo", 2023 "sleep_clk"; 2024 #clock-cells = <1>; 2025 #reset-cells = <1>; 2026 #power-domain-cells = <1>; 2027 }; 2028 2029 cci0: cci@ac4a000 { 2030 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2031 reg = <0x0 0x0ac4a000 0x0 0x1000>; 2032 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 2033 power-domains = <&camcc TITAN_TOP_GDSC>; 2034 2035 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2036 <&camcc CAMCC_SOC_AHB_CLK>, 2037 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2038 <&camcc CAMCC_CPAS_AHB_CLK>, 2039 <&camcc CAMCC_CCI_0_CLK>, 2040 <&camcc CAMCC_CCI_0_CLK_SRC>; 2041 clock-names = "camnoc_axi", 2042 "soc_ahb", 2043 "slow_ahb_src", 2044 "cpas_ahb", 2045 "cci", 2046 "cci_src"; 2047 2048 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2049 <&camcc CAMCC_CCI_0_CLK>; 2050 assigned-clock-rates = <80000000>, <37500000>; 2051 2052 pinctrl-0 = <&cci0_default &cci1_default>; 2053 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2054 pinctrl-names = "default", "sleep"; 2055 2056 #address-cells = <1>; 2057 #size-cells = <0>; 2058 2059 status = "disabled"; 2060 2061 cci0_i2c0: i2c-bus@0 { 2062 reg = <0>; 2063 clock-frequency = <1000000>; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 }; 2067 2068 cci0_i2c1: i2c-bus@1 { 2069 reg = <1>; 2070 clock-frequency = <1000000>; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 }; 2074 }; 2075 2076 cci1: cci@ac4b000 { 2077 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2078 reg = <0x0 0x0ac4b000 0x0 0x1000>; 2079 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 2080 power-domains = <&camcc TITAN_TOP_GDSC>; 2081 2082 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2083 <&camcc CAMCC_SOC_AHB_CLK>, 2084 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2085 <&camcc CAMCC_CPAS_AHB_CLK>, 2086 <&camcc CAMCC_CCI_1_CLK>, 2087 <&camcc CAMCC_CCI_1_CLK_SRC>; 2088 clock-names = "camnoc_axi", 2089 "soc_ahb", 2090 "slow_ahb_src", 2091 "cpas_ahb", 2092 "cci", 2093 "cci_src"; 2094 2095 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2096 <&camcc CAMCC_CCI_1_CLK>; 2097 assigned-clock-rates = <80000000>, <37500000>; 2098 2099 pinctrl-0 = <&cci2_default>; 2100 pinctrl-1 = <&cci2_sleep>; 2101 pinctrl-names = "default", "sleep"; 2102 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 status = "disabled"; 2107 2108 cci1_i2c0: i2c-bus@0 { 2109 reg = <0>; 2110 clock-frequency = <1000000>; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 }; 2114 2115 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 2116 }; 2117 2118 camcc: clock-controller@ad00000 { 2119 compatible = "qcom,sm6350-camcc"; 2120 reg = <0x0 0x0ad00000 0x0 0x16000>; 2121 clocks = <&rpmhcc RPMH_CXO_CLK>; 2122 #clock-cells = <1>; 2123 #reset-cells = <1>; 2124 #power-domain-cells = <1>; 2125 }; 2126 2127 mdss: display-subsystem@ae00000 { 2128 compatible = "qcom,sm6350-mdss"; 2129 reg = <0x0 0x0ae00000 0x0 0x1000>; 2130 reg-names = "mdss"; 2131 2132 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2133 interrupt-controller; 2134 #interrupt-cells = <1>; 2135 2136 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2137 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2138 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 2139 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2140 interconnect-names = "mdp0-mem", 2141 "cpu-cfg"; 2142 2143 clocks = <&gcc GCC_DISP_AHB_CLK>, 2144 <&gcc GCC_DISP_AXI_CLK>, 2145 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2146 clock-names = "iface", 2147 "bus", 2148 "core"; 2149 2150 power-domains = <&dispcc MDSS_GDSC>; 2151 iommus = <&apps_smmu 0x800 0x2>; 2152 2153 #address-cells = <2>; 2154 #size-cells = <2>; 2155 ranges; 2156 2157 status = "disabled"; 2158 2159 mdss_mdp: display-controller@ae01000 { 2160 compatible = "qcom,sm6350-dpu"; 2161 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2162 <0x0 0x0aeb0000 0x0 0x2008>; 2163 reg-names = "mdp", "vbif"; 2164 2165 interrupt-parent = <&mdss>; 2166 interrupts = <0>; 2167 2168 clocks = <&gcc GCC_DISP_AXI_CLK>, 2169 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2170 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2171 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2172 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2173 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2174 clock-names = "bus", 2175 "iface", 2176 "rot", 2177 "lut", 2178 "core", 2179 "vsync"; 2180 2181 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2182 assigned-clock-rates = <19200000>; 2183 2184 operating-points-v2 = <&mdp_opp_table>; 2185 power-domains = <&rpmhpd SM6350_CX>; 2186 2187 ports { 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 2191 port@0 { 2192 reg = <0>; 2193 2194 dpu_intf1_out: endpoint { 2195 remote-endpoint = <&mdss_dsi0_in>; 2196 }; 2197 }; 2198 2199 port@2 { 2200 reg = <2>; 2201 2202 dpu_intf0_out: endpoint { 2203 remote-endpoint = <&mdss_dp_in>; 2204 }; 2205 }; 2206 }; 2207 2208 mdp_opp_table: opp-table { 2209 compatible = "operating-points-v2"; 2210 2211 opp-19200000 { 2212 opp-hz = /bits/ 64 <19200000>; 2213 required-opps = <&rpmhpd_opp_min_svs>; 2214 }; 2215 2216 opp-200000000 { 2217 opp-hz = /bits/ 64 <200000000>; 2218 required-opps = <&rpmhpd_opp_low_svs>; 2219 }; 2220 2221 opp-300000000 { 2222 opp-hz = /bits/ 64 <300000000>; 2223 required-opps = <&rpmhpd_opp_svs>; 2224 }; 2225 2226 opp-373333333 { 2227 opp-hz = /bits/ 64 <373333333>; 2228 required-opps = <&rpmhpd_opp_svs_l1>; 2229 }; 2230 2231 opp-448000000 { 2232 opp-hz = /bits/ 64 <448000000>; 2233 required-opps = <&rpmhpd_opp_nom>; 2234 }; 2235 2236 opp-560000000 { 2237 opp-hz = /bits/ 64 <560000000>; 2238 required-opps = <&rpmhpd_opp_turbo>; 2239 }; 2240 }; 2241 }; 2242 2243 mdss_dp: displayport-controller@ae90000 { 2244 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; 2245 reg = <0x0 0xae90000 0x0 0x200>, 2246 <0x0 0xae90200 0x0 0x200>, 2247 <0x0 0xae90400 0x0 0x600>, 2248 <0x0 0xae91000 0x0 0x400>, 2249 <0x0 0xae91400 0x0 0x400>; 2250 interrupt-parent = <&mdss>; 2251 interrupts = <12>; 2252 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2253 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2254 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2255 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2256 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2257 clock-names = "core_iface", 2258 "core_aux", 2259 "ctrl_link", 2260 "ctrl_link_iface", 2261 "stream_pixel"; 2262 2263 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2264 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2265 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2266 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2267 2268 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2269 phy-names = "dp"; 2270 2271 #sound-dai-cells = <0>; 2272 2273 operating-points-v2 = <&dp_opp_table>; 2274 power-domains = <&rpmhpd SM6350_CX>; 2275 2276 status = "disabled"; 2277 2278 ports { 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 2282 port@0 { 2283 reg = <0>; 2284 2285 mdss_dp_in: endpoint { 2286 remote-endpoint = <&dpu_intf0_out>; 2287 }; 2288 }; 2289 2290 port@1 { 2291 reg = <1>; 2292 2293 mdss_dp_out: endpoint { 2294 }; 2295 }; 2296 }; 2297 2298 dp_opp_table: opp-table { 2299 compatible = "operating-points-v2"; 2300 2301 opp-160000000 { 2302 opp-hz = /bits/ 64 <160000000>; 2303 required-opps = <&rpmhpd_opp_low_svs>; 2304 }; 2305 2306 opp-270000000 { 2307 opp-hz = /bits/ 64 <270000000>; 2308 required-opps = <&rpmhpd_opp_svs>; 2309 }; 2310 2311 opp-540000000 { 2312 opp-hz = /bits/ 64 <540000000>; 2313 required-opps = <&rpmhpd_opp_svs_l1>; 2314 }; 2315 2316 opp-810000000 { 2317 opp-hz = /bits/ 64 <810000000>; 2318 required-opps = <&rpmhpd_opp_nom>; 2319 }; 2320 }; 2321 }; 2322 2323 mdss_dsi0: dsi@ae94000 { 2324 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2325 reg = <0x0 0x0ae94000 0x0 0x400>; 2326 reg-names = "dsi_ctrl"; 2327 2328 interrupt-parent = <&mdss>; 2329 interrupts = <4>; 2330 2331 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2332 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2333 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2334 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2335 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2336 <&gcc GCC_DISP_AXI_CLK>; 2337 clock-names = "byte", 2338 "byte_intf", 2339 "pixel", 2340 "core", 2341 "iface", 2342 "bus"; 2343 2344 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2345 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2346 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2347 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2348 2349 operating-points-v2 = <&mdss_dsi_opp_table>; 2350 power-domains = <&rpmhpd SM6350_MX>; 2351 2352 phys = <&mdss_dsi0_phy>; 2353 phy-names = "dsi"; 2354 2355 #address-cells = <1>; 2356 #size-cells = <0>; 2357 2358 status = "disabled"; 2359 2360 ports { 2361 #address-cells = <1>; 2362 #size-cells = <0>; 2363 2364 port@0 { 2365 reg = <0>; 2366 2367 mdss_dsi0_in: endpoint { 2368 remote-endpoint = <&dpu_intf1_out>; 2369 }; 2370 }; 2371 2372 port@1 { 2373 reg = <1>; 2374 2375 mdss_dsi0_out: endpoint { 2376 }; 2377 }; 2378 }; 2379 2380 mdss_dsi_opp_table: opp-table { 2381 compatible = "operating-points-v2"; 2382 2383 opp-187500000 { 2384 opp-hz = /bits/ 64 <187500000>; 2385 required-opps = <&rpmhpd_opp_low_svs>; 2386 }; 2387 2388 opp-300000000 { 2389 opp-hz = /bits/ 64 <300000000>; 2390 required-opps = <&rpmhpd_opp_svs>; 2391 }; 2392 2393 opp-358000000 { 2394 opp-hz = /bits/ 64 <358000000>; 2395 required-opps = <&rpmhpd_opp_svs_l1>; 2396 }; 2397 }; 2398 }; 2399 2400 mdss_dsi0_phy: phy@ae94400 { 2401 compatible = "qcom,dsi-phy-10nm"; 2402 reg = <0x0 0x0ae94400 0x0 0x200>, 2403 <0x0 0x0ae94600 0x0 0x280>, 2404 <0x0 0x0ae94a00 0x0 0x1e0>; 2405 reg-names = "dsi_phy", 2406 "dsi_phy_lane", 2407 "dsi_pll"; 2408 2409 #clock-cells = <1>; 2410 #phy-cells = <0>; 2411 2412 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2413 <&rpmhcc RPMH_CXO_CLK>; 2414 clock-names = "iface", "ref"; 2415 2416 status = "disabled"; 2417 }; 2418 }; 2419 2420 dispcc: clock-controller@af00000 { 2421 compatible = "qcom,sm6350-dispcc"; 2422 reg = <0x0 0x0af00000 0x0 0x20000>; 2423 clocks = <&rpmhcc RPMH_CXO_CLK>, 2424 <&gcc GCC_DISP_GPLL0_CLK>, 2425 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2426 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2427 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2428 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2429 clock-names = "bi_tcxo", 2430 "gcc_disp_gpll0_clk", 2431 "dsi0_phy_pll_out_byteclk", 2432 "dsi0_phy_pll_out_dsiclk", 2433 "dp_phy_pll_link_clk", 2434 "dp_phy_pll_vco_div_clk"; 2435 #clock-cells = <1>; 2436 #reset-cells = <1>; 2437 #power-domain-cells = <1>; 2438 }; 2439 2440 pdc: interrupt-controller@b220000 { 2441 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2442 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; 2443 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2444 <125 63 1>, <126 655 12>, <138 139 15>; 2445 #interrupt-cells = <2>; 2446 interrupt-parent = <&intc>; 2447 interrupt-controller; 2448 }; 2449 2450 tsens0: thermal-sensor@c263000 { 2451 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2452 reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ 2453 <0x0 0x0c222000 0x0 0x8>; /* SROT */ 2454 #qcom,sensors = <16>; 2455 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2456 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2457 interrupt-names = "uplow", "critical"; 2458 #thermal-sensor-cells = <1>; 2459 }; 2460 2461 tsens1: thermal-sensor@c265000 { 2462 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2463 reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ 2464 <0x0 0x0c223000 0x0 0x8>; /* SROT */ 2465 #qcom,sensors = <16>; 2466 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2467 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2468 interrupt-names = "uplow", "critical"; 2469 #thermal-sensor-cells = <1>; 2470 }; 2471 2472 aoss_qmp: power-management@c300000 { 2473 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2474 reg = <0x0 0x0c300000 0x0 0x1000>; 2475 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2476 IRQ_TYPE_EDGE_RISING>; 2477 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2478 2479 #clock-cells = <0>; 2480 }; 2481 2482 spmi_bus: spmi@c440000 { 2483 compatible = "qcom,spmi-pmic-arb"; 2484 reg = <0x0 0x0c440000 0x0 0x1100>, 2485 <0x0 0x0c600000 0x0 0x2000000>, 2486 <0x0 0x0e600000 0x0 0x100000>, 2487 <0x0 0x0e700000 0x0 0xa0000>, 2488 <0x0 0x0c40a000 0x0 0x26000>; 2489 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2490 interrupt-names = "periph_irq"; 2491 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2492 qcom,ee = <0>; 2493 qcom,channel = <0>; 2494 #address-cells = <2>; 2495 #size-cells = <0>; 2496 interrupt-controller; 2497 #interrupt-cells = <4>; 2498 }; 2499 2500 tlmm: pinctrl@f100000 { 2501 compatible = "qcom,sm6350-tlmm"; 2502 reg = <0x0 0x0f100000 0x0 0x300000>; 2503 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2512 gpio-controller; 2513 #gpio-cells = <2>; 2514 interrupt-controller; 2515 #interrupt-cells = <2>; 2516 gpio-ranges = <&tlmm 0 0 157>; 2517 wakeup-parent = <&pdc>; 2518 2519 cci0_default: cci0-default-state { 2520 pins = "gpio39", "gpio40"; 2521 function = "cci_i2c"; 2522 drive-strength = <2>; 2523 bias-pull-up; 2524 }; 2525 2526 cci0_sleep: cci0-sleep-state { 2527 pins = "gpio39", "gpio40"; 2528 function = "cci_i2c"; 2529 drive-strength = <2>; 2530 bias-pull-down; 2531 }; 2532 2533 cci1_default: cci1-default-state { 2534 pins = "gpio41", "gpio42"; 2535 function = "cci_i2c"; 2536 drive-strength = <2>; 2537 bias-pull-up; 2538 }; 2539 2540 cci1_sleep: cci1-sleep-state { 2541 pins = "gpio41", "gpio42"; 2542 function = "cci_i2c"; 2543 drive-strength = <2>; 2544 bias-pull-down; 2545 }; 2546 2547 cci2_default: cci2-default-state { 2548 pins = "gpio43", "gpio44"; 2549 function = "cci_i2c"; 2550 drive-strength = <2>; 2551 bias-pull-up; 2552 }; 2553 2554 cci2_sleep: cci2-sleep-state { 2555 pins = "gpio43", "gpio44"; 2556 function = "cci_i2c"; 2557 drive-strength = <2>; 2558 bias-pull-down; 2559 }; 2560 2561 sdc2_off_state: sdc2-off-state { 2562 clk-pins { 2563 pins = "sdc2_clk"; 2564 drive-strength = <2>; 2565 bias-disable; 2566 }; 2567 2568 cmd-pins { 2569 pins = "sdc2_cmd"; 2570 drive-strength = <2>; 2571 bias-pull-up; 2572 }; 2573 2574 data-pins { 2575 pins = "sdc2_data"; 2576 drive-strength = <2>; 2577 bias-pull-up; 2578 }; 2579 }; 2580 2581 sdc2_on_state: sdc2-on-state { 2582 clk-pins { 2583 pins = "sdc2_clk"; 2584 drive-strength = <16>; 2585 bias-disable; 2586 }; 2587 2588 cmd-pins { 2589 pins = "sdc2_cmd"; 2590 drive-strength = <10>; 2591 bias-pull-up; 2592 }; 2593 2594 data-pins { 2595 pins = "sdc2_data"; 2596 drive-strength = <10>; 2597 bias-pull-up; 2598 }; 2599 }; 2600 2601 qup_uart9_default: qup-uart9-default-state { 2602 pins = "gpio25", "gpio26"; 2603 function = "qup13_f2"; 2604 drive-strength = <2>; 2605 bias-disable; 2606 }; 2607 2608 qup_i2c0_default: qup-i2c0-default-state { 2609 pins = "gpio0", "gpio1"; 2610 function = "qup00"; 2611 drive-strength = <2>; 2612 bias-pull-up; 2613 }; 2614 2615 qup_i2c2_default: qup-i2c2-default-state { 2616 pins = "gpio45", "gpio46"; 2617 function = "qup02"; 2618 drive-strength = <2>; 2619 bias-pull-up; 2620 }; 2621 2622 qup_i2c6_default: qup-i2c6-default-state { 2623 pins = "gpio13", "gpio14"; 2624 function = "qup10"; 2625 drive-strength = <2>; 2626 bias-pull-up; 2627 }; 2628 2629 qup_i2c7_default: qup-i2c7-default-state { 2630 pins = "gpio27", "gpio28"; 2631 function = "qup11"; 2632 drive-strength = <2>; 2633 bias-pull-up; 2634 }; 2635 2636 qup_i2c8_default: qup-i2c8-default-state { 2637 pins = "gpio19", "gpio20"; 2638 function = "qup12"; 2639 drive-strength = <2>; 2640 bias-pull-up; 2641 }; 2642 2643 qup_i2c10_default: qup-i2c10-default-state { 2644 pins = "gpio4", "gpio5"; 2645 function = "qup14"; 2646 drive-strength = <2>; 2647 bias-pull-up; 2648 }; 2649 2650 qup_uart1_cts: qup-uart1-cts-default-state { 2651 pins = "gpio61"; 2652 function = "qup01"; 2653 drive-strength = <2>; 2654 bias-disable; 2655 }; 2656 2657 qup_uart1_rts: qup-uart1-rts-default-state { 2658 pins = "gpio62"; 2659 function = "qup01"; 2660 drive-strength = <2>; 2661 bias-pull-down; 2662 }; 2663 2664 qup_uart1_rx: qup-uart1-rx-default-state { 2665 pins = "gpio64"; 2666 function = "qup01"; 2667 drive-strength = <2>; 2668 bias-disable; 2669 }; 2670 2671 qup_uart1_tx: qup-uart1-tx-default-state { 2672 pins = "gpio63"; 2673 function = "qup01"; 2674 drive-strength = <2>; 2675 bias-pull-up; 2676 }; 2677 }; 2678 2679 apps_smmu: iommu@15000000 { 2680 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2681 reg = <0x0 0x15000000 0x0 0x100000>; 2682 #iommu-cells = <2>; 2683 #global-interrupts = <1>; 2684 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2685 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2686 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2687 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2688 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2689 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2690 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2691 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2695 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2728 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2729 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2731 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2734 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2735 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2736 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2737 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2738 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2739 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2740 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2741 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2742 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2743 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2744 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2745 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2746 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2747 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2748 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2749 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2765 dma-coherent; 2766 }; 2767 2768 intc: interrupt-controller@17a00000 { 2769 compatible = "arm,gic-v3"; 2770 #interrupt-cells = <3>; 2771 interrupt-controller; 2772 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2773 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2774 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2775 }; 2776 2777 watchdog@17c10000 { 2778 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2779 reg = <0x0 0x17c10000 0x0 0x1000>; 2780 clocks = <&sleep_clk>; 2781 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2782 }; 2783 2784 timer@17c20000 { 2785 compatible = "arm,armv7-timer-mem"; 2786 reg = <0x0 0x17c20000 0x0 0x1000>; 2787 clock-frequency = <19200000>; 2788 #address-cells = <1>; 2789 #size-cells = <1>; 2790 ranges = <0 0 0 0x20000000>; 2791 2792 frame@17c21000 { 2793 frame-number = <0>; 2794 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2796 reg = <0x17c21000 0x1000>, 2797 <0x17c22000 0x1000>; 2798 }; 2799 2800 frame@17c23000 { 2801 frame-number = <1>; 2802 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2803 reg = <0x17c23000 0x1000>; 2804 status = "disabled"; 2805 }; 2806 2807 frame@17c25000 { 2808 frame-number = <2>; 2809 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2810 reg = <0x17c25000 0x1000>; 2811 status = "disabled"; 2812 }; 2813 2814 frame@17c27000 { 2815 frame-number = <3>; 2816 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2817 reg = <0x17c27000 0x1000>; 2818 status = "disabled"; 2819 }; 2820 2821 frame@17c29000 { 2822 frame-number = <4>; 2823 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2824 reg = <0x17c29000 0x1000>; 2825 status = "disabled"; 2826 }; 2827 2828 frame@17c2b000 { 2829 frame-number = <5>; 2830 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2831 reg = <0x17c2b000 0x1000>; 2832 status = "disabled"; 2833 }; 2834 2835 frame@17c2d000 { 2836 frame-number = <6>; 2837 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2838 reg = <0x17c2d000 0x1000>; 2839 status = "disabled"; 2840 }; 2841 }; 2842 2843 apps_rsc: rsc@18200000 { 2844 compatible = "qcom,rpmh-rsc"; 2845 label = "apps_rsc"; 2846 reg = <0x0 0x18200000 0x0 0x10000>, 2847 <0x0 0x18210000 0x0 0x10000>, 2848 <0x0 0x18220000 0x0 0x10000>; 2849 reg-names = "drv-0", "drv-1", "drv-2"; 2850 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2853 qcom,tcs-offset = <0xd00>; 2854 qcom,drv-id = <2>; 2855 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2856 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2857 power-domains = <&cluster_pd>; 2858 2859 rpmhcc: clock-controller { 2860 compatible = "qcom,sm6350-rpmh-clk"; 2861 #clock-cells = <1>; 2862 clock-names = "xo"; 2863 clocks = <&xo_board>; 2864 }; 2865 2866 rpmhpd: power-controller { 2867 compatible = "qcom,sm6350-rpmhpd"; 2868 #power-domain-cells = <1>; 2869 operating-points-v2 = <&rpmhpd_opp_table>; 2870 2871 rpmhpd_opp_table: opp-table { 2872 compatible = "operating-points-v2"; 2873 2874 rpmhpd_opp_ret: opp1 { 2875 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2876 }; 2877 2878 rpmhpd_opp_min_svs: opp2 { 2879 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2880 }; 2881 2882 rpmhpd_opp_low_svs: opp3 { 2883 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2884 }; 2885 2886 rpmhpd_opp_svs: opp4 { 2887 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2888 }; 2889 2890 rpmhpd_opp_svs_l1: opp5 { 2891 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2892 }; 2893 2894 rpmhpd_opp_nom: opp6 { 2895 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2896 }; 2897 2898 rpmhpd_opp_nom_l1: opp7 { 2899 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2900 }; 2901 2902 rpmhpd_opp_nom_l2: opp8 { 2903 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2904 }; 2905 2906 rpmhpd_opp_turbo: opp9 { 2907 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2908 }; 2909 2910 rpmhpd_opp_turbo_l1: opp10 { 2911 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2912 }; 2913 }; 2914 }; 2915 2916 apps_bcm_voter: bcm-voter { 2917 compatible = "qcom,bcm-voter"; 2918 }; 2919 }; 2920 2921 osm_l3: interconnect@18321000 { 2922 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2923 reg = <0x0 0x18321000 0x0 0x1000>; 2924 2925 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2926 clock-names = "xo", "alternate"; 2927 2928 #interconnect-cells = <1>; 2929 }; 2930 2931 cpufreq_hw: cpufreq@18323000 { 2932 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2933 reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; 2934 reg-names = "freq-domain0", "freq-domain1"; 2935 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2936 clock-names = "xo", "alternate"; 2937 2938 #freq-domain-cells = <1>; 2939 #clock-cells = <1>; 2940 }; 2941 2942 wifi: wifi@18800000 { 2943 compatible = "qcom,wcn3990-wifi"; 2944 reg = <0x0 0x18800000 0x0 0x800000>; 2945 reg-names = "membase"; 2946 memory-region = <&wlan_fw_mem>; 2947 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2959 iommus = <&apps_smmu 0x20 0x1>; 2960 qcom,msa-fixed-perm; 2961 status = "disabled"; 2962 }; 2963 }; 2964 2965 thermal-zones { 2966 aoss0-thermal { 2967 thermal-sensors = <&tsens0 0>; 2968 2969 trips { 2970 aoss0-crit { 2971 temperature = <125000>; 2972 hysteresis = <0>; 2973 type = "critical"; 2974 }; 2975 }; 2976 }; 2977 2978 aoss1-thermal { 2979 thermal-sensors = <&tsens1 0>; 2980 2981 trips { 2982 aoss1-crit { 2983 temperature = <125000>; 2984 hysteresis = <0>; 2985 type = "critical"; 2986 }; 2987 }; 2988 }; 2989 2990 audio-thermal { 2991 thermal-sensors = <&tsens1 2>; 2992 2993 trips { 2994 audio-crit { 2995 temperature = <125000>; 2996 hysteresis = <0>; 2997 type = "critical"; 2998 }; 2999 }; 3000 }; 3001 3002 camera-thermal { 3003 thermal-sensors = <&tsens1 5>; 3004 3005 trips { 3006 camera-crit { 3007 temperature = <125000>; 3008 hysteresis = <0>; 3009 type = "critical"; 3010 }; 3011 }; 3012 }; 3013 3014 cpu0-thermal { 3015 thermal-sensors = <&tsens0 1>; 3016 3017 trips { 3018 cpu0_alert0: trip-point0 { 3019 temperature = <95000>; 3020 hysteresis = <2000>; 3021 type = "passive"; 3022 }; 3023 3024 cpu0-crit { 3025 temperature = <115000>; 3026 hysteresis = <0>; 3027 type = "critical"; 3028 }; 3029 }; 3030 3031 cooling-maps { 3032 map0 { 3033 trip = <&cpu0_alert0>; 3034 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3035 }; 3036 }; 3037 }; 3038 3039 cpu1-thermal { 3040 thermal-sensors = <&tsens0 2>; 3041 3042 trips { 3043 cpu1_alert0: trip-point0 { 3044 temperature = <95000>; 3045 hysteresis = <2000>; 3046 type = "passive"; 3047 }; 3048 3049 cpu1-crit { 3050 temperature = <115000>; 3051 hysteresis = <0>; 3052 type = "critical"; 3053 }; 3054 }; 3055 3056 cooling-maps { 3057 map0 { 3058 trip = <&cpu1_alert0>; 3059 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3060 }; 3061 }; 3062 }; 3063 3064 cpu2-thermal { 3065 thermal-sensors = <&tsens0 3>; 3066 3067 trips { 3068 cpu2_alert0: trip-point0 { 3069 temperature = <95000>; 3070 hysteresis = <2000>; 3071 type = "passive"; 3072 }; 3073 3074 cpu2-crit { 3075 temperature = <115000>; 3076 hysteresis = <0>; 3077 type = "critical"; 3078 }; 3079 }; 3080 3081 cooling-maps { 3082 map0 { 3083 trip = <&cpu2_alert0>; 3084 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3085 }; 3086 }; 3087 }; 3088 3089 cpu3-thermal { 3090 thermal-sensors = <&tsens0 4>; 3091 3092 trips { 3093 cpu3_alert0: trip-point0 { 3094 temperature = <95000>; 3095 hysteresis = <2000>; 3096 type = "passive"; 3097 }; 3098 3099 cpu3-crit { 3100 temperature = <115000>; 3101 hysteresis = <0>; 3102 type = "critical"; 3103 }; 3104 }; 3105 3106 cooling-maps { 3107 map0 { 3108 trip = <&cpu3_alert0>; 3109 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3110 }; 3111 }; 3112 }; 3113 3114 cpu4-thermal { 3115 thermal-sensors = <&tsens0 5>; 3116 3117 trips { 3118 cpu4_alert0: trip-point0 { 3119 temperature = <95000>; 3120 hysteresis = <2000>; 3121 type = "passive"; 3122 }; 3123 3124 cpu4-crit { 3125 temperature = <115000>; 3126 hysteresis = <0>; 3127 type = "critical"; 3128 }; 3129 }; 3130 3131 cooling-maps { 3132 map0 { 3133 trip = <&cpu4_alert0>; 3134 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3135 }; 3136 }; 3137 }; 3138 3139 cpu5-thermal { 3140 thermal-sensors = <&tsens0 6>; 3141 3142 trips { 3143 cpu5_alert0: trip-point0 { 3144 temperature = <95000>; 3145 hysteresis = <2000>; 3146 type = "passive"; 3147 }; 3148 3149 cpu5-crit { 3150 temperature = <115000>; 3151 hysteresis = <0>; 3152 type = "critical"; 3153 }; 3154 }; 3155 3156 cooling-maps { 3157 map0 { 3158 trip = <&cpu5_alert0>; 3159 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3160 }; 3161 }; 3162 }; 3163 3164 cpu6-left-thermal { 3165 thermal-sensors = <&tsens0 9>; 3166 3167 trips { 3168 cpu6_left_alert0: trip-point0 { 3169 temperature = <95000>; 3170 hysteresis = <2000>; 3171 type = "passive"; 3172 }; 3173 3174 cpu6-left-crit { 3175 temperature = <115000>; 3176 hysteresis = <0>; 3177 type = "critical"; 3178 }; 3179 }; 3180 3181 cooling-maps { 3182 map0 { 3183 trip = <&cpu6_left_alert0>; 3184 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3185 }; 3186 }; 3187 }; 3188 3189 cpu6-right-thermal { 3190 thermal-sensors = <&tsens0 10>; 3191 3192 trips { 3193 cpu6_right_alert0: trip-point0 { 3194 temperature = <95000>; 3195 hysteresis = <2000>; 3196 type = "passive"; 3197 }; 3198 3199 cpu6-right-crit { 3200 temperature = <115000>; 3201 hysteresis = <0>; 3202 type = "critical"; 3203 }; 3204 }; 3205 3206 cooling-maps { 3207 map0 { 3208 trip = <&cpu6_right_alert0>; 3209 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3210 }; 3211 }; 3212 }; 3213 3214 cpu7-left-thermal { 3215 thermal-sensors = <&tsens0 11>; 3216 3217 trips { 3218 cpu7_left_alert0: trip-point0 { 3219 temperature = <95000>; 3220 hysteresis = <2000>; 3221 type = "passive"; 3222 }; 3223 3224 cpu7-left-crit { 3225 temperature = <115000>; 3226 hysteresis = <0>; 3227 type = "critical"; 3228 }; 3229 }; 3230 3231 cooling-maps { 3232 map0 { 3233 trip = <&cpu7_left_alert0>; 3234 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3235 }; 3236 }; 3237 }; 3238 3239 cpu7-right-thermal { 3240 thermal-sensors = <&tsens0 12>; 3241 3242 trips { 3243 cpu7_right_alert0: trip-point0 { 3244 temperature = <95000>; 3245 hysteresis = <2000>; 3246 type = "passive"; 3247 }; 3248 3249 cpu7-right-crit { 3250 temperature = <115000>; 3251 hysteresis = <0>; 3252 type = "critical"; 3253 }; 3254 }; 3255 3256 cooling-maps { 3257 map0 { 3258 trip = <&cpu7_right_alert0>; 3259 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3260 }; 3261 }; 3262 }; 3263 3264 cpuss0-thermal { 3265 thermal-sensors = <&tsens0 7>; 3266 3267 trips { 3268 cpuss0-crit { 3269 temperature = <125000>; 3270 hysteresis = <0>; 3271 type = "critical"; 3272 }; 3273 }; 3274 }; 3275 3276 cpuss1-thermal { 3277 thermal-sensors = <&tsens0 8>; 3278 3279 trips { 3280 cpuss1-crit { 3281 temperature = <125000>; 3282 hysteresis = <0>; 3283 type = "critical"; 3284 }; 3285 }; 3286 }; 3287 3288 cwlan-thermal { 3289 thermal-sensors = <&tsens1 1>; 3290 3291 trips { 3292 cwlan-crit { 3293 temperature = <125000>; 3294 hysteresis = <0>; 3295 type = "critical"; 3296 }; 3297 }; 3298 }; 3299 3300 ddr-thermal { 3301 thermal-sensors = <&tsens1 3>; 3302 3303 trips { 3304 ddr-crit { 3305 temperature = <125000>; 3306 hysteresis = <0>; 3307 type = "critical"; 3308 }; 3309 }; 3310 }; 3311 3312 gpuss0-thermal { 3313 polling-delay-passive = <250>; 3314 3315 thermal-sensors = <&tsens0 13>; 3316 3317 trips { 3318 gpuss0_alert0: trip-point0 { 3319 temperature = <85000>; 3320 hysteresis = <2000>; 3321 type = "passive"; 3322 }; 3323 3324 gpuss0-crit { 3325 temperature = <110000>; 3326 hysteresis = <1000>; 3327 type = "critical"; 3328 }; 3329 }; 3330 3331 cooling-maps { 3332 map0 { 3333 trip = <&gpuss0_alert0>; 3334 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3335 }; 3336 }; 3337 }; 3338 3339 gpuss1-thermal { 3340 polling-delay-passive = <250>; 3341 3342 thermal-sensors = <&tsens0 14>; 3343 3344 trips { 3345 gpuss1_alert0: trip-point0 { 3346 temperature = <85000>; 3347 hysteresis = <2000>; 3348 type = "passive"; 3349 }; 3350 3351 gpuss1-crit { 3352 temperature = <110000>; 3353 hysteresis = <1000>; 3354 type = "critical"; 3355 }; 3356 }; 3357 3358 cooling-maps { 3359 map0 { 3360 trip = <&gpuss1_alert0>; 3361 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3362 }; 3363 }; 3364 }; 3365 3366 modem-core0-thermal { 3367 thermal-sensors = <&tsens1 6>; 3368 3369 trips { 3370 modem-core0-crit { 3371 temperature = <125000>; 3372 hysteresis = <0>; 3373 type = "critical"; 3374 }; 3375 }; 3376 }; 3377 3378 modem-core1-thermal { 3379 thermal-sensors = <&tsens1 7>; 3380 3381 trips { 3382 modem-core1-crit { 3383 temperature = <125000>; 3384 hysteresis = <0>; 3385 type = "critical"; 3386 }; 3387 }; 3388 }; 3389 3390 modem-scl-thermal { 3391 thermal-sensors = <&tsens1 9>; 3392 3393 trips { 3394 modem-scl-crit { 3395 temperature = <125000>; 3396 hysteresis = <0>; 3397 type = "critical"; 3398 }; 3399 }; 3400 }; 3401 3402 modem-vec-thermal { 3403 thermal-sensors = <&tsens1 8>; 3404 3405 trips { 3406 modem-vec-crit { 3407 temperature = <125000>; 3408 hysteresis = <0>; 3409 type = "critical"; 3410 }; 3411 }; 3412 }; 3413 3414 npu-thermal { 3415 thermal-sensors = <&tsens1 10>; 3416 3417 trips { 3418 npu-crit { 3419 temperature = <125000>; 3420 hysteresis = <0>; 3421 type = "critical"; 3422 }; 3423 }; 3424 }; 3425 3426 q6-hvx-thermal { 3427 thermal-sensors = <&tsens1 4>; 3428 3429 trips { 3430 q6-hvx-crit { 3431 temperature = <125000>; 3432 hysteresis = <0>; 3433 type = "critical"; 3434 }; 3435 }; 3436 }; 3437 3438 video-thermal { 3439 thermal-sensors = <&tsens1 11>; 3440 3441 trips { 3442 video-crit { 3443 temperature = <125000>; 3444 hysteresis = <0>; 3445 type = "critical"; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 timer { 3452 compatible = "arm,armv8-timer"; 3453 clock-frequency = <19200000>; 3454 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3455 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3456 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3457 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3458 }; 3459}; 3460