1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART
9 * 1) CLINT (Core Level Interruptor)
10 * 2) PLIC (Platform Level Interrupt Controller)
11 * 3) PRCI (Power, Reset, Clock, Interrupt)
12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13 * 5) Flash memory emulated as RAM
14 *
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16 * The OTP ROM and Flash boot code will be emulated in a future version.
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2 or later, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/cutils.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
35 #include "hw/boards.h"
36 #include "hw/loader.h"
37 #include "hw/sysbus.h"
38 #include "hw/misc/unimp.h"
39 #include "target/riscv/cpu.h"
40 #include "hw/riscv/riscv_hart.h"
41 #include "hw/riscv/sifive_e.h"
42 #include "hw/riscv/boot.h"
43 #include "hw/char/sifive_uart.h"
44 #include "hw/intc/riscv_aclint.h"
45 #include "hw/intc/sifive_plic.h"
46 #include "hw/misc/sifive_e_prci.h"
47 #include "hw/misc/sifive_e_aon.h"
48 #include "chardev/char.h"
49 #include "system/system.h"
50
51 static const MemMapEntry sifive_e_memmap[] = {
52 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
53 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
54 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
56 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
57 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
58 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
59 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
60 [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
61 [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
62 [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
63 [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
64 [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
65 [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
66 [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
67 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
68 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
69 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
70 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
71 };
72
sifive_e_machine_init(MachineState * machine)73 static void sifive_e_machine_init(MachineState *machine)
74 {
75 MachineClass *mc = MACHINE_GET_CLASS(machine);
76 const MemMapEntry *memmap = sifive_e_memmap;
77
78 SiFiveEState *s = RISCV_E_MACHINE(machine);
79 MemoryRegion *sys_mem = get_system_memory();
80 int i;
81 RISCVBootInfo boot_info;
82
83 if (machine->ram_size != mc->default_ram_size) {
84 char *sz = size_to_str(mc->default_ram_size);
85 error_report("Invalid RAM size, should be %s", sz);
86 g_free(sz);
87 exit(EXIT_FAILURE);
88 }
89
90 /* Initialize SoC */
91 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
92 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
93
94 /* Data Tightly Integrated Memory */
95 memory_region_add_subregion(sys_mem,
96 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
97
98 /* Mask ROM reset vector */
99 uint32_t reset_vec[4];
100
101 if (s->revb) {
102 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */
103 } else {
104 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */
105 }
106 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */
107
108 reset_vec[0] = reset_vec[3] = 0;
109
110 /* copy in the reset vector in little_endian byte order */
111 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
112 reset_vec[i] = cpu_to_le32(reset_vec[i]);
113 }
114 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
115 memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
116
117 riscv_boot_info_init(&boot_info, &s->soc.cpus);
118 if (machine->kernel_filename) {
119 riscv_load_kernel(machine, &boot_info,
120 memmap[SIFIVE_E_DEV_DTIM].base,
121 false, NULL);
122 }
123 }
124
sifive_e_machine_get_revb(Object * obj,Error ** errp)125 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
126 {
127 SiFiveEState *s = RISCV_E_MACHINE(obj);
128
129 return s->revb;
130 }
131
sifive_e_machine_set_revb(Object * obj,bool value,Error ** errp)132 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
133 {
134 SiFiveEState *s = RISCV_E_MACHINE(obj);
135
136 s->revb = value;
137 }
138
sifive_e_machine_instance_init(Object * obj)139 static void sifive_e_machine_instance_init(Object *obj)
140 {
141 SiFiveEState *s = RISCV_E_MACHINE(obj);
142
143 s->revb = false;
144 }
145
sifive_e_machine_class_init(ObjectClass * oc,const void * data)146 static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
147 {
148 MachineClass *mc = MACHINE_CLASS(oc);
149
150 mc->desc = "RISC-V Board compatible with SiFive E SDK";
151 mc->init = sifive_e_machine_init;
152 mc->max_cpus = 1;
153 mc->default_cpu_type = SIFIVE_E_CPU;
154 mc->default_ram_id = "riscv.sifive.e.ram";
155 mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
156
157 object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
158 sifive_e_machine_set_revb);
159 object_class_property_set_description(oc, "revb",
160 "Set on to tell QEMU that it should model "
161 "the revB HiFive1 board");
162 }
163
164 static const TypeInfo sifive_e_machine_typeinfo = {
165 .name = MACHINE_TYPE_NAME("sifive_e"),
166 .parent = TYPE_MACHINE,
167 .class_init = sifive_e_machine_class_init,
168 .instance_init = sifive_e_machine_instance_init,
169 .instance_size = sizeof(SiFiveEState),
170 };
171
sifive_e_machine_init_register_types(void)172 static void sifive_e_machine_init_register_types(void)
173 {
174 type_register_static(&sifive_e_machine_typeinfo);
175 }
176
type_init(sifive_e_machine_init_register_types)177 type_init(sifive_e_machine_init_register_types)
178
179 static void sifive_e_soc_init(Object *obj)
180 {
181 MachineState *ms = MACHINE(qdev_get_machine());
182 SiFiveESoCState *s = RISCV_E_SOC(obj);
183
184 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
185 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
186 &error_abort);
187 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
188 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
189 TYPE_SIFIVE_GPIO);
190 object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon,
191 TYPE_SIFIVE_E_AON);
192 }
193
sifive_e_soc_realize(DeviceState * dev,Error ** errp)194 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
195 {
196 MachineState *ms = MACHINE(qdev_get_machine());
197 const MemMapEntry *memmap = sifive_e_memmap;
198 SiFiveESoCState *s = RISCV_E_SOC(dev);
199 MemoryRegion *sys_mem = get_system_memory();
200
201 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
202 &error_abort);
203 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
204
205 /* Mask ROM */
206 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
207 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
208 memory_region_add_subregion(sys_mem,
209 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
210
211 /* MMIO */
212 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
213 (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
214 SIFIVE_E_PLIC_NUM_SOURCES,
215 SIFIVE_E_PLIC_NUM_PRIORITIES,
216 SIFIVE_E_PLIC_PRIORITY_BASE,
217 SIFIVE_E_PLIC_PENDING_BASE,
218 SIFIVE_E_PLIC_ENABLE_BASE,
219 SIFIVE_E_PLIC_ENABLE_STRIDE,
220 SIFIVE_E_PLIC_CONTEXT_BASE,
221 SIFIVE_E_PLIC_CONTEXT_STRIDE,
222 memmap[SIFIVE_E_DEV_PLIC].size);
223 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
224 0, ms->smp.cpus, false);
225 riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
226 RISCV_ACLINT_SWI_SIZE,
227 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
228 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
229 SIFIVE_E_LFCLK_DEFAULT_FREQ, false);
230 sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
231
232 /* AON */
233
234 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) {
235 return;
236 }
237
238 /* Map AON registers */
239 sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base);
240
241 /* GPIO */
242
243 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
244 return;
245 }
246
247 /* Map GPIO registers */
248 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
249
250 /* Pass all GPIOs to the SOC layer so they are available to the board */
251 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
252
253 /* Connect GPIO interrupts to the PLIC */
254 for (int i = 0; i < 32; i++) {
255 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
256 qdev_get_gpio_in(DEVICE(s->plic),
257 SIFIVE_E_GPIO0_IRQ0 + i));
258 }
259 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0,
260 qdev_get_gpio_in(DEVICE(s->plic),
261 SIFIVE_E_AON_WDT_IRQ));
262
263 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
264 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
265 create_unimplemented_device("riscv.sifive.e.qspi0",
266 memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
267 create_unimplemented_device("riscv.sifive.e.pwm0",
268 memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
269 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
270 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
271 create_unimplemented_device("riscv.sifive.e.qspi1",
272 memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
273 create_unimplemented_device("riscv.sifive.e.pwm1",
274 memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
275 create_unimplemented_device("riscv.sifive.e.qspi2",
276 memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
277 create_unimplemented_device("riscv.sifive.e.pwm2",
278 memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
279
280 /* Flash memory */
281 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
282 memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
283 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
284 &s->xip_mem);
285 }
286
sifive_e_soc_class_init(ObjectClass * oc,const void * data)287 static void sifive_e_soc_class_init(ObjectClass *oc, const void *data)
288 {
289 DeviceClass *dc = DEVICE_CLASS(oc);
290
291 dc->realize = sifive_e_soc_realize;
292 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
293 dc->user_creatable = false;
294 }
295
296 static const TypeInfo sifive_e_soc_type_info = {
297 .name = TYPE_RISCV_E_SOC,
298 .parent = TYPE_DEVICE,
299 .instance_size = sizeof(SiFiveESoCState),
300 .instance_init = sifive_e_soc_init,
301 .class_init = sifive_e_soc_class_init,
302 };
303
sifive_e_soc_register_types(void)304 static void sifive_e_soc_register_types(void)
305 {
306 type_register_static(&sifive_e_soc_type_info);
307 }
308
309 type_init(sifive_e_soc_register_types)
310