1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S8001 "A9X" SoC 4 * 5 * Other names: H8G, "Elba" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,twister"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled in by loader */ 35 operating-points-v2 = <&twister_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "apple,twister"; 43 reg = <0x0 0x1>; 44 cpu-release-addr = <0 0>; /* To be filled in by loader */ 45 operating-points-v2 = <&twister_opp>; 46 performance-domains = <&cpufreq>; 47 enable-method = "spin-table"; 48 device_type = "cpu"; 49 }; 50 }; 51 52 twister_opp: opp-table { 53 compatible = "operating-points-v2"; 54 55 opp01 { 56 opp-hz = /bits/ 64 <300000000>; 57 opp-level = <1>; 58 clock-latency-ns = <800>; 59 }; 60 opp02 { 61 opp-hz = /bits/ 64 <396000000>; 62 opp-level = <2>; 63 clock-latency-ns = <53000>; 64 }; 65 opp03 { 66 opp-hz = /bits/ 64 <792000000>; 67 opp-level = <3>; 68 clock-latency-ns = <18000>; 69 }; 70 opp04 { 71 opp-hz = /bits/ 64 <1080000000>; 72 opp-level = <4>; 73 clock-latency-ns = <21000>; 74 }; 75 opp05 { 76 opp-hz = /bits/ 64 <1440000000>; 77 opp-level = <5>; 78 clock-latency-ns = <25000>; 79 }; 80 opp06 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-level = <6>; 83 clock-latency-ns = <33000>; 84 }; 85 opp07 { 86 opp-hz = /bits/ 64 <2160000000>; 87 opp-level = <7>; 88 clock-latency-ns = <45000>; 89 }; 90#if 0 91 /* Not available until CPU deep sleep is implemented */ 92 opp08 { 93 opp-hz = /bits/ 64 <2160000000>; 94 opp-level = <8>; 95 clock-latency-ns = <45000>; 96 turbo-mode; 97 }; 98#endif 99 }; 100 101 soc { 102 compatible = "simple-bus"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 nonposted-mmio; 106 ranges; 107 108 cpufreq: performance-controller@202220000 { 109 compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 110 reg = <0x2 0x02220000 0 0x1000>; 111 #performance-domain-cells = <0>; 112 }; 113 114 serial0: serial@20a0c0000 { 115 compatible = "apple,s5l-uart"; 116 reg = <0x2 0x0a0c0000 0x0 0x4000>; 117 reg-io-width = <4>; 118 interrupt-parent = <&aic>; 119 interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; 120 /* Use the bootloader-enabled clocks for now. */ 121 clocks = <&clkref>, <&clkref>; 122 clock-names = "uart", "clk_uart_baud0"; 123 power-domains = <&ps_uart0>; 124 status = "disabled"; 125 }; 126 127 pmgr: power-management@20e000000 { 128 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 132 reg = <0x2 0xe000000 0 0x8c000>; 133 }; 134 135 aic: interrupt-controller@20e100000 { 136 compatible = "apple,s8000-aic", "apple,aic"; 137 reg = <0x2 0x0e100000 0x0 0x100000>; 138 #interrupt-cells = <3>; 139 interrupt-controller; 140 power-domains = <&ps_aic>; 141 }; 142 143 pinctrl_ap: pinctrl@20f100000 { 144 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 145 reg = <0x2 0x0f100000 0x0 0x100000>; 146 power-domains = <&ps_gpio>; 147 148 gpio-controller; 149 #gpio-cells = <2>; 150 gpio-ranges = <&pinctrl_ap 0 0 219>; 151 apple,npins = <219>; 152 153 interrupt-controller; 154 #interrupt-cells = <2>; 155 interrupt-parent = <&aic>; 156 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 157 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 158 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 159 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 160 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 161 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 162 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 163 }; 164 165 pinctrl_aop: pinctrl@2100f0000 { 166 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 167 reg = <0x2 0x100f0000 0x0 0x100000>; 168 power-domains = <&ps_aop_gpio>; 169 170 gpio-controller; 171 #gpio-cells = <2>; 172 gpio-ranges = <&pinctrl_aop 0 0 28>; 173 apple,npins = <28>; 174 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 interrupt-parent = <&aic>; 178 interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 179 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 180 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 181 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 182 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 183 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 184 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; 185 }; 186 187 pmgr_mini: power-management@210200000 { 188 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 192 reg = <0x2 0x10200000 0 0x84000>; 193 }; 194 195 wdt: watchdog@2102b0000 { 196 compatible = "apple,s8000-wdt", "apple,wdt"; 197 reg = <0x2 0x102b0000 0x0 0x4000>; 198 clocks = <&clkref>; 199 interrupt-parent = <&aic>; 200 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 201 }; 202 }; 203 204 timer { 205 compatible = "arm,armv8-timer"; 206 interrupt-parent = <&aic>; 207 interrupt-names = "phys", "virt"; 208 /* Note that A9X doesn't actually have a hypervisor (EL2 is not implemented). */ 209 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 210 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 211 }; 212}; 213 214#include "s8001-pmgr.dtsi" 215