1 /****************************************************************************** 2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 3 * 4 * This program is distributed in the hope that it will be useful, but WITHOUT 5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 7 * more details. 8 * 9 * You should have received a copy of the GNU General Public License along with 10 * this program; if not, write to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 12 * 13 * The full GNU General Public License is included in this distribution in the 14 * file called LICENSE. 15 * 16 * Contact Information: 17 * wlanfae <wlanfae@realtek.com> 18 ******************************************************************************/ 19 #ifndef __R8192UDM_H__ 20 #define __R8192UDM_H__ 21 22 23 /*--------------------------Define Parameters-------------------------------*/ 24 #define OFDM_Table_Length 19 25 #define CCK_Table_length 12 26 27 #define DM_DIG_THRESH_HIGH 40 28 #define DM_DIG_THRESH_LOW 35 29 30 #define DM_FALSEALARM_THRESH_LOW 40 31 #define DM_FALSEALARM_THRESH_HIGH 1000 32 33 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75 34 #define DM_DIG_HIGH_PWR_THRESH_LOW 70 35 36 #define BW_AUTO_SWITCH_HIGH_LOW 25 37 #define BW_AUTO_SWITCH_LOW_HIGH 30 38 39 #define DM_check_fsync_time_interval 500 40 41 42 #define DM_DIG_BACKOFF 12 43 #define DM_DIG_MAX 0x36 44 #define DM_DIG_MIN 0x1c 45 #define DM_DIG_MIN_Netcore 0x12 46 47 #define DM_DIG_BACKOFF_MAX 12 48 #define DM_DIG_BACKOFF_MIN -4 49 50 #define RxPathSelection_SS_TH_low 30 51 #define RxPathSelection_diff_TH 18 52 53 #define RateAdaptiveTH_High 50 54 #define RateAdaptiveTH_Low_20M 30 55 #define RateAdaptiveTH_Low_40M 10 56 #define VeryLowRSSI 15 57 58 #define CTSToSelfTHVal 35 59 60 #define WAIotTHVal 25 61 62 #define E_FOR_TX_POWER_TRACK 300 63 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 64 #define TX_POWER_NEAR_FIELD_THRESH_LOW 62 65 #define TX_POWER_ATHEROAP_THRESH_HIGH 78 66 #define TX_POWER_ATHEROAP_THRESH_LOW 72 67 68 #define Current_Tx_Rate_Reg 0x1e0 69 #define Initial_Tx_Rate_Reg 0x1e1 70 #define Tx_Retry_Count_Reg 0x1ac 71 #define RegC38_TH 20 72 73 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 74 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 75 76 #define TxHighPwrLevel_Normal 0 77 #define TxHighPwrLevel_Level1 1 78 #define TxHighPwrLevel_Level2 2 79 80 #define DM_Type_ByFW 0 81 #define DM_Type_ByDriver 1 82 83 /*--------------------------Define Parameters-------------------------------*/ 84 85 86 /*------------------------------Define structure----------------------------*/ 87 struct dig_t { 88 u8 dig_enable_flag; 89 u8 dig_algorithm; 90 u8 Dig_TwoPort_Algorithm; 91 u8 Dig_Ext_Port_Stage; 92 u8 dbg_mode; 93 u8 dig_algorithm_switch; 94 95 long rssi_low_thresh; 96 long rssi_high_thresh; 97 98 u32 FALowThresh; 99 u32 FAHighThresh; 100 101 long rssi_high_power_lowthresh; 102 long rssi_high_power_highthresh; 103 104 u8 dig_state; 105 u8 dig_highpwr_state; 106 u8 CurSTAConnectState; 107 u8 PreSTAConnectState; 108 u8 CurAPConnectState; 109 u8 PreAPConnectState; 110 111 u8 curpd_thstate; 112 u8 prepd_thstate; 113 u8 curcs_ratio_state; 114 u8 precs_ratio_state; 115 116 u32 pre_ig_value; 117 u32 cur_ig_value; 118 119 u8 Backoff_Enable_Flag; 120 u8 backoff_val; 121 char BackoffVal_range_max; 122 char BackoffVal_range_min; 123 u8 rx_gain_range_max; 124 u8 rx_gain_range_min; 125 bool initialgain_lowerbound_state; 126 127 long rssi_val; 128 }; 129 130 enum dm_dig_sta { 131 DM_STA_DIG_OFF = 0, 132 DM_STA_DIG_ON, 133 DM_STA_DIG_MAX 134 }; 135 136 137 enum dm_ratr_sta { 138 DM_RATR_STA_HIGH = 0, 139 DM_RATR_STA_MIDDLE = 1, 140 DM_RATR_STA_LOW = 2, 141 DM_RATR_STA_MAX 142 }; 143 144 enum dm_dig_op_sta { 145 DIG_TYPE_THRESH_HIGH = 0, 146 DIG_TYPE_THRESH_LOW = 1, 147 DIG_TYPE_THRESH_HIGHPWR_HIGH = 2, 148 DIG_TYPE_THRESH_HIGHPWR_LOW = 3, 149 DIG_TYPE_DBG_MODE = 4, 150 DIG_TYPE_RSSI = 5, 151 DIG_TYPE_ALGORITHM = 6, 152 DIG_TYPE_BACKOFF = 7, 153 DIG_TYPE_PWDB_FACTOR = 8, 154 DIG_TYPE_RX_GAIN_MIN = 9, 155 DIG_TYPE_RX_GAIN_MAX = 10, 156 DIG_TYPE_ENABLE = 20, 157 DIG_TYPE_DISABLE = 30, 158 DIG_OP_TYPE_MAX 159 }; 160 161 enum dm_dig_alg { 162 DIG_ALGO_BY_FALSE_ALARM = 0, 163 DIG_ALGO_BY_RSSI = 1, 164 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2, 165 DIG_ALGO_BY_TOW_PORT = 3, 166 DIG_ALGO_MAX 167 }; 168 169 enum dm_dig_two_port_alg { 170 DIG_TWO_PORT_ALGO_RSSI = 0, 171 DIG_TWO_PORT_ALGO_FALSE_ALARM = 1, 172 }; 173 174 175 enum dm_dig_ext_port_alg { 176 DIG_EXT_PORT_STAGE_0 = 0, 177 DIG_EXT_PORT_STAGE_1 = 1, 178 DIG_EXT_PORT_STAGE_2 = 2, 179 DIG_EXT_PORT_STAGE_3 = 3, 180 DIG_EXT_PORT_STAGE_MAX = 4, 181 }; 182 183 enum dm_dig_dbg { 184 DIG_DBG_OFF = 0, 185 DIG_DBG_ON = 1, 186 DIG_DBG_MAX 187 }; 188 189 enum dm_dig_connect { 190 DIG_STA_DISCONNECT = 0, 191 DIG_STA_CONNECT = 1, 192 DIG_STA_BEFORE_CONNECT = 2, 193 DIG_AP_DISCONNECT = 3, 194 DIG_AP_CONNECT = 4, 195 DIG_AP_ADD_STATION = 5, 196 DIG_CONNECT_MAX 197 }; 198 199 enum dm_dig_pd_th { 200 DIG_PD_AT_LOW_POWER = 0, 201 DIG_PD_AT_NORMAL_POWER = 1, 202 DIG_PD_AT_HIGH_POWER = 2, 203 DIG_PD_MAX 204 }; 205 206 enum dm_dig_cs_ratio { 207 DIG_CS_RATIO_LOWER = 0, 208 DIG_CS_RATIO_HIGHER = 1, 209 DIG_CS_MAX 210 }; 211 212 struct drx_path_sel { 213 u8 Enable; 214 u8 DbgMode; 215 u8 cck_method; 216 u8 cck_Rx_path; 217 218 u8 SS_TH_low; 219 u8 diff_TH; 220 u8 disabledRF; 221 u8 reserved; 222 223 u8 rf_rssi[4]; 224 u8 rf_enable_rssi_th[4]; 225 long cck_pwdb_sta[4]; 226 }; 227 228 enum dm_cck_rx_path_method { 229 CCK_Rx_Version_1 = 0, 230 CCK_Rx_Version_2 = 1, 231 CCK_Rx_Version_MAX 232 }; 233 234 235 enum dm_dbg { 236 DM_DBG_OFF = 0, 237 DM_DBG_ON = 1, 238 DM_DBG_MAX 239 }; 240 241 struct dcmd_txcmd { 242 u32 Op; 243 u32 Length; 244 u32 Value; 245 }; 246 /*------------------------------Define structure----------------------------*/ 247 248 249 /*------------------------Export global variable----------------------------*/ 250 extern struct dig_t dm_digtable; 251 extern u8 dm_shadow[16][256]; 252 extern struct drx_path_sel DM_RxPathSelTable; 253 254 extern u8 test_flag; 255 /*------------------------Export global variable----------------------------*/ 256 257 258 /*------------------------Export Marco Definition---------------------------*/ 259 #define DM_APInitGainChangeNotify(Event) \ 260 { \ 261 dm_digtable.CurAPConnectState = Event; \ 262 } 263 /*------------------------Export Marco Definition---------------------------*/ 264 265 266 /*--------------------------Exported Function prototype---------------------*/ 267 /*--------------------------Exported Function prototype---------------------*/ 268 extern void init_hal_dm(struct net_device *dev); 269 extern void deinit_hal_dm(struct net_device *dev); 270 271 extern void hal_dm_watchdog(struct net_device *dev); 272 273 274 extern void init_rate_adaptive(struct net_device *dev); 275 extern void dm_txpower_trackingcallback(void *data); 276 277 extern void dm_cck_txpower_adjust(struct net_device *dev, bool binch14); 278 279 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); 280 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); 281 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, 282 u32 dm_type, 283 u32 dm_value); 284 extern void DM_ChangeFsyncSetting(struct net_device *dev, 285 s32 DM_Type, 286 s32 DM_Value); 287 extern void dm_force_tx_fw_info(struct net_device *dev, 288 u32 force_type, 289 u32 force_value); 290 extern void dm_init_edca_turbo(struct net_device *dev); 291 extern void dm_rf_operation_test_callback(unsigned long data); 292 extern void dm_rf_pathcheck_workitemcallback(void *data); 293 extern void dm_fsync_timer_callback(unsigned long data); 294 extern void dm_check_fsync(struct net_device *dev); 295 extern void dm_shadow_init(struct net_device *dev); 296 extern void dm_initialize_txpower_tracking(struct net_device *dev); 297 extern void dm_CheckRfCtrlGPIO(void *data); 298 extern void dm_InitRateAdaptiveMask(struct net_device *dev); 299 extern void init_hal_dm(struct net_device *dev); 300 extern void deinit_hal_dm(struct net_device *dev); 301 extern void hal_dm_watchdog(struct net_device *dev); 302 extern void init_rate_adaptive(struct net_device *dev); 303 extern void dm_txpower_trackingcallback(void *data); 304 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev); 305 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev); 306 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev, 307 u32 dm_type, 308 u32 dm_value); 309 extern void DM_ChangeFsyncSetting(struct net_device *dev, 310 s32 DM_Type, 311 s32 DM_Value); 312 extern void dm_force_tx_fw_info(struct net_device *dev, 313 u32 force_type, 314 u32 force_value); 315 extern void dm_init_edca_turbo(struct net_device *dev); 316 extern void dm_rf_operation_test_callback(unsigned long data); 317 extern void dm_rf_pathcheck_workitemcallback(void *data); 318 extern void dm_fsync_timer_callback(unsigned long data); 319 extern void dm_check_fsync(struct net_device *dev); 320 extern void dm_shadow_init(struct net_device *dev); 321 extern void dm_initialize_txpower_tracking(struct net_device *dev); 322 extern void dm_CheckRfCtrlGPIO(void *data); 323 324 #endif /*__R8192UDM_H__ */ 325