1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RoCE HSI File - Autogenerated 37 */ 38 39 #ifndef __BNXT_RE_HSI_H__ 40 #define __BNXT_RE_HSI_H__ 41 42 /* include linux/bnxt/hsi.h */ 43 #include <linux/bnxt/hsi.h> 44 45 /* tx_doorbell (size:32b/4B) */ 46 struct tx_doorbell { 47 __le32 key_idx; 48 #define TX_DOORBELL_IDX_MASK 0xffffffUL 49 #define TX_DOORBELL_IDX_SFT 0 50 #define TX_DOORBELL_KEY_MASK 0xf0000000UL 51 #define TX_DOORBELL_KEY_SFT 28 52 #define TX_DOORBELL_KEY_TX (0x0UL << 28) 53 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX 54 }; 55 56 /* rx_doorbell (size:32b/4B) */ 57 struct rx_doorbell { 58 __le32 key_idx; 59 #define RX_DOORBELL_IDX_MASK 0xffffffUL 60 #define RX_DOORBELL_IDX_SFT 0 61 #define RX_DOORBELL_KEY_MASK 0xf0000000UL 62 #define RX_DOORBELL_KEY_SFT 28 63 #define RX_DOORBELL_KEY_RX (0x1UL << 28) 64 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX 65 }; 66 67 /* cmpl_doorbell (size:32b/4B) */ 68 struct cmpl_doorbell { 69 __le32 key_mask_valid_idx; 70 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL 71 #define CMPL_DOORBELL_IDX_SFT 0 72 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL 73 #define CMPL_DOORBELL_MASK 0x8000000UL 74 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL 75 #define CMPL_DOORBELL_KEY_SFT 28 76 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28) 77 #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL 78 }; 79 80 /* status_doorbell (size:32b/4B) */ 81 struct status_doorbell { 82 __le32 key_idx; 83 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL 84 #define STATUS_DOORBELL_IDX_SFT 0 85 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL 86 #define STATUS_DOORBELL_KEY_SFT 28 87 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28) 88 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT 89 }; 90 91 /* cmdq_init (size:128b/16B) */ 92 struct cmdq_init { 93 __le64 cmdq_pbl; 94 __le16 cmdq_size_cmdq_lvl; 95 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL 96 #define CMDQ_INIT_CMDQ_LVL_SFT 0 97 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL 98 #define CMDQ_INIT_CMDQ_SIZE_SFT 2 99 __le16 creq_ring_id; 100 __le32 prod_idx; 101 }; 102 103 /* cmdq_base (size:128b/16B) */ 104 struct cmdq_base { 105 u8 opcode; 106 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL 107 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL 108 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL 109 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL 110 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL 111 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL 112 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL 113 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL 114 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL 115 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL 116 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL 117 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL 118 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL 119 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL 120 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL 121 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL 122 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL 123 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL 124 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL 125 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL 126 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL 127 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL 128 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL 129 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL 130 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL 131 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL 132 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL 133 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL 134 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL 135 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL 136 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL 137 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL 138 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL 139 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL 140 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL 141 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL 142 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL 143 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 144 #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL 145 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL 146 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 147 #define CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG 0x99UL 148 #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG 149 u8 cmd_size; 150 __le16 flags; 151 __le16 cookie; 152 u8 resp_size; 153 u8 reserved8; 154 __le64 resp_addr; 155 }; 156 157 /* creq_base (size:128b/16B) */ 158 struct creq_base { 159 u8 type; 160 #define CREQ_BASE_TYPE_MASK 0x3fUL 161 #define CREQ_BASE_TYPE_SFT 0 162 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL 163 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL 164 #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT 165 u8 reserved56[7]; 166 u8 v; 167 #define CREQ_BASE_V 0x1UL 168 u8 event; 169 u8 reserved48[6]; 170 }; 171 172 /* cmdq_query_version (size:128b/16B) */ 173 struct cmdq_query_version { 174 u8 opcode; 175 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL 176 #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 177 u8 cmd_size; 178 __le16 flags; 179 __le16 cookie; 180 u8 resp_size; 181 u8 reserved8; 182 __le64 resp_addr; 183 }; 184 185 /* creq_query_version_resp (size:128b/16B) */ 186 struct creq_query_version_resp { 187 u8 type; 188 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL 189 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 190 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL 191 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 192 u8 status; 193 __le16 cookie; 194 u8 fw_maj; 195 u8 fw_minor; 196 u8 fw_bld; 197 u8 fw_rsvd; 198 u8 v; 199 #define CREQ_QUERY_VERSION_RESP_V 0x1UL 200 u8 event; 201 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL 202 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST \ 203 CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 204 __le16 reserved16; 205 u8 intf_maj; 206 u8 intf_minor; 207 u8 intf_bld; 208 u8 intf_rsvd; 209 }; 210 211 /* cmdq_initialize_fw (size:896b/112B) */ 212 struct cmdq_initialize_fw { 213 u8 opcode; 214 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL 215 #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 216 u8 cmd_size; 217 __le16 flags; 218 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 219 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL 220 #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED 0x8UL 221 #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT 0x10UL 222 #define CMDQ_INITIALIZE_FW_FLAGS_MIRROR_ON_ROCE_SUPPORTED 0x80UL 223 __le16 cookie; 224 u8 resp_size; 225 u8 reserved8; 226 __le64 resp_addr; 227 u8 qpc_pg_size_qpc_lvl; 228 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL 229 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 230 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL 231 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL 232 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL 233 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 234 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL 235 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 236 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4) 237 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4) 238 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4) 239 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4) 240 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4) 241 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4) 242 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G 243 u8 mrw_pg_size_mrw_lvl; 244 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL 245 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 246 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL 247 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL 248 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL 249 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 250 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL 251 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 252 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4) 253 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4) 254 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4) 255 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4) 256 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4) 257 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4) 258 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G 259 u8 srq_pg_size_srq_lvl; 260 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL 261 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 262 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL 263 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL 264 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL 265 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 266 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL 267 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 268 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 269 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 270 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 271 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 272 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 273 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 274 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G 275 u8 cq_pg_size_cq_lvl; 276 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL 277 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 278 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL 279 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL 280 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL 281 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 282 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL 283 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 284 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4) 285 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4) 286 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4) 287 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4) 288 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4) 289 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4) 290 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G 291 u8 tqm_pg_size_tqm_lvl; 292 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL 293 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 294 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL 295 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL 296 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL 297 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 298 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL 299 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 300 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4) 301 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4) 302 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4) 303 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4) 304 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4) 305 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4) 306 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G 307 u8 tim_pg_size_tim_lvl; 308 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL 309 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 310 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL 311 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL 312 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL 313 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 314 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL 315 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 316 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4) 317 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4) 318 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4) 319 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4) 320 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4) 321 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4) 322 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G 323 __le16 log2_dbr_pg_size; 324 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL 325 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 326 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL 327 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL 328 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL 329 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL 330 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL 331 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL 332 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL 333 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL 334 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL 335 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL 336 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL 337 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL 338 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL 339 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL 340 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL 341 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL 342 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \ 343 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 344 #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL 345 #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 346 __le64 qpc_page_dir; 347 __le64 mrw_page_dir; 348 __le64 srq_page_dir; 349 __le64 cq_page_dir; 350 __le64 tqm_page_dir; 351 __le64 tim_page_dir; 352 __le32 number_of_qp; 353 __le32 number_of_mrw; 354 __le32 number_of_srq; 355 __le32 number_of_cq; 356 __le32 max_qp_per_vf; 357 __le32 max_mrw_per_vf; 358 __le32 max_srq_per_vf; 359 __le32 max_cq_per_vf; 360 __le32 max_gid_per_vf; 361 __le32 stat_ctx_id; 362 }; 363 364 /* creq_initialize_fw_resp (size:128b/16B) */ 365 struct creq_initialize_fw_resp { 366 u8 type; 367 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 368 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 369 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 370 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 371 u8 status; 372 __le16 cookie; 373 __le32 reserved32; 374 u8 v; 375 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL 376 u8 event; 377 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL 378 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \ 379 CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 380 u8 reserved48[6]; 381 }; 382 383 /* cmdq_deinitialize_fw (size:128b/16B) */ 384 struct cmdq_deinitialize_fw { 385 u8 opcode; 386 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL 387 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \ 388 CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 389 u8 cmd_size; 390 __le16 flags; 391 __le16 cookie; 392 u8 resp_size; 393 u8 reserved8; 394 __le64 resp_addr; 395 }; 396 397 /* creq_deinitialize_fw_resp (size:128b/16B) */ 398 struct creq_deinitialize_fw_resp { 399 u8 type; 400 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL 401 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 402 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL 403 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 404 u8 status; 405 __le16 cookie; 406 __le32 reserved32; 407 u8 v; 408 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL 409 u8 event; 410 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL 411 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \ 412 CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 413 u8 reserved48[6]; 414 }; 415 416 /* cmdq_create_qp (size:832b/104B) */ 417 struct cmdq_create_qp { 418 u8 opcode; 419 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL 420 #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP 421 u8 cmd_size; 422 __le16 flags; 423 __le16 cookie; 424 u8 resp_size; 425 u8 reserved8; 426 __le64 resp_addr; 427 __le64 qp_handle; 428 __le32 qp_flags; 429 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL 430 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL 431 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 432 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL 433 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL 434 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL 435 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL 436 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL 437 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED 0x100UL 438 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID 0x200UL 439 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 0x400UL 440 #define CMDQ_CREATE_QP_QP_FLAGS_LAST \ 441 CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 442 u8 type; 443 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL 444 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL 445 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL 446 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL 447 #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI 448 u8 sq_pg_size_sq_lvl; 449 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL 450 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 451 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL 452 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL 453 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL 454 #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 455 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL 456 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 457 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4) 458 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4) 459 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4) 460 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4) 461 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4) 462 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4) 463 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G 464 u8 rq_pg_size_rq_lvl; 465 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL 466 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 467 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL 468 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL 469 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL 470 #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 471 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL 472 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 473 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4) 474 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4) 475 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4) 476 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4) 477 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4) 478 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4) 479 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G 480 u8 unused_0; 481 __le32 dpi; 482 __le32 sq_size; 483 __le32 rq_size; 484 __le16 sq_fwo_sq_sge; 485 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL 486 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 487 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL 488 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 489 __le16 rq_fwo_rq_sge; 490 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL 491 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 492 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL 493 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 494 __le32 scq_cid; 495 __le32 rcq_cid; 496 __le32 srq_cid; 497 __le32 pd_id; 498 __le64 sq_pbl; 499 __le64 rq_pbl; 500 __le64 irrq_addr; 501 __le64 orrq_addr; 502 __le32 request_xid; 503 __le16 steering_tag; 504 __le16 reserved16; 505 }; 506 507 /* creq_create_qp_resp (size:128b/16B) */ 508 struct creq_create_qp_resp { 509 u8 type; 510 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL 511 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 512 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL 513 #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 514 u8 status; 515 __le16 cookie; 516 __le32 xid; 517 u8 v; 518 #define CREQ_CREATE_QP_RESP_V 0x1UL 519 u8 event; 520 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL 521 #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 522 u8 optimized_transmit_enabled; 523 u8 reserved48[5]; 524 }; 525 526 /* cmdq_destroy_qp (size:192b/24B) */ 527 struct cmdq_destroy_qp { 528 u8 opcode; 529 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL 530 #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 531 u8 cmd_size; 532 __le16 flags; 533 __le16 cookie; 534 u8 resp_size; 535 u8 reserved8; 536 __le64 resp_addr; 537 __le32 qp_cid; 538 __le32 unused_0; 539 }; 540 541 /* creq_destroy_qp_resp (size:128b/16B) */ 542 struct creq_destroy_qp_resp { 543 u8 type; 544 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL 545 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 546 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL 547 #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 548 u8 status; 549 __le16 cookie; 550 __le32 xid; 551 u8 v; 552 #define CREQ_DESTROY_QP_RESP_V 0x1UL 553 u8 event; 554 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL 555 #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 556 u8 reserved48[6]; 557 }; 558 559 /* cmdq_modify_qp (size:1024b/128B) */ 560 struct cmdq_modify_qp { 561 u8 opcode; 562 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL 563 #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 564 u8 cmd_size; 565 __le16 flags; 566 #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED 0x1UL 567 __le16 cookie; 568 u8 resp_size; 569 u8 qp_type; 570 #define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL 571 #define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL 572 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL 573 #define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL 574 #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI 575 __le64 resp_addr; 576 __le32 modify_mask; 577 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL 578 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL 579 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL 580 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL 581 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL 582 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL 583 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL 584 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL 585 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL 586 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL 587 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL 588 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL 589 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL 590 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL 591 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL 592 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL 593 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL 594 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL 595 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL 596 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL 597 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL 598 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL 599 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL 600 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL 601 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL 602 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL 603 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL 604 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL 605 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL 606 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL 607 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL 608 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL 609 __le32 qp_cid; 610 u8 network_type_en_sqd_async_notify_new_state; 611 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL 612 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 613 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL 614 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL 615 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL 616 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL 617 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL 618 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL 619 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL 620 #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR 621 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL 622 #define CMDQ_MODIFY_QP_UNUSED1 0x20UL 623 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL 624 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 625 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6) 626 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6) 627 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6) 628 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 629 u8 access; 630 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL 631 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 632 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL 633 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL 634 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL 635 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL 636 __le16 pkey; 637 __le32 qkey; 638 __le32 dgid[4]; 639 __le32 flow_label; 640 __le16 sgid_index; 641 u8 hop_limit; 642 u8 traffic_class; 643 __le16 dest_mac[3]; 644 u8 tos_dscp_tos_ecn; 645 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL 646 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 647 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL 648 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 649 u8 path_mtu_pingpong_push_enable; 650 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL 651 #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL 652 #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 653 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL 654 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 655 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4) 656 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4) 657 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4) 658 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4) 659 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4) 660 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4) 661 #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 662 u8 timeout; 663 u8 retry_cnt; 664 u8 rnr_retry; 665 u8 min_rnr_timer; 666 __le32 rq_psn; 667 __le32 sq_psn; 668 u8 max_rd_atomic; 669 u8 max_dest_rd_atomic; 670 __le16 enable_cc; 671 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL 672 #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL 673 #define CMDQ_MODIFY_QP_UNUSED15_SFT 1 674 __le32 sq_size; 675 __le32 rq_size; 676 __le16 sq_sge; 677 __le16 rq_sge; 678 __le32 max_inline_data; 679 __le32 dest_qp_id; 680 __le32 pingpong_push_dpi; 681 __le16 src_mac[3]; 682 __le16 vlan_pcp_vlan_dei_vlan_id; 683 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL 684 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 685 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL 686 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL 687 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 688 __le64 irrq_addr; 689 __le64 orrq_addr; 690 __le32 ext_modify_mask; 691 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL 692 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL 693 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID 0x8UL 694 __le32 ext_stats_ctx_id; 695 __le16 schq_id; 696 __le16 unused_0; 697 __le32 rate_limit; 698 }; 699 700 /* creq_modify_qp_resp (size:128b/16B) */ 701 struct creq_modify_qp_resp { 702 u8 type; 703 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL 704 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 705 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL 706 #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 707 u8 status; 708 __le16 cookie; 709 __le32 xid; 710 u8 v; 711 #define CREQ_MODIFY_QP_RESP_V 0x1UL 712 u8 event; 713 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL 714 #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 715 u8 pingpong_push_state_index_enabled; 716 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL 717 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL 718 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 719 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL 720 u8 shaper_allocation_status; 721 #define CREQ_MODIFY_QP_RESP_SHAPER_ALLOCATED 0x1UL 722 __le32 lag_src_mac; 723 }; 724 725 /* cmdq_query_qp (size:192b/24B) */ 726 struct cmdq_query_qp { 727 u8 opcode; 728 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL 729 #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP 730 u8 cmd_size; 731 __le16 flags; 732 __le16 cookie; 733 u8 resp_size; 734 u8 reserved8; 735 __le64 resp_addr; 736 __le32 qp_cid; 737 __le32 unused_0; 738 }; 739 740 /* creq_query_qp_resp (size:128b/16B) */ 741 struct creq_query_qp_resp { 742 u8 type; 743 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL 744 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 745 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL 746 #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 747 u8 status; 748 __le16 cookie; 749 __le32 size; 750 u8 v; 751 #define CREQ_QUERY_QP_RESP_V 0x1UL 752 u8 event; 753 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL 754 #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 755 u8 reserved48[6]; 756 }; 757 758 /* creq_query_qp_resp_sb (size:832b/104B) */ 759 struct creq_query_qp_resp_sb { 760 u8 opcode; 761 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL 762 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 763 u8 status; 764 __le16 cookie; 765 __le16 flags; 766 u8 resp_size; 767 u8 reserved8; 768 __le32 xid; 769 u8 en_sqd_async_notify_state; 770 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL 771 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 772 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL 773 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL 774 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL 775 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL 776 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL 777 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL 778 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL 779 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR 780 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL 781 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL 782 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 783 u8 access; 784 #define \ 785 CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\ 786 0xffUL 787 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\ 788 0 789 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL 790 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL 791 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL 792 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL 793 __le16 pkey; 794 __le32 qkey; 795 __le16 udp_src_port; 796 __le16 reserved16; 797 __le32 dgid[4]; 798 __le32 flow_label; 799 __le16 sgid_index; 800 u8 hop_limit; 801 u8 traffic_class; 802 __le16 dest_mac[3]; 803 __le16 path_mtu_dest_vlan_id; 804 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL 805 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 806 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL 807 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 808 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12) 809 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12) 810 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12) 811 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12) 812 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12) 813 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12) 814 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 815 u8 timeout; 816 u8 retry_cnt; 817 u8 rnr_retry; 818 u8 min_rnr_timer; 819 __le32 rq_psn; 820 __le32 sq_psn; 821 u8 max_rd_atomic; 822 u8 max_dest_rd_atomic; 823 u8 tos_dscp_tos_ecn; 824 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL 825 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 826 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL 827 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 828 u8 enable_cc; 829 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL 830 __le32 sq_size; 831 __le32 rq_size; 832 __le16 sq_sge; 833 __le16 rq_sge; 834 __le32 max_inline_data; 835 __le32 dest_qp_id; 836 __le16 port_id; 837 u8 unused_0; 838 u8 stat_collection_id; 839 __le16 src_mac[3]; 840 __le16 vlan_pcp_vlan_dei_vlan_id; 841 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL 842 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 843 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL 844 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL 845 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 846 }; 847 848 /* cmdq_query_qp_extend (size:192b/24B) */ 849 struct cmdq_query_qp_extend { 850 u8 opcode; 851 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL 852 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 853 u8 cmd_size; 854 __le16 flags; 855 __le16 cookie; 856 u8 resp_size; 857 u8 num_qps; 858 __le64 resp_addr; 859 __le32 function_id; 860 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL 861 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 862 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL 863 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 864 #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL 865 __le32 current_index; 866 }; 867 868 /* creq_query_qp_extend_resp (size:128b/16B) */ 869 struct creq_query_qp_extend_resp { 870 u8 type; 871 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL 872 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 873 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL 874 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 875 u8 status; 876 __le16 cookie; 877 __le32 size; 878 u8 v; 879 #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL 880 u8 event; 881 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL 882 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 883 __le16 reserved16; 884 __le32 current_index; 885 }; 886 887 /* creq_query_qp_extend_resp_sb (size:384b/48B) */ 888 struct creq_query_qp_extend_resp_sb { 889 u8 opcode; 890 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL 891 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \ 892 CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 893 u8 status; 894 __le16 cookie; 895 __le16 flags; 896 u8 resp_size; 897 u8 reserved8; 898 __le32 xid; 899 u8 state; 900 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL 901 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 902 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL 903 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL 904 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL 905 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL 906 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL 907 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL 908 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL 909 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 910 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL 911 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 912 u8 reserved_8; 913 __le16 port_id; 914 __le32 qkey; 915 __le16 sgid_index; 916 u8 network_type; 917 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL 918 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 919 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 920 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \ 921 CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 922 u8 unused_0; 923 __le32 dgid[4]; 924 __le32 dest_qp_id; 925 u8 stat_collection_id; 926 u8 reservred_8; 927 __le16 reserved_16; 928 }; 929 930 /* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ 931 struct creq_query_qp_extend_resp_sb_tlv { 932 __le16 cmd_discr; 933 u8 reserved_8b; 934 u8 tlv_flags; 935 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 936 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 937 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 938 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 939 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 940 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 941 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 942 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 943 __le16 tlv_type; 944 __le16 length; 945 u8 total_size; 946 u8 reserved56[7]; 947 u8 opcode; 948 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL 949 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \ 950 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 951 u8 status; 952 __le16 cookie; 953 __le16 flags; 954 u8 resp_size; 955 u8 reserved8; 956 __le32 xid; 957 u8 state; 958 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL 959 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 960 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL 961 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL 962 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL 963 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL 964 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL 965 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL 966 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL 967 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \ 968 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 969 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL 970 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 971 u8 reserved_8; 972 __le16 port_id; 973 __le32 qkey; 974 __le16 sgid_index; 975 u8 network_type; 976 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL 977 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL 978 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL 979 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \ 980 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 981 u8 unused_0; 982 __le32 dgid[4]; 983 __le32 dest_qp_id; 984 u8 stat_collection_id; 985 u8 reservred_8; 986 __le16 reserved_16; 987 }; 988 989 /* cmdq_create_srq (size:448b/56B) */ 990 struct cmdq_create_srq { 991 u8 opcode; 992 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL 993 #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 994 u8 cmd_size; 995 __le16 flags; 996 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL 997 __le16 cookie; 998 u8 resp_size; 999 u8 reserved8; 1000 __le64 resp_addr; 1001 __le64 srq_handle; 1002 __le16 pg_size_lvl; 1003 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL 1004 #define CMDQ_CREATE_SRQ_LVL_SFT 0 1005 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL 1006 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL 1007 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL 1008 #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 1009 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL 1010 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 1011 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2) 1012 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2) 1013 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2) 1014 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2) 1015 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2) 1016 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2) 1017 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G 1018 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL 1019 #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 1020 __le16 eventq_id; 1021 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL 1022 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 1023 #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL 1024 #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 1025 __le16 srq_size; 1026 __le16 srq_fwo; 1027 __le32 dpi; 1028 __le32 pd_id; 1029 __le64 pbl; 1030 __le16 steering_tag; 1031 u8 reserved48[6]; 1032 }; 1033 1034 /* creq_create_srq_resp (size:128b/16B) */ 1035 struct creq_create_srq_resp { 1036 u8 type; 1037 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL 1038 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 1039 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1040 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 1041 u8 status; 1042 __le16 cookie; 1043 __le32 xid; 1044 u8 v; 1045 #define CREQ_CREATE_SRQ_RESP_V 0x1UL 1046 u8 event; 1047 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL 1048 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 1049 u8 reserved48[6]; 1050 }; 1051 1052 /* cmdq_destroy_srq (size:192b/24B) */ 1053 struct cmdq_destroy_srq { 1054 u8 opcode; 1055 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL 1056 #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 1057 u8 cmd_size; 1058 __le16 flags; 1059 __le16 cookie; 1060 u8 resp_size; 1061 u8 reserved8; 1062 __le64 resp_addr; 1063 __le32 srq_cid; 1064 __le32 unused_0; 1065 }; 1066 1067 /* creq_destroy_srq_resp (size:128b/16B) */ 1068 struct creq_destroy_srq_resp { 1069 u8 type; 1070 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL 1071 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 1072 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1073 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 1074 u8 status; 1075 __le16 cookie; 1076 __le32 xid; 1077 u8 v; 1078 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL 1079 u8 event; 1080 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL 1081 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 1082 __le16 enable_for_arm[3]; 1083 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL 1084 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 1085 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL 1086 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 1087 }; 1088 1089 /* cmdq_query_srq (size:192b/24B) */ 1090 struct cmdq_query_srq { 1091 u8 opcode; 1092 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL 1093 #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 1094 u8 cmd_size; 1095 __le16 flags; 1096 __le16 cookie; 1097 u8 resp_size; 1098 u8 reserved8; 1099 __le64 resp_addr; 1100 __le32 srq_cid; 1101 __le32 unused_0; 1102 }; 1103 1104 /* creq_query_srq_resp (size:128b/16B) */ 1105 struct creq_query_srq_resp { 1106 u8 type; 1107 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL 1108 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 1109 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL 1110 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 1111 u8 status; 1112 __le16 cookie; 1113 __le32 size; 1114 u8 v; 1115 #define CREQ_QUERY_SRQ_RESP_V 0x1UL 1116 u8 event; 1117 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL 1118 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 1119 u8 reserved48[6]; 1120 }; 1121 1122 /* creq_query_srq_resp_sb (size:256b/32B) */ 1123 struct creq_query_srq_resp_sb { 1124 u8 opcode; 1125 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL 1126 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 1127 u8 status; 1128 __le16 cookie; 1129 __le16 flags; 1130 u8 resp_size; 1131 u8 reserved8; 1132 __le32 xid; 1133 __le16 srq_limit; 1134 __le16 reserved16; 1135 __le32 data[4]; 1136 }; 1137 1138 /* cmdq_create_cq (size:448b/56B) */ 1139 struct cmdq_create_cq { 1140 u8 opcode; 1141 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL 1142 #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 1143 u8 cmd_size; 1144 __le16 flags; 1145 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL 1146 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL 1147 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL 1148 #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID 0x8UL 1149 __le16 cookie; 1150 u8 resp_size; 1151 u8 reserved8; 1152 __le64 resp_addr; 1153 __le64 cq_handle; 1154 __le32 pg_size_lvl; 1155 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL 1156 #define CMDQ_CREATE_CQ_LVL_SFT 0 1157 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL 1158 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL 1159 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL 1160 #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 1161 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL 1162 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 1163 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1164 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1165 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1166 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1167 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1168 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1169 #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G 1170 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL 1171 #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 1172 __le32 cq_fco_cnq_id; 1173 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL 1174 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 1175 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL 1176 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 1177 __le32 dpi; 1178 __le32 cq_size; 1179 __le64 pbl; 1180 __le16 steering_tag; 1181 u8 reserved48[2]; 1182 __le32 coalescing; 1183 #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK 0x1ffUL 1184 #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0 1185 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK 0x3e00UL 1186 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9 1187 #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK 0x7c000UL 1188 #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14 1189 #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE 0x80000UL 1190 #define CMDQ_CREATE_CQ_UNUSED12_MASK 0xfff00000UL 1191 #define CMDQ_CREATE_CQ_UNUSED12_SFT 20 1192 __le64 reserved64; 1193 }; 1194 1195 /* creq_create_cq_resp (size:128b/16B) */ 1196 struct creq_create_cq_resp { 1197 u8 type; 1198 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL 1199 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 1200 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1201 #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 1202 u8 status; 1203 __le16 cookie; 1204 __le32 xid; 1205 u8 v; 1206 #define CREQ_CREATE_CQ_RESP_V 0x1UL 1207 u8 event; 1208 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL 1209 #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 1210 u8 reserved48[6]; 1211 }; 1212 1213 /* cmdq_destroy_cq (size:192b/24B) */ 1214 struct cmdq_destroy_cq { 1215 u8 opcode; 1216 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL 1217 #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 1218 u8 cmd_size; 1219 __le16 flags; 1220 __le16 cookie; 1221 u8 resp_size; 1222 u8 reserved8; 1223 __le64 resp_addr; 1224 __le32 cq_cid; 1225 __le32 unused_0; 1226 }; 1227 1228 /* creq_destroy_cq_resp (size:128b/16B) */ 1229 struct creq_destroy_cq_resp { 1230 u8 type; 1231 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL 1232 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 1233 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL 1234 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 1235 u8 status; 1236 __le16 cookie; 1237 __le32 xid; 1238 u8 v; 1239 #define CREQ_DESTROY_CQ_RESP_V 0x1UL 1240 u8 event; 1241 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL 1242 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 1243 __le16 cq_arm_lvl; 1244 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL 1245 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 1246 __le16 total_cnq_events; 1247 __le16 reserved16; 1248 }; 1249 1250 /* cmdq_resize_cq (size:320b/40B) */ 1251 struct cmdq_resize_cq { 1252 u8 opcode; 1253 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL 1254 #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 1255 u8 cmd_size; 1256 __le16 flags; 1257 __le16 cookie; 1258 u8 resp_size; 1259 u8 reserved8; 1260 __le64 resp_addr; 1261 __le32 cq_cid; 1262 __le32 new_cq_size_pg_size_lvl; 1263 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL 1264 #define CMDQ_RESIZE_CQ_LVL_SFT 0 1265 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL 1266 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL 1267 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL 1268 #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 1269 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL 1270 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 1271 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2) 1272 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2) 1273 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2) 1274 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2) 1275 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2) 1276 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2) 1277 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G 1278 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL 1279 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 1280 __le64 new_pbl; 1281 __le32 new_cq_fco; 1282 __le32 unused_0; 1283 }; 1284 1285 /* creq_resize_cq_resp (size:128b/16B) */ 1286 struct creq_resize_cq_resp { 1287 u8 type; 1288 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL 1289 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 1290 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL 1291 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 1292 u8 status; 1293 __le16 cookie; 1294 __le32 xid; 1295 u8 v; 1296 #define CREQ_RESIZE_CQ_RESP_V 0x1UL 1297 u8 event; 1298 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL 1299 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 1300 u8 reserved48[6]; 1301 }; 1302 1303 /* cmdq_allocate_mrw (size:256b/32B) */ 1304 struct cmdq_allocate_mrw { 1305 u8 opcode; 1306 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL 1307 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 1308 u8 cmd_size; 1309 __le16 flags; 1310 __le16 cookie; 1311 u8 resp_size; 1312 u8 reserved8; 1313 __le64 resp_addr; 1314 __le64 mrw_handle; 1315 u8 mrw_flags; 1316 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL 1317 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 1318 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL 1319 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL 1320 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL 1321 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL 1322 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL 1323 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 1324 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID 0x10UL 1325 #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xe0UL 1326 #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 5 1327 u8 access; 1328 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL 1329 __le16 steering_tag; 1330 __le32 pd_id; 1331 }; 1332 1333 /* creq_allocate_mrw_resp (size:128b/16B) */ 1334 struct creq_allocate_mrw_resp { 1335 u8 type; 1336 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL 1337 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 1338 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL 1339 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 1340 u8 status; 1341 __le16 cookie; 1342 __le32 xid; 1343 u8 v; 1344 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL 1345 u8 event; 1346 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL 1347 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 1348 u8 reserved48[6]; 1349 }; 1350 1351 /* cmdq_deallocate_key (size:192b/24B) */ 1352 struct cmdq_deallocate_key { 1353 u8 opcode; 1354 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL 1355 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 1356 u8 cmd_size; 1357 __le16 flags; 1358 __le16 cookie; 1359 u8 resp_size; 1360 u8 reserved8; 1361 __le64 resp_addr; 1362 u8 mrw_flags; 1363 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL 1364 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 1365 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL 1366 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL 1367 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL 1368 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL 1369 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL 1370 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 1371 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL 1372 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 1373 u8 unused24[3]; 1374 __le32 key; 1375 }; 1376 1377 /* creq_deallocate_key_resp (size:128b/16B) */ 1378 struct creq_deallocate_key_resp { 1379 u8 type; 1380 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL 1381 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 1382 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL 1383 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 1384 u8 status; 1385 __le16 cookie; 1386 __le32 xid; 1387 u8 v; 1388 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL 1389 u8 event; 1390 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL 1391 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 1392 __le16 reserved16; 1393 __le32 bound_window_info; 1394 }; 1395 1396 /* cmdq_register_mr (size:448b/56B) */ 1397 struct cmdq_register_mr { 1398 u8 opcode; 1399 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL 1400 #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 1401 u8 cmd_size; 1402 __le16 flags; 1403 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL 1404 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL 1405 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO 0x4UL 1406 __le16 cookie; 1407 u8 resp_size; 1408 u8 reserved8; 1409 __le64 resp_addr; 1410 u8 log2_pg_size_lvl; 1411 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL 1412 #define CMDQ_REGISTER_MR_LVL_SFT 0 1413 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL 1414 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL 1415 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL 1416 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 1417 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL 1418 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 1419 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2) 1420 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2) 1421 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2) 1422 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2) 1423 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2) 1424 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2) 1425 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2) 1426 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2) 1427 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G 1428 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL 1429 u8 access; 1430 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL 1431 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL 1432 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL 1433 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL 1434 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL 1435 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL 1436 __le16 log2_pbl_pg_size; 1437 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL 1438 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 1439 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL 1440 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL 1441 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL 1442 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL 1443 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL 1444 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL 1445 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL 1446 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL 1447 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 1448 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL 1449 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 1450 __le32 key; 1451 __le64 pbl; 1452 __le64 va; 1453 __le64 mr_size; 1454 __le16 steering_tag; 1455 u8 reserved48[6]; 1456 }; 1457 1458 /* creq_register_mr_resp (size:128b/16B) */ 1459 struct creq_register_mr_resp { 1460 u8 type; 1461 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL 1462 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 1463 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1464 #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 1465 u8 status; 1466 __le16 cookie; 1467 __le32 xid; 1468 u8 v; 1469 #define CREQ_REGISTER_MR_RESP_V 0x1UL 1470 u8 event; 1471 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL 1472 #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 1473 u8 reserved48[6]; 1474 }; 1475 1476 /* cmdq_deregister_mr (size:192b/24B) */ 1477 struct cmdq_deregister_mr { 1478 u8 opcode; 1479 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL 1480 #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 1481 u8 cmd_size; 1482 __le16 flags; 1483 __le16 cookie; 1484 u8 resp_size; 1485 u8 reserved8; 1486 __le64 resp_addr; 1487 __le32 lkey; 1488 __le32 unused_0; 1489 }; 1490 1491 /* creq_deregister_mr_resp (size:128b/16B) */ 1492 struct creq_deregister_mr_resp { 1493 u8 type; 1494 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL 1495 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 1496 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL 1497 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 1498 u8 status; 1499 __le16 cookie; 1500 __le32 xid; 1501 u8 v; 1502 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL 1503 u8 event; 1504 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL 1505 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 1506 __le16 reserved16; 1507 __le32 bound_windows; 1508 }; 1509 1510 /* cmdq_add_gid (size:384b/48B) */ 1511 struct cmdq_add_gid { 1512 u8 opcode; 1513 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL 1514 #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID 1515 u8 cmd_size; 1516 __le16 flags; 1517 __le16 cookie; 1518 u8 resp_size; 1519 u8 reserved8; 1520 __le64 resp_addr; 1521 __be32 gid[4]; 1522 __be16 src_mac[3]; 1523 __le16 vlan; 1524 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1525 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1526 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL 1527 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 1528 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL 1529 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 1530 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1531 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1532 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1533 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1534 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1535 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1536 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1537 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1538 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 1539 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL 1540 __le16 ipid; 1541 __le16 stats_ctx; 1542 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL 1543 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 1544 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1545 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1546 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1547 __le32 unused_0; 1548 }; 1549 1550 /* creq_add_gid_resp (size:128b/16B) */ 1551 struct creq_add_gid_resp { 1552 u8 type; 1553 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL 1554 #define CREQ_ADD_GID_RESP_TYPE_SFT 0 1555 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL 1556 #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT 1557 u8 status; 1558 __le16 cookie; 1559 __le32 xid; 1560 u8 v; 1561 #define CREQ_ADD_GID_RESP_V 0x1UL 1562 u8 event; 1563 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL 1564 #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID 1565 u8 reserved48[6]; 1566 }; 1567 1568 /* cmdq_delete_gid (size:192b/24B) */ 1569 struct cmdq_delete_gid { 1570 u8 opcode; 1571 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL 1572 #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID 1573 u8 cmd_size; 1574 __le16 flags; 1575 __le16 cookie; 1576 u8 resp_size; 1577 u8 reserved8; 1578 __le64 resp_addr; 1579 __le16 gid_index; 1580 u8 unused_0[6]; 1581 }; 1582 1583 /* creq_delete_gid_resp (size:128b/16B) */ 1584 struct creq_delete_gid_resp { 1585 u8 type; 1586 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL 1587 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 1588 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL 1589 #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 1590 u8 status; 1591 __le16 cookie; 1592 __le32 xid; 1593 u8 v; 1594 #define CREQ_DELETE_GID_RESP_V 0x1UL 1595 u8 event; 1596 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL 1597 #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 1598 u8 reserved48[6]; 1599 }; 1600 1601 /* cmdq_modify_gid (size:384b/48B) */ 1602 struct cmdq_modify_gid { 1603 u8 opcode; 1604 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL 1605 #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 1606 u8 cmd_size; 1607 __le16 flags; 1608 __le16 cookie; 1609 u8 resp_size; 1610 u8 reserved8; 1611 __le64 resp_addr; 1612 __be32 gid[4]; 1613 __be16 src_mac[3]; 1614 __le16 vlan; 1615 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL 1616 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 1617 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL 1618 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 1619 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1620 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12) 1621 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12) 1622 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12) 1623 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12) 1624 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1625 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1626 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1627 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 1628 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL 1629 __le16 ipid; 1630 __le16 gid_index; 1631 __le16 stats_ctx; 1632 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL 1633 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 1634 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL 1635 __le16 unused_0; 1636 }; 1637 1638 /* creq_modify_gid_resp (size:128b/16B) */ 1639 struct creq_modify_gid_resp { 1640 u8 type; 1641 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL 1642 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 1643 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL 1644 #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 1645 u8 status; 1646 __le16 cookie; 1647 __le32 xid; 1648 u8 v; 1649 #define CREQ_MODIFY_GID_RESP_V 0x1UL 1650 u8 event; 1651 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL 1652 #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 1653 u8 reserved48[6]; 1654 }; 1655 1656 /* cmdq_query_gid (size:192b/24B) */ 1657 struct cmdq_query_gid { 1658 u8 opcode; 1659 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL 1660 #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID 1661 u8 cmd_size; 1662 __le16 flags; 1663 __le16 cookie; 1664 u8 resp_size; 1665 u8 reserved8; 1666 __le64 resp_addr; 1667 __le16 gid_index; 1668 u8 unused16[6]; 1669 }; 1670 1671 /* creq_query_gid_resp (size:128b/16B) */ 1672 struct creq_query_gid_resp { 1673 u8 type; 1674 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL 1675 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 1676 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL 1677 #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 1678 u8 status; 1679 __le16 cookie; 1680 __le32 size; 1681 u8 v; 1682 #define CREQ_QUERY_GID_RESP_V 0x1UL 1683 u8 event; 1684 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL 1685 #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 1686 u8 reserved48[6]; 1687 }; 1688 1689 /* creq_query_gid_resp_sb (size:320b/40B) */ 1690 struct creq_query_gid_resp_sb { 1691 u8 opcode; 1692 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL 1693 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 1694 u8 status; 1695 __le16 cookie; 1696 __le16 flags; 1697 u8 resp_size; 1698 u8 reserved8; 1699 __le32 gid[4]; 1700 __le16 src_mac[3]; 1701 __le16 vlan; 1702 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL 1703 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 1704 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL 1705 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 1706 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL 1707 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 1708 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12) 1709 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12) 1710 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12) 1711 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12) 1712 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12) 1713 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12) 1714 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12) 1715 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12) 1716 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 1717 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL 1718 __le16 ipid; 1719 __le16 gid_index; 1720 __le32 unused_0; 1721 }; 1722 1723 /* cmdq_create_qp1 (size:640b/80B) */ 1724 struct cmdq_create_qp1 { 1725 u8 opcode; 1726 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL 1727 #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 1728 u8 cmd_size; 1729 __le16 flags; 1730 __le16 cookie; 1731 u8 resp_size; 1732 u8 reserved8; 1733 __le64 resp_addr; 1734 __le64 qp_handle; 1735 __le32 qp_flags; 1736 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL 1737 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL 1738 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL 1739 #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 1740 u8 type; 1741 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL 1742 #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI 1743 u8 sq_pg_size_sq_lvl; 1744 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL 1745 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 1746 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL 1747 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL 1748 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL 1749 #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 1750 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL 1751 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 1752 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4) 1753 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4) 1754 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4) 1755 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4) 1756 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4) 1757 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4) 1758 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G 1759 u8 rq_pg_size_rq_lvl; 1760 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL 1761 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 1762 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL 1763 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL 1764 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL 1765 #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 1766 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL 1767 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 1768 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4) 1769 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4) 1770 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4) 1771 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4) 1772 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4) 1773 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4) 1774 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G 1775 u8 unused_0; 1776 __le32 dpi; 1777 __le32 sq_size; 1778 __le32 rq_size; 1779 __le16 sq_fwo_sq_sge; 1780 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL 1781 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 1782 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL 1783 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 1784 __le16 rq_fwo_rq_sge; 1785 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL 1786 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 1787 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL 1788 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 1789 __le32 scq_cid; 1790 __le32 rcq_cid; 1791 __le32 srq_cid; 1792 __le32 pd_id; 1793 __le64 sq_pbl; 1794 __le64 rq_pbl; 1795 }; 1796 1797 /* creq_create_qp1_resp (size:128b/16B) */ 1798 struct creq_create_qp1_resp { 1799 u8 type; 1800 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL 1801 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 1802 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL 1803 #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 1804 u8 status; 1805 __le16 cookie; 1806 __le32 xid; 1807 u8 v; 1808 #define CREQ_CREATE_QP1_RESP_V 0x1UL 1809 u8 event; 1810 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL 1811 #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 1812 u8 reserved48[6]; 1813 }; 1814 1815 /* cmdq_destroy_qp1 (size:192b/24B) */ 1816 struct cmdq_destroy_qp1 { 1817 u8 opcode; 1818 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL 1819 #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 1820 u8 cmd_size; 1821 __le16 flags; 1822 __le16 cookie; 1823 u8 resp_size; 1824 u8 reserved8; 1825 __le64 resp_addr; 1826 __le32 qp1_cid; 1827 __le32 unused_0; 1828 }; 1829 1830 /* creq_destroy_qp1_resp (size:128b/16B) */ 1831 struct creq_destroy_qp1_resp { 1832 u8 type; 1833 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL 1834 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 1835 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL 1836 #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 1837 u8 status; 1838 __le16 cookie; 1839 __le32 xid; 1840 u8 v; 1841 #define CREQ_DESTROY_QP1_RESP_V 0x1UL 1842 u8 event; 1843 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL 1844 #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 1845 u8 reserved48[6]; 1846 }; 1847 1848 /* cmdq_create_ah (size:512b/64B) */ 1849 struct cmdq_create_ah { 1850 u8 opcode; 1851 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL 1852 #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH 1853 u8 cmd_size; 1854 __le16 flags; 1855 __le16 cookie; 1856 u8 resp_size; 1857 u8 reserved8; 1858 __le64 resp_addr; 1859 __le64 ah_handle; 1860 __le32 dgid[4]; 1861 u8 type; 1862 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL 1863 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL 1864 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL 1865 #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 1866 u8 hop_limit; 1867 __le16 sgid_index; 1868 __le32 dest_vlan_id_flow_label; 1869 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL 1870 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 1871 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL 1872 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 1873 __le32 pd_id; 1874 __le32 unused_0; 1875 __le16 dest_mac[3]; 1876 u8 traffic_class; 1877 u8 enable_cc; 1878 #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL 1879 }; 1880 1881 /* creq_create_ah_resp (size:128b/16B) */ 1882 struct creq_create_ah_resp { 1883 u8 type; 1884 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL 1885 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 1886 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL 1887 #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 1888 u8 status; 1889 __le16 cookie; 1890 __le32 xid; 1891 u8 v; 1892 #define CREQ_CREATE_AH_RESP_V 0x1UL 1893 u8 event; 1894 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL 1895 #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 1896 u8 reserved48[6]; 1897 }; 1898 1899 /* cmdq_destroy_ah (size:192b/24B) */ 1900 struct cmdq_destroy_ah { 1901 u8 opcode; 1902 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL 1903 #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 1904 u8 cmd_size; 1905 __le16 flags; 1906 __le16 cookie; 1907 u8 resp_size; 1908 u8 reserved8; 1909 __le64 resp_addr; 1910 __le32 ah_cid; 1911 __le32 unused_0; 1912 }; 1913 1914 /* creq_destroy_ah_resp (size:128b/16B) */ 1915 struct creq_destroy_ah_resp { 1916 u8 type; 1917 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL 1918 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 1919 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL 1920 #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 1921 u8 status; 1922 __le16 cookie; 1923 __le32 xid; 1924 u8 v; 1925 #define CREQ_DESTROY_AH_RESP_V 0x1UL 1926 u8 event; 1927 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL 1928 #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 1929 u8 reserved48[6]; 1930 }; 1931 1932 /* cmdq_query_roce_stats (size:192b/24B) */ 1933 struct cmdq_query_roce_stats { 1934 u8 opcode; 1935 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL 1936 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 1937 u8 cmd_size; 1938 __le16 flags; 1939 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL 1940 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL 1941 __le16 cookie; 1942 u8 resp_size; 1943 u8 collection_id; 1944 __le64 resp_addr; 1945 __le32 function_id; 1946 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL 1947 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 1948 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL 1949 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 1950 #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL 1951 __le32 reserved32; 1952 }; 1953 1954 /* creq_query_roce_stats_resp (size:128b/16B) */ 1955 struct creq_query_roce_stats_resp { 1956 u8 type; 1957 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL 1958 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 1959 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL 1960 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 1961 u8 status; 1962 __le16 cookie; 1963 __le32 size; 1964 u8 v; 1965 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL 1966 u8 event; 1967 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL 1968 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \ 1969 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 1970 u8 reserved48[6]; 1971 }; 1972 1973 /* creq_query_roce_stats_resp_sb (size:2944b/368B) */ 1974 struct creq_query_roce_stats_resp_sb { 1975 u8 opcode; 1976 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL 1977 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \ 1978 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 1979 u8 status; 1980 __le16 cookie; 1981 __le16 flags; 1982 u8 resp_size; 1983 u8 rsvd; 1984 __le32 num_counters; 1985 __le32 rsvd1; 1986 __le64 to_retransmits; 1987 __le64 seq_err_naks_rcvd; 1988 __le64 max_retry_exceeded; 1989 __le64 rnr_naks_rcvd; 1990 __le64 missing_resp; 1991 __le64 unrecoverable_err; 1992 __le64 bad_resp_err; 1993 __le64 local_qp_op_err; 1994 __le64 local_protection_err; 1995 __le64 mem_mgmt_op_err; 1996 __le64 remote_invalid_req_err; 1997 __le64 remote_access_err; 1998 __le64 remote_op_err; 1999 __le64 dup_req; 2000 __le64 res_exceed_max; 2001 __le64 res_length_mismatch; 2002 __le64 res_exceeds_wqe; 2003 __le64 res_opcode_err; 2004 __le64 res_rx_invalid_rkey; 2005 __le64 res_rx_domain_err; 2006 __le64 res_rx_no_perm; 2007 __le64 res_rx_range_err; 2008 __le64 res_tx_invalid_rkey; 2009 __le64 res_tx_domain_err; 2010 __le64 res_tx_no_perm; 2011 __le64 res_tx_range_err; 2012 __le64 res_irrq_oflow; 2013 __le64 res_unsup_opcode; 2014 __le64 res_unaligned_atomic; 2015 __le64 res_rem_inv_err; 2016 __le64 res_mem_error; 2017 __le64 res_srq_err; 2018 __le64 res_cmp_err; 2019 __le64 res_invalid_dup_rkey; 2020 __le64 res_wqe_format_err; 2021 __le64 res_cq_load_err; 2022 __le64 res_srq_load_err; 2023 __le64 res_tx_pci_err; 2024 __le64 res_rx_pci_err; 2025 __le64 res_oos_drop_count; 2026 __le64 active_qp_count_p0; 2027 __le64 active_qp_count_p1; 2028 __le64 active_qp_count_p2; 2029 __le64 active_qp_count_p3; 2030 }; 2031 2032 /* cmdq_query_roce_stats_ext (size:192b/24B) */ 2033 struct cmdq_query_roce_stats_ext { 2034 u8 opcode; 2035 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL 2036 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \ 2037 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 2038 u8 cmd_size; 2039 __le16 flags; 2040 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL 2041 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL 2042 __le16 cookie; 2043 u8 resp_size; 2044 u8 collection_id; 2045 __le64 resp_addr; 2046 __le32 function_id; 2047 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL 2048 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 2049 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL 2050 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 2051 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL 2052 __le32 reserved32; 2053 }; 2054 2055 /* creq_query_roce_stats_ext_resp (size:128b/16B) */ 2056 struct creq_query_roce_stats_ext_resp { 2057 u8 type; 2058 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL 2059 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 2060 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL 2061 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \ 2062 CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 2063 u8 status; 2064 __le16 cookie; 2065 __le32 size; 2066 u8 v; 2067 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL 2068 u8 event; 2069 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL 2070 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \ 2071 CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 2072 u8 reserved48[6]; 2073 }; 2074 2075 /* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */ 2076 struct creq_query_roce_stats_ext_resp_sb { 2077 u8 opcode; 2078 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL 2079 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \ 2080 CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 2081 u8 status; 2082 __le16 cookie; 2083 __le16 flags; 2084 u8 resp_size; 2085 u8 rsvd; 2086 __le64 tx_atomic_req_pkts; 2087 __le64 tx_read_req_pkts; 2088 __le64 tx_read_res_pkts; 2089 __le64 tx_write_req_pkts; 2090 __le64 tx_send_req_pkts; 2091 __le64 tx_roce_pkts; 2092 __le64 tx_roce_bytes; 2093 __le64 rx_atomic_req_pkts; 2094 __le64 rx_read_req_pkts; 2095 __le64 rx_read_res_pkts; 2096 __le64 rx_write_req_pkts; 2097 __le64 rx_send_req_pkts; 2098 __le64 rx_roce_pkts; 2099 __le64 rx_roce_bytes; 2100 __le64 rx_roce_good_pkts; 2101 __le64 rx_roce_good_bytes; 2102 __le64 rx_out_of_buffer_pkts; 2103 __le64 rx_out_of_sequence_pkts; 2104 __le64 tx_cnp_pkts; 2105 __le64 rx_cnp_pkts; 2106 __le64 rx_ecn_marked_pkts; 2107 __le64 tx_cnp_bytes; 2108 __le64 rx_cnp_bytes; 2109 __le64 seq_err_naks_rcvd; 2110 __le64 rnr_naks_rcvd; 2111 __le64 missing_resp; 2112 __le64 to_retransmit; 2113 __le64 dup_req; 2114 }; 2115 2116 /* cmdq_roce_mirror_cfg (size:192b/24B) */ 2117 struct cmdq_roce_mirror_cfg { 2118 u8 opcode; 2119 #define CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG 0x99UL 2120 #define CMDQ_ROCE_MIRROR_CFG_OPCODE_LAST \ 2121 CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG 2122 u8 cmd_size; 2123 __le16 flags; 2124 __le16 cookie; 2125 u8 resp_size; 2126 u8 reserved8; 2127 __le64 resp_addr; 2128 u8 mirror_flags; 2129 #define CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE 0x1UL 2130 u8 rsvd[7]; 2131 }; 2132 2133 /* creq_roce_mirror_cfg_resp (size:128b/16B) */ 2134 struct creq_roce_mirror_cfg_resp { 2135 u8 type; 2136 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_MASK 0x3fUL 2137 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_SFT 0 2138 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT 0x38UL 2139 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_LAST \ 2140 CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT 2141 u8 status; 2142 __le16 cookie; 2143 __le32 reserved32; 2144 u8 v; 2145 #define CREQ_ROCE_MIRROR_CFG_RESP_V 0x1UL 2146 u8 event; 2147 #define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG 0x99UL 2148 #define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_LAST \ 2149 CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG 2150 u8 reserved48[6]; 2151 }; 2152 2153 /* cmdq_query_func (size:128b/16B) */ 2154 struct cmdq_query_func { 2155 u8 opcode; 2156 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL 2157 #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 2158 u8 cmd_size; 2159 __le16 flags; 2160 __le16 cookie; 2161 u8 resp_size; 2162 u8 reserved8; 2163 __le64 resp_addr; 2164 }; 2165 2166 /* creq_query_func_resp (size:128b/16B) */ 2167 struct creq_query_func_resp { 2168 u8 type; 2169 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL 2170 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 2171 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL 2172 #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 2173 u8 status; 2174 __le16 cookie; 2175 __le32 size; 2176 u8 v; 2177 #define CREQ_QUERY_FUNC_RESP_V 0x1UL 2178 u8 event; 2179 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL 2180 #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 2181 u8 reserved48[6]; 2182 }; 2183 2184 /* creq_query_func_resp_sb (size:1280b/160B) */ 2185 struct creq_query_func_resp_sb { 2186 u8 opcode; 2187 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL 2188 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 2189 u8 status; 2190 __le16 cookie; 2191 __le16 flags; 2192 u8 resp_size; 2193 u8 reserved8; 2194 __le64 max_mr_size; 2195 __le32 max_qp; 2196 __le16 max_qp_wr; 2197 __le16 dev_cap_flags; 2198 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL 2199 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL 2200 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 2201 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1) 2202 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1) 2203 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1) 2204 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \ 2205 CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT 2206 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL 2207 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL 2208 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL 2209 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL 2210 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL 2211 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL 2212 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL 2213 __le32 max_cq; 2214 __le32 max_cqe; 2215 __le32 max_pd; 2216 u8 max_sge; 2217 u8 max_srq_sge; 2218 u8 max_qp_rd_atom; 2219 u8 max_qp_init_rd_atom; 2220 __le32 max_mr; 2221 __le32 max_mw; 2222 __le32 max_raw_eth_qp; 2223 __le32 max_ah; 2224 __le32 max_fmr; 2225 __le32 max_srq_wr; 2226 __le32 max_pkeys; 2227 __le32 max_inline_data; 2228 u8 max_map_per_fmr; 2229 u8 l2_db_space_size; 2230 __le16 max_srq; 2231 __le32 max_gid; 2232 __le32 tqm_alloc_reqs[12]; 2233 __le32 max_dpi; 2234 u8 max_sge_var_wqe; 2235 u8 dev_cap_ext_flags; 2236 #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL 2237 #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL 2238 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL 2239 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL 2240 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL 2241 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL 2242 #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL 2243 #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL 2244 __le16 max_inline_data_var_wqe; 2245 __le32 start_qid; 2246 u8 max_msn_table_size; 2247 u8 reserved8_1; 2248 __le16 dev_cap_ext_flags_2; 2249 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL 2250 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL 2251 #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL 2252 #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL 2253 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL 2254 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4 2255 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4) 2256 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4) 2257 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4) 2258 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \ 2259 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE 2260 #define CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED 0x40UL 2261 #define CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED 0x400UL 2262 #define CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED 0x1000UL 2263 __le16 max_xp_qp_size; 2264 __le16 create_qp_batch_size; 2265 __le16 destroy_qp_batch_size; 2266 __le16 max_srq_ext; 2267 __le16 reserved16; 2268 __le16 rate_limit_min; 2269 __le32 rate_limit_max; 2270 }; 2271 2272 /* cmdq_set_func_resources (size:448b/56B) */ 2273 struct cmdq_set_func_resources { 2274 u8 opcode; 2275 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL 2276 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\ 2277 CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 2278 u8 cmd_size; 2279 __le16 flags; 2280 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL 2281 __le16 cookie; 2282 u8 resp_size; 2283 u8 reserved8; 2284 __le64 resp_addr; 2285 __le32 number_of_qp; 2286 __le32 number_of_mrw; 2287 __le32 number_of_srq; 2288 __le32 number_of_cq; 2289 __le32 max_qp_per_vf; 2290 __le32 max_mrw_per_vf; 2291 __le32 max_srq_per_vf; 2292 __le32 max_cq_per_vf; 2293 __le32 max_gid_per_vf; 2294 __le32 stat_ctx_id; 2295 }; 2296 2297 /* creq_set_func_resources_resp (size:128b/16B) */ 2298 struct creq_set_func_resources_resp { 2299 u8 type; 2300 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL 2301 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 2302 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL 2303 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 2304 u8 status; 2305 __le16 cookie; 2306 __le32 reserved32; 2307 u8 v; 2308 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL 2309 u8 event; 2310 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL 2311 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \ 2312 CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 2313 u8 reserved48[6]; 2314 }; 2315 2316 /* cmdq_read_context (size:192b/24B) */ 2317 struct cmdq_read_context { 2318 u8 opcode; 2319 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL 2320 #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 2321 u8 cmd_size; 2322 __le16 flags; 2323 __le16 cookie; 2324 u8 resp_size; 2325 u8 reserved8; 2326 __le64 resp_addr; 2327 __le32 xid; 2328 u8 type; 2329 #define CMDQ_READ_CONTEXT_TYPE_QPC 0x0UL 2330 #define CMDQ_READ_CONTEXT_TYPE_CQ 0x1UL 2331 #define CMDQ_READ_CONTEXT_TYPE_MRW 0x2UL 2332 #define CMDQ_READ_CONTEXT_TYPE_SRQ 0x3UL 2333 #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ 2334 u8 unused_0[3]; 2335 }; 2336 2337 /* creq_read_context (size:128b/16B) */ 2338 struct creq_read_context { 2339 u8 type; 2340 #define CREQ_READ_CONTEXT_TYPE_MASK 0x3fUL 2341 #define CREQ_READ_CONTEXT_TYPE_SFT 0 2342 #define CREQ_READ_CONTEXT_TYPE_QP_EVENT 0x38UL 2343 #define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT 2344 u8 status; 2345 __le16 cookie; 2346 __le32 reserved32; 2347 u8 v; 2348 #define CREQ_READ_CONTEXT_V 0x1UL 2349 u8 event; 2350 #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 0x85UL 2351 #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 2352 __le16 reserved16; 2353 __le32 reserved_32; 2354 }; 2355 2356 /* cmdq_map_tc_to_cos (size:192b/24B) */ 2357 struct cmdq_map_tc_to_cos { 2358 u8 opcode; 2359 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL 2360 #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 2361 u8 cmd_size; 2362 __le16 flags; 2363 __le16 cookie; 2364 u8 resp_size; 2365 u8 reserved8; 2366 __le64 resp_addr; 2367 __le16 cos0; 2368 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL 2369 #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 2370 __le16 cos1; 2371 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL 2372 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL 2373 #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 2374 __le32 unused_0; 2375 }; 2376 2377 /* creq_map_tc_to_cos_resp (size:128b/16B) */ 2378 struct creq_map_tc_to_cos_resp { 2379 u8 type; 2380 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL 2381 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 2382 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL 2383 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 2384 u8 status; 2385 __le16 cookie; 2386 __le32 reserved32; 2387 u8 v; 2388 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL 2389 u8 event; 2390 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL 2391 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 2392 u8 reserved48[6]; 2393 }; 2394 2395 /* cmdq_query_roce_cc (size:128b/16B) */ 2396 struct cmdq_query_roce_cc { 2397 u8 opcode; 2398 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL 2399 #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 2400 u8 cmd_size; 2401 __le16 flags; 2402 __le16 cookie; 2403 u8 resp_size; 2404 u8 reserved8; 2405 __le64 resp_addr; 2406 }; 2407 2408 /* creq_query_roce_cc_resp (size:128b/16B) */ 2409 struct creq_query_roce_cc_resp { 2410 u8 type; 2411 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2412 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 2413 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2414 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 2415 u8 status; 2416 __le16 cookie; 2417 __le32 size; 2418 u8 v; 2419 #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL 2420 u8 event; 2421 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL 2422 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 2423 u8 reserved48[6]; 2424 }; 2425 2426 /* creq_query_roce_cc_resp_sb (size:256b/32B) */ 2427 struct creq_query_roce_cc_resp_sb { 2428 u8 opcode; 2429 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL 2430 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \ 2431 CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 2432 u8 status; 2433 __le16 cookie; 2434 __le16 flags; 2435 u8 resp_size; 2436 u8 reserved8; 2437 u8 enable_cc; 2438 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL 2439 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL 2440 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 2441 u8 tos_dscp_tos_ecn; 2442 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL 2443 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 2444 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL 2445 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 2446 u8 g; 2447 u8 num_phases_per_state; 2448 __le16 init_cr; 2449 __le16 init_tr; 2450 u8 alt_vlan_pcp; 2451 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL 2452 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 2453 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL 2454 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 2455 u8 alt_tos_dscp; 2456 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL 2457 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 2458 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL 2459 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 2460 u8 cc_mode; 2461 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL 2462 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL 2463 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \ 2464 CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 2465 u8 tx_queue; 2466 __le16 rtt; 2467 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL 2468 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 2469 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL 2470 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 2471 __le16 tcp_cp; 2472 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL 2473 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 2474 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL 2475 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 2476 __le16 inactivity_th; 2477 u8 pkts_per_phase; 2478 u8 time_per_phase; 2479 __le32 reserved32; 2480 }; 2481 2482 /* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ 2483 struct creq_query_roce_cc_resp_sb_tlv { 2484 __le16 cmd_discr; 2485 u8 reserved_8b; 2486 u8 tlv_flags; 2487 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2488 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2489 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2490 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2491 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2492 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2493 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2494 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2495 __le16 tlv_type; 2496 __le16 length; 2497 u8 total_size; 2498 u8 reserved56[7]; 2499 u8 opcode; 2500 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL 2501 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \ 2502 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 2503 u8 status; 2504 __le16 cookie; 2505 __le16 flags; 2506 u8 resp_size; 2507 u8 reserved8; 2508 u8 enable_cc; 2509 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL 2510 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL 2511 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 2512 u8 tos_dscp_tos_ecn; 2513 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL 2514 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 2515 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL 2516 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 2517 u8 g; 2518 u8 num_phases_per_state; 2519 __le16 init_cr; 2520 __le16 init_tr; 2521 u8 alt_vlan_pcp; 2522 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL 2523 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 2524 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL 2525 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 2526 u8 alt_tos_dscp; 2527 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2528 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 2529 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL 2530 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 2531 u8 cc_mode; 2532 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL 2533 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL 2534 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\ 2535 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 2536 u8 tx_queue; 2537 __le16 rtt; 2538 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL 2539 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 2540 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL 2541 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 2542 __le16 tcp_cp; 2543 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL 2544 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 2545 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL 2546 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 2547 __le16 inactivity_th; 2548 u8 pkts_per_phase; 2549 u8 time_per_phase; 2550 __le32 reserved32; 2551 }; 2552 2553 /* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ 2554 struct creq_query_roce_cc_gen1_resp_sb_tlv { 2555 __le16 cmd_discr; 2556 u8 reserved_8b; 2557 u8 tlv_flags; 2558 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL 2559 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2560 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2561 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL 2562 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2563 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2564 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \ 2565 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES 2566 __le16 tlv_type; 2567 __le16 length; 2568 __le64 reserved64; 2569 __le16 inactivity_th_hi; 2570 __le16 min_time_between_cnps; 2571 __le16 init_cp; 2572 u8 tr_update_mode; 2573 u8 tr_update_cycles; 2574 u8 fr_num_rtts; 2575 u8 ai_rate_increase; 2576 __le16 reduction_relax_rtts_th; 2577 __le16 additional_relax_cr_th; 2578 __le16 cr_min_th; 2579 u8 bw_avg_weight; 2580 u8 actual_cr_factor; 2581 __le16 max_cp_cr_th; 2582 u8 cp_bias_en; 2583 u8 cp_bias; 2584 u8 cnp_ecn; 2585 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL 2586 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL 2587 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL 2588 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \ 2589 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 2590 u8 rtt_jitter_en; 2591 __le16 link_bytes_per_usec; 2592 __le16 reset_cc_cr_th; 2593 u8 cr_width; 2594 u8 quota_period_min; 2595 u8 quota_period_max; 2596 u8 quota_period_abs_max; 2597 __le16 tr_lower_bound; 2598 u8 cr_prob_factor; 2599 u8 tr_prob_factor; 2600 __le16 fairness_cr_th; 2601 u8 red_div; 2602 u8 cnp_ratio_th; 2603 __le16 exp_ai_rtts; 2604 u8 exp_ai_cr_cp_ratio; 2605 u8 use_rate_table; 2606 __le16 cp_exp_update_th; 2607 __le16 high_exp_ai_rtts_th1; 2608 __le16 high_exp_ai_rtts_th2; 2609 __le16 actual_cr_cong_free_rtts_th; 2610 __le16 severe_cong_cr_th1; 2611 __le16 severe_cong_cr_th2; 2612 __le32 link64B_per_rtt; 2613 u8 cc_ack_bytes; 2614 u8 reduce_init_en; 2615 __le16 reduce_init_cong_free_rtts_th; 2616 u8 random_no_red_en; 2617 u8 actual_cr_shift_correction_en; 2618 u8 quota_period_adjust_en; 2619 u8 reserved[5]; 2620 }; 2621 2622 /* cmdq_modify_roce_cc (size:448b/56B) */ 2623 struct cmdq_modify_roce_cc { 2624 u8 opcode; 2625 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL 2626 #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 2627 u8 cmd_size; 2628 __le16 flags; 2629 __le16 cookie; 2630 u8 resp_size; 2631 u8 reserved8; 2632 __le64 resp_addr; 2633 __le32 modify_mask; 2634 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL 2635 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL 2636 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2637 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL 2638 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL 2639 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL 2640 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL 2641 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2642 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2643 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL 2644 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL 2645 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL 2646 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL 2647 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2648 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2649 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2650 u8 enable_cc; 2651 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL 2652 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL 2653 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 2654 u8 g; 2655 u8 num_phases_per_state; 2656 u8 pkts_per_phase; 2657 __le16 init_cr; 2658 __le16 init_tr; 2659 u8 tos_dscp_tos_ecn; 2660 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL 2661 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 2662 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL 2663 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 2664 u8 alt_vlan_pcp; 2665 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL 2666 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 2667 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL 2668 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 2669 __le16 alt_tos_dscp; 2670 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL 2671 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 2672 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL 2673 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 2674 __le16 rtt; 2675 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL 2676 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 2677 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL 2678 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 2679 __le16 tcp_cp; 2680 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL 2681 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 2682 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL 2683 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 2684 u8 cc_mode; 2685 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL 2686 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2687 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 2688 u8 tx_queue; 2689 __le16 inactivity_th; 2690 u8 time_per_phase; 2691 u8 reserved8_1; 2692 __le16 reserved16; 2693 __le32 reserved32; 2694 __le64 reserved64; 2695 }; 2696 2697 /* cmdq_modify_roce_cc_tlv (size:640b/80B) */ 2698 struct cmdq_modify_roce_cc_tlv { 2699 __le16 cmd_discr; 2700 u8 reserved_8b; 2701 u8 tlv_flags; 2702 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL 2703 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2704 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2705 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL 2706 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2707 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2708 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \ 2709 CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES 2710 __le16 tlv_type; 2711 __le16 length; 2712 u8 total_size; 2713 u8 reserved56[7]; 2714 u8 opcode; 2715 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL 2716 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 2717 u8 cmd_size; 2718 __le16 flags; 2719 __le16 cookie; 2720 u8 resp_size; 2721 u8 reserved8; 2722 __le64 resp_addr; 2723 __le32 modify_mask; 2724 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL 2725 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL 2726 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL 2727 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL 2728 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL 2729 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL 2730 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL 2731 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL 2732 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL 2733 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL 2734 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL 2735 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL 2736 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL 2737 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL 2738 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL 2739 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL 2740 u8 enable_cc; 2741 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL 2742 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL 2743 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 2744 u8 g; 2745 u8 num_phases_per_state; 2746 u8 pkts_per_phase; 2747 __le16 init_cr; 2748 __le16 init_tr; 2749 u8 tos_dscp_tos_ecn; 2750 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL 2751 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 2752 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL 2753 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 2754 u8 alt_vlan_pcp; 2755 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL 2756 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 2757 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL 2758 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 2759 __le16 alt_tos_dscp; 2760 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL 2761 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 2762 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL 2763 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 2764 __le16 rtt; 2765 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL 2766 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 2767 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL 2768 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 2769 __le16 tcp_cp; 2770 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL 2771 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 2772 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL 2773 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 2774 u8 cc_mode; 2775 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL 2776 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL 2777 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\ 2778 CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 2779 u8 tx_queue; 2780 __le16 inactivity_th; 2781 u8 time_per_phase; 2782 u8 reserved8_1; 2783 __le16 reserved16; 2784 __le32 reserved32; 2785 __le64 reserved64; 2786 __le64 reservedtlvpad; 2787 }; 2788 2789 /* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ 2790 struct cmdq_modify_roce_cc_gen1_tlv { 2791 __le16 cmd_discr; 2792 u8 reserved_8b; 2793 u8 tlv_flags; 2794 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL 2795 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL 2796 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL 2797 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL 2798 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 2799 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 2800 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\ 2801 CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES 2802 __le16 tlv_type; 2803 __le16 length; 2804 __le64 reserved64; 2805 __le64 modify_mask; 2806 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL 2807 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL 2808 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL 2809 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL 2810 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL 2811 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL 2812 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL 2813 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL 2814 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL 2815 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL 2816 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL 2817 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL 2818 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL 2819 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL 2820 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL 2821 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL 2822 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL 2823 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL 2824 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL 2825 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL 2826 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL 2827 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL 2828 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL 2829 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL 2830 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL 2831 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL 2832 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL 2833 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL 2834 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL 2835 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL 2836 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL 2837 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL 2838 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL 2839 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL 2840 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL 2841 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL 2842 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL 2843 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL 2844 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL 2845 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL 2846 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \ 2847 0x10000000000ULL 2848 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL 2849 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \ 2850 0x40000000000ULL 2851 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL 2852 __le16 inactivity_th_hi; 2853 __le16 min_time_between_cnps; 2854 __le16 init_cp; 2855 u8 tr_update_mode; 2856 u8 tr_update_cycles; 2857 u8 fr_num_rtts; 2858 u8 ai_rate_increase; 2859 __le16 reduction_relax_rtts_th; 2860 __le16 additional_relax_cr_th; 2861 __le16 cr_min_th; 2862 u8 bw_avg_weight; 2863 u8 actual_cr_factor; 2864 __le16 max_cp_cr_th; 2865 u8 cp_bias_en; 2866 u8 cp_bias; 2867 u8 cnp_ecn; 2868 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL 2869 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL 2870 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL 2871 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 2872 u8 rtt_jitter_en; 2873 __le16 link_bytes_per_usec; 2874 __le16 reset_cc_cr_th; 2875 u8 cr_width; 2876 u8 quota_period_min; 2877 u8 quota_period_max; 2878 u8 quota_period_abs_max; 2879 __le16 tr_lower_bound; 2880 u8 cr_prob_factor; 2881 u8 tr_prob_factor; 2882 __le16 fairness_cr_th; 2883 u8 red_div; 2884 u8 cnp_ratio_th; 2885 __le16 exp_ai_rtts; 2886 u8 exp_ai_cr_cp_ratio; 2887 u8 use_rate_table; 2888 __le16 cp_exp_update_th; 2889 __le16 high_exp_ai_rtts_th1; 2890 __le16 high_exp_ai_rtts_th2; 2891 __le16 actual_cr_cong_free_rtts_th; 2892 __le16 severe_cong_cr_th1; 2893 __le16 severe_cong_cr_th2; 2894 __le32 link64B_per_rtt; 2895 u8 cc_ack_bytes; 2896 u8 reduce_init_en; 2897 __le16 reduce_init_cong_free_rtts_th; 2898 u8 random_no_red_en; 2899 u8 actual_cr_shift_correction_en; 2900 u8 quota_period_adjust_en; 2901 u8 reserved[5]; 2902 }; 2903 2904 /* creq_modify_roce_cc_resp (size:128b/16B) */ 2905 struct creq_modify_roce_cc_resp { 2906 u8 type; 2907 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL 2908 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 2909 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL 2910 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 2911 u8 status; 2912 __le16 cookie; 2913 __le32 reserved32; 2914 u8 v; 2915 #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL 2916 u8 event; 2917 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL 2918 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 2919 u8 reserved48[6]; 2920 }; 2921 2922 /* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ 2923 struct cmdq_set_link_aggr_mode_cc { 2924 u8 opcode; 2925 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL 2926 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \ 2927 CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 2928 u8 cmd_size; 2929 __le16 flags; 2930 __le16 cookie; 2931 u8 resp_size; 2932 u8 reserved8; 2933 __le64 resp_addr; 2934 __le32 modify_mask; 2935 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL 2936 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL 2937 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL 2938 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL 2939 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL 2940 u8 aggr_enable; 2941 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL 2942 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL 2943 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 2944 u8 active_port_map; 2945 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL 2946 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 2947 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL 2948 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 2949 u8 member_port_map; 2950 u8 link_aggr_mode; 2951 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL 2952 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL 2953 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL 2954 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL 2955 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 2956 __le16 stat_ctx_id[4]; 2957 __le64 rsvd1; 2958 }; 2959 2960 /* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ 2961 struct creq_set_link_aggr_mode_resources_resp { 2962 u8 type; 2963 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL 2964 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 2965 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL 2966 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 2967 u8 status; 2968 __le16 cookie; 2969 __le32 reserved32; 2970 u8 v; 2971 #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL 2972 u8 event; 2973 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL 2974 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\ 2975 CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 2976 u8 reserved48[6]; 2977 }; 2978 2979 /* creq_func_event (size:128b/16B) */ 2980 struct creq_func_event { 2981 u8 type; 2982 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL 2983 #define CREQ_FUNC_EVENT_TYPE_SFT 0 2984 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL 2985 #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 2986 u8 reserved56[7]; 2987 u8 v; 2988 #define CREQ_FUNC_EVENT_V 0x1UL 2989 u8 event; 2990 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL 2991 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL 2992 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL 2993 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL 2994 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL 2995 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL 2996 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL 2997 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL 2998 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL 2999 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL 3000 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL 3001 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL 3002 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL 3003 #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 3004 u8 reserved48[6]; 3005 }; 3006 3007 /* creq_qp_event (size:128b/16B) */ 3008 struct creq_qp_event { 3009 u8 type; 3010 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL 3011 #define CREQ_QP_EVENT_TYPE_SFT 0 3012 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL 3013 #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT 3014 u8 status; 3015 #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL 3016 #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL 3017 #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL 3018 #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL 3019 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL 3020 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL 3021 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL 3022 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL 3023 #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 3024 __le16 cookie; 3025 __le32 reserved32; 3026 u8 v; 3027 #define CREQ_QP_EVENT_V 0x1UL 3028 u8 event; 3029 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL 3030 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL 3031 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL 3032 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL 3033 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL 3034 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL 3035 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL 3036 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL 3037 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL 3038 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL 3039 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL 3040 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL 3041 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL 3042 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL 3043 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL 3044 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL 3045 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL 3046 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL 3047 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL 3048 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL 3049 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL 3050 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL 3051 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL 3052 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL 3053 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL 3054 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL 3055 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL 3056 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL 3057 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL 3058 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL 3059 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL 3060 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL 3061 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL 3062 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL 3063 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL 3064 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3065 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 3066 #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 3067 u8 reserved48[6]; 3068 }; 3069 3070 /* creq_qp_error_notification (size:128b/16B) */ 3071 struct creq_qp_error_notification { 3072 u8 type; 3073 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 3074 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 3075 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL 3076 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 3077 u8 status; 3078 u8 req_slow_path_state; 3079 u8 req_err_state_reason; 3080 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0X0UL 3081 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0X1UL 3082 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0X2UL 3083 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0X3UL 3084 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0X4UL 3085 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0X5UL 3086 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0X6UL 3087 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0X7UL 3088 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0X8UL 3089 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0X9UL 3090 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0XAUL 3091 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0XBUL 3092 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0XCUL 3093 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0XDUL 3094 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0XEUL 3095 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0XFUL 3096 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0X10UL 3097 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0X11UL 3098 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0X12UL 3099 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0X13UL 3100 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0X14UL 3101 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0X15UL 3102 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0X16UL 3103 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0X17UL 3104 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0X18UL 3105 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0X19UL 3106 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0X1AUL 3107 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0X1BUL 3108 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0X1CUL 3109 __le32 xid; 3110 u8 v; 3111 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL 3112 u8 event; 3113 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL 3114 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \ 3115 CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 3116 u8 res_slow_path_state; 3117 u8 res_err_state_reason; 3118 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL 3119 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL 3120 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL 3121 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL 3122 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL 3123 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL 3124 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL 3125 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL 3126 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL 3127 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL 3128 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL 3129 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL 3130 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL 3131 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL 3132 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL 3133 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL 3134 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL 3135 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL 3136 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL 3137 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL 3138 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL 3139 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL 3140 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL 3141 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL 3142 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL 3143 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL 3144 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL 3145 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL 3146 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL 3147 __le16 sq_cons_idx; 3148 __le16 rq_cons_idx; 3149 }; 3150 3151 /* creq_cq_error_notification (size:128b/16B) */ 3152 struct creq_cq_error_notification { 3153 u8 type; 3154 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL 3155 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 3156 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL 3157 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 3158 u8 status; 3159 u8 cq_err_reason; 3160 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL 3161 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL 3162 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL 3163 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL 3164 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL 3165 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL 3166 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \ 3167 CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 3168 u8 reserved8; 3169 __le32 xid; 3170 u8 v; 3171 #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL 3172 u8 event; 3173 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL 3174 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \ 3175 CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 3176 u8 reserved48[6]; 3177 }; 3178 3179 /* sq_base (size:64b/8B) */ 3180 struct sq_base { 3181 u8 wqe_type; 3182 #define SQ_BASE_WQE_TYPE_SEND 0x0UL 3183 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3184 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL 3185 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL 3186 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3187 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL 3188 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL 3189 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL 3190 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL 3191 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL 3192 #define SQ_BASE_WQE_TYPE_BIND 0xeUL 3193 #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL 3194 #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR 3195 u8 unused_0[7]; 3196 }; 3197 3198 /* sq_sge (size:128b/16B) */ 3199 struct sq_sge { 3200 __le64 va_or_pa; 3201 __le32 l_key; 3202 __le32 size; 3203 }; 3204 3205 /* sq_psn_search (size:64b/8B) */ 3206 struct sq_psn_search { 3207 __le32 opcode_start_psn; 3208 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL 3209 #define SQ_PSN_SEARCH_START_PSN_SFT 0 3210 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL 3211 #define SQ_PSN_SEARCH_OPCODE_SFT 24 3212 __le32 flags_next_psn; 3213 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL 3214 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 3215 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL 3216 #define SQ_PSN_SEARCH_FLAGS_SFT 24 3217 }; 3218 3219 /* sq_psn_search_ext (size:128b/16B) */ 3220 struct sq_psn_search_ext { 3221 __le32 opcode_start_psn; 3222 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL 3223 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 3224 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL 3225 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 3226 __le32 flags_next_psn; 3227 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL 3228 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 3229 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL 3230 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 3231 __le16 start_slot_idx; 3232 __le16 reserved16; 3233 __le32 reserved32; 3234 }; 3235 3236 /* sq_msn_search (size:64b/8B) */ 3237 struct sq_msn_search { 3238 __le64 start_idx_next_psn_start_psn; 3239 #define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL 3240 #define SQ_MSN_SEARCH_START_PSN_SFT 0 3241 #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL 3242 #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24 3243 #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL 3244 #define SQ_MSN_SEARCH_START_IDX_SFT 48 3245 }; 3246 3247 /* sq_send (size:1024b/128B) */ 3248 struct sq_send { 3249 u8 wqe_type; 3250 #define SQ_SEND_WQE_TYPE_SEND 0x0UL 3251 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3252 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL 3253 #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID 3254 u8 flags; 3255 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3256 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3257 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL 3258 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3259 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL 3260 #define SQ_SEND_FLAGS_SE 0x8UL 3261 #define SQ_SEND_FLAGS_INLINE 0x10UL 3262 #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL 3263 #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL 3264 u8 wqe_size; 3265 u8 reserved8_1; 3266 __le32 inv_key_or_imm_data; 3267 __le32 length; 3268 __le32 q_key; 3269 __le32 dst_qp; 3270 #define SQ_SEND_DST_QP_MASK 0xffffffUL 3271 #define SQ_SEND_DST_QP_SFT 0 3272 __le32 avid; 3273 #define SQ_SEND_AVID_MASK 0xfffffUL 3274 #define SQ_SEND_AVID_SFT 0 3275 __le32 reserved32; 3276 __le32 timestamp; 3277 #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL 3278 #define SQ_SEND_TIMESTAMP_SFT 0 3279 __le32 data[24]; 3280 }; 3281 3282 /* sq_send_hdr (size:256b/32B) */ 3283 struct sq_send_hdr { 3284 u8 wqe_type; 3285 #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL 3286 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL 3287 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL 3288 #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 3289 u8 flags; 3290 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3291 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3292 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3293 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3294 #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL 3295 #define SQ_SEND_HDR_FLAGS_SE 0x8UL 3296 #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL 3297 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL 3298 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3299 u8 wqe_size; 3300 u8 reserved8_1; 3301 __le32 inv_key_or_imm_data; 3302 __le32 length; 3303 __le32 q_key; 3304 __le32 dst_qp; 3305 #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL 3306 #define SQ_SEND_HDR_DST_QP_SFT 0 3307 __le32 avid; 3308 #define SQ_SEND_HDR_AVID_MASK 0xfffffUL 3309 #define SQ_SEND_HDR_AVID_SFT 0 3310 __le32 reserved32; 3311 __le32 timestamp; 3312 #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL 3313 #define SQ_SEND_HDR_TIMESTAMP_SFT 0 3314 }; 3315 3316 /* sq_send_raweth_qp1 (size:1024b/128B) */ 3317 struct sq_send_raweth_qp1 { 3318 u8 wqe_type; 3319 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL 3320 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 3321 u8 flags; 3322 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \ 3323 0xffUL 3324 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \ 3325 0 3326 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL 3327 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3328 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL 3329 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL 3330 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL 3331 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL 3332 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL 3333 u8 wqe_size; 3334 u8 reserved8; 3335 __le16 lflags; 3336 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3337 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL 3338 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL 3339 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL 3340 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL 3341 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL 3342 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL 3343 __le16 cfa_action; 3344 __le32 length; 3345 __le32 reserved32_1; 3346 __le32 cfa_meta; 3347 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL 3348 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 3349 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL 3350 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL 3351 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 3352 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL 3353 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 3354 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3355 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3356 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3357 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3358 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3359 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3360 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\ 3361 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG 3362 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3363 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 3364 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL 3365 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 3366 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28) 3367 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3368 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG 3369 __le32 reserved32_2; 3370 __le32 reserved32_3; 3371 __le32 timestamp; 3372 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL 3373 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 3374 __le32 data[24]; 3375 }; 3376 3377 /* sq_send_raweth_qp1_hdr (size:256b/32B) */ 3378 struct sq_send_raweth_qp1_hdr { 3379 u8 wqe_type; 3380 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL 3381 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 3382 u8 flags; 3383 #define \ 3384 SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3385 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3386 0 3387 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL 3388 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3389 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL 3390 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL 3391 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL 3392 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL 3393 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL 3394 u8 wqe_size; 3395 u8 reserved8; 3396 __le16 lflags; 3397 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL 3398 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL 3399 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL 3400 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL 3401 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL 3402 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL 3403 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL 3404 __le16 cfa_action; 3405 __le32 length; 3406 __le32 reserved32_1; 3407 __le32 cfa_meta; 3408 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL 3409 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 3410 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL 3411 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL 3412 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 3413 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL 3414 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 3415 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16) 3416 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16) 3417 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16) 3418 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16) 3419 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16) 3420 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16) 3421 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\ 3422 SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG 3423 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL 3424 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 3425 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL 3426 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 3427 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28) 3428 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28) 3429 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\ 3430 SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG 3431 __le32 reserved32_2; 3432 __le32 reserved32_3; 3433 __le32 timestamp; 3434 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL 3435 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 3436 }; 3437 3438 /* sq_rdma (size:1024b/128B) */ 3439 struct sq_rdma { 3440 u8 wqe_type; 3441 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL 3442 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3443 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL 3444 #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE 3445 u8 flags; 3446 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3447 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3448 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL 3449 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3450 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL 3451 #define SQ_RDMA_FLAGS_SE 0x8UL 3452 #define SQ_RDMA_FLAGS_INLINE 0x10UL 3453 #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL 3454 #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL 3455 u8 wqe_size; 3456 u8 reserved8; 3457 __le32 imm_data; 3458 __le32 length; 3459 __le32 reserved32_1; 3460 __le64 remote_va; 3461 __le32 remote_key; 3462 __le32 timestamp; 3463 #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL 3464 #define SQ_RDMA_TIMESTAMP_SFT 0 3465 __le32 data[24]; 3466 }; 3467 3468 /* sq_rdma_hdr (size:256b/32B) */ 3469 struct sq_rdma_hdr { 3470 u8 wqe_type; 3471 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL 3472 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL 3473 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL 3474 #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE 3475 u8 flags; 3476 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3477 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3478 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL 3479 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3480 #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL 3481 #define SQ_RDMA_HDR_FLAGS_SE 0x8UL 3482 #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL 3483 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL 3484 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL 3485 u8 wqe_size; 3486 u8 reserved8; 3487 __le32 imm_data; 3488 __le32 length; 3489 __le32 reserved32_1; 3490 __le64 remote_va; 3491 __le32 remote_key; 3492 __le32 timestamp; 3493 #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL 3494 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 3495 }; 3496 3497 /* sq_atomic (size:1024b/128B) */ 3498 struct sq_atomic { 3499 u8 wqe_type; 3500 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL 3501 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL 3502 #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 3503 u8 flags; 3504 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3505 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3506 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL 3507 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3508 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL 3509 #define SQ_ATOMIC_FLAGS_SE 0x8UL 3510 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL 3511 #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL 3512 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL 3513 __le16 reserved16; 3514 __le32 remote_key; 3515 __le64 remote_va; 3516 __le64 swap_data; 3517 __le64 cmp_data; 3518 __le32 data[24]; 3519 }; 3520 3521 /* sq_atomic_hdr (size:256b/32B) */ 3522 struct sq_atomic_hdr { 3523 u8 wqe_type; 3524 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL 3525 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL 3526 #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 3527 u8 flags; 3528 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3529 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3530 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL 3531 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3532 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL 3533 #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL 3534 #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL 3535 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL 3536 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL 3537 __le16 reserved16; 3538 __le32 remote_key; 3539 __le64 remote_va; 3540 __le64 swap_data; 3541 __le64 cmp_data; 3542 }; 3543 3544 /* sq_localinvalidate (size:1024b/128B) */ 3545 struct sq_localinvalidate { 3546 u8 wqe_type; 3547 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL 3548 #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 3549 u8 flags; 3550 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\ 3551 0xffUL 3552 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3553 0 3554 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL 3555 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3556 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL 3557 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL 3558 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL 3559 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL 3560 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL 3561 __le16 reserved16; 3562 __le32 inv_l_key; 3563 __le64 reserved64; 3564 u8 reserved128[16]; 3565 __le32 data[24]; 3566 }; 3567 3568 /* sq_localinvalidate_hdr (size:256b/32B) */ 3569 struct sq_localinvalidate_hdr { 3570 u8 wqe_type; 3571 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL 3572 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 3573 u8 flags; 3574 #define \ 3575 SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3576 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\ 3577 0 3578 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL 3579 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3580 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL 3581 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL 3582 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL 3583 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL 3584 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL 3585 __le16 reserved16; 3586 __le32 inv_l_key; 3587 __le64 reserved64; 3588 u8 reserved128[16]; 3589 }; 3590 3591 /* sq_fr_pmr (size:1024b/128B) */ 3592 struct sq_fr_pmr { 3593 u8 wqe_type; 3594 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL 3595 #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR 3596 u8 flags; 3597 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL 3598 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3599 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL 3600 #define SQ_FR_PMR_FLAGS_SE 0x8UL 3601 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL 3602 #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL 3603 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL 3604 u8 access_cntl; 3605 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3606 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL 3607 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3608 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3609 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3610 u8 zero_based_page_size_log; 3611 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL 3612 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 3613 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3614 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3615 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3616 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3617 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3618 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3619 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3620 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3621 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3622 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3623 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3624 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3625 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3626 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3627 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3628 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3629 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3630 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3631 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3632 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3633 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3634 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3635 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3636 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3637 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3638 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3639 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3640 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3641 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3642 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3643 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3644 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3645 #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 3646 #define SQ_FR_PMR_ZERO_BASED 0x20UL 3647 __le32 l_key; 3648 u8 length[5]; 3649 u8 reserved8_1; 3650 u8 reserved8_2; 3651 u8 numlevels_pbl_page_size_log; 3652 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3653 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 3654 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3655 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3656 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3657 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3658 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3659 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3660 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3661 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3662 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3663 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3664 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3665 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3666 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3667 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3668 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3669 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3670 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3671 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3672 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3673 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3674 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3675 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3676 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3677 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3678 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3679 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3680 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3681 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3682 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3683 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3684 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3685 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3686 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3687 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL 3688 #define SQ_FR_PMR_NUMLEVELS_SFT 6 3689 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3690 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6) 3691 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6) 3692 #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 3693 __le64 pblptr; 3694 __le64 va; 3695 __le32 data[24]; 3696 }; 3697 3698 /* sq_fr_pmr_hdr (size:256b/32B) */ 3699 struct sq_fr_pmr_hdr { 3700 u8 wqe_type; 3701 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL 3702 #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 3703 u8 flags; 3704 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL 3705 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3706 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL 3707 #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL 3708 #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL 3709 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL 3710 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL 3711 u8 access_cntl; 3712 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3713 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3714 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3715 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3716 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3717 u8 zero_based_page_size_log; 3718 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL 3719 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 3720 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3721 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3722 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3723 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3724 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3725 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3726 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3727 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3728 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3729 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3730 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3731 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3732 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3733 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3734 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3735 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3736 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3737 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3738 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3739 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3740 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3741 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3742 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3743 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3744 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3745 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3746 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3747 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3748 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3749 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3750 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3751 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3752 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 3753 #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL 3754 __le32 l_key; 3755 u8 length[5]; 3756 u8 reserved8_1; 3757 u8 reserved8_2; 3758 u8 numlevels_pbl_page_size_log; 3759 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL 3760 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 3761 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL 3762 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL 3763 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL 3764 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL 3765 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL 3766 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL 3767 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL 3768 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL 3769 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL 3770 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL 3771 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL 3772 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL 3773 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL 3774 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL 3775 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL 3776 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL 3777 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL 3778 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL 3779 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL 3780 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL 3781 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL 3782 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL 3783 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL 3784 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL 3785 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL 3786 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL 3787 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL 3788 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL 3789 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL 3790 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL 3791 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL 3792 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL 3793 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 3794 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL 3795 #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 3796 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6) 3797 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6) 3798 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6) 3799 #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 3800 __le64 pblptr; 3801 __le64 va; 3802 }; 3803 3804 /* sq_bind (size:1024b/128B) */ 3805 struct sq_bind { 3806 u8 wqe_type; 3807 #define SQ_BIND_WQE_TYPE_BIND 0xeUL 3808 #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND 3809 u8 flags; 3810 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3811 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3812 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL 3813 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3814 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL 3815 #define SQ_BIND_FLAGS_SE 0x8UL 3816 #define SQ_BIND_FLAGS_INLINE 0x10UL 3817 #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL 3818 #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL 3819 u8 access_cntl; 3820 #define \ 3821 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3822 0xffUL 3823 #define \ 3824 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 3825 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3826 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL 3827 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3828 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3829 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL 3830 u8 reserved8_1; 3831 u8 mw_type_zero_based; 3832 #define SQ_BIND_ZERO_BASED 0x1UL 3833 #define SQ_BIND_MW_TYPE 0x2UL 3834 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1) 3835 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1) 3836 #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 3837 u8 reserved8_2; 3838 __le16 reserved16; 3839 __le32 parent_l_key; 3840 __le32 l_key; 3841 __le64 va; 3842 u8 length[5]; 3843 u8 reserved24[3]; 3844 __le32 data[24]; 3845 }; 3846 3847 /* sq_bind_hdr (size:256b/32B) */ 3848 struct sq_bind_hdr { 3849 u8 wqe_type; 3850 #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL 3851 #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND 3852 u8 flags; 3853 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL 3854 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 3855 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL 3856 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL 3857 #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL 3858 #define SQ_BIND_HDR_FLAGS_SE 0x8UL 3859 #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL 3860 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL 3861 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL 3862 u8 access_cntl; 3863 #define \ 3864 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\ 3865 0xffUL 3866 #define \ 3867 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \ 3868 0 3869 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL 3870 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL 3871 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL 3872 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL 3873 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL 3874 u8 reserved8_1; 3875 u8 mw_type_zero_based; 3876 #define SQ_BIND_HDR_ZERO_BASED 0x1UL 3877 #define SQ_BIND_HDR_MW_TYPE 0x2UL 3878 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1) 3879 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1) 3880 #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 3881 u8 reserved8_2; 3882 __le16 reserved16; 3883 __le32 parent_l_key; 3884 __le32 l_key; 3885 __le64 va; 3886 u8 length[5]; 3887 u8 reserved24[3]; 3888 }; 3889 3890 /* rq_wqe (size:1024b/128B) */ 3891 struct rq_wqe { 3892 u8 wqe_type; 3893 #define RQ_WQE_WQE_TYPE_RCV 0x80UL 3894 #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV 3895 u8 flags; 3896 u8 wqe_size; 3897 u8 reserved8; 3898 __le32 reserved32; 3899 __le32 wr_id[2]; 3900 #define RQ_WQE_WR_ID_MASK 0xfffffUL 3901 #define RQ_WQE_WR_ID_SFT 0 3902 u8 reserved128[16]; 3903 __le32 data[24]; 3904 }; 3905 3906 /* rq_wqe_hdr (size:256b/32B) */ 3907 struct rq_wqe_hdr { 3908 u8 wqe_type; 3909 #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL 3910 #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV 3911 u8 flags; 3912 u8 wqe_size; 3913 u8 reserved8; 3914 __le32 reserved32; 3915 __le32 wr_id[2]; 3916 #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL 3917 #define RQ_WQE_HDR_WR_ID_SFT 0 3918 u8 reserved128[16]; 3919 }; 3920 3921 /* cq_base (size:256b/32B) */ 3922 struct cq_base { 3923 __le64 reserved64_1; 3924 __le64 reserved64_2; 3925 __le64 reserved64_3; 3926 u8 cqe_type_toggle; 3927 #define CQ_BASE_TOGGLE 0x1UL 3928 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL 3929 #define CQ_BASE_CQE_TYPE_SFT 1 3930 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1) 3931 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1) 3932 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1) 3933 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 3934 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 3935 #define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1) 3936 #define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1) 3937 #define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1) 3938 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1) 3939 #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1) 3940 #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1) 3941 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1) 3942 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1) 3943 #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF 3944 u8 status; 3945 #define CQ_BASE_STATUS_OK 0x0UL 3946 #define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL 3947 #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL 3948 #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL 3949 #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 3950 #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL 3951 #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL 3952 #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL 3953 #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL 3954 #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL 3955 #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL 3956 #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL 3957 #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL 3958 #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL 3959 #define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL 3960 #define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL 3961 #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR 3962 __le16 reserved16; 3963 __le32 opaque; 3964 }; 3965 3966 /* cq_req (size:256b/32B) */ 3967 struct cq_req { 3968 __le64 qp_handle; 3969 __le16 sq_cons_idx; 3970 __le16 reserved16_1; 3971 __le32 reserved32_2; 3972 __le64 reserved64; 3973 u8 cqe_type_toggle; 3974 #define CQ_REQ_TOGGLE 0x1UL 3975 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL 3976 #define CQ_REQ_CQE_TYPE_SFT 1 3977 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1) 3978 #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ 3979 #define CQ_REQ_PUSH 0x20UL 3980 u8 status; 3981 #define CQ_REQ_STATUS_OK 0x0UL 3982 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL 3983 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL 3984 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL 3985 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL 3986 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 3987 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 3988 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL 3989 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL 3990 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL 3991 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL 3992 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL 3993 #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 3994 __le16 reserved16_2; 3995 __le32 reserved32_1; 3996 }; 3997 3998 /* cq_res_rc (size:256b/32B) */ 3999 struct cq_res_rc { 4000 __le32 length; 4001 __le32 imm_data_or_inv_r_key; 4002 __le64 qp_handle; 4003 __le64 mr_handle; 4004 u8 cqe_type_toggle; 4005 #define CQ_RES_RC_TOGGLE 0x1UL 4006 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL 4007 #define CQ_RES_RC_CQE_TYPE_SFT 1 4008 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1) 4009 #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC 4010 u8 status; 4011 #define CQ_RES_RC_STATUS_OK 0x0UL 4012 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4013 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL 4014 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4015 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4016 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4017 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL 4018 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4019 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL 4020 #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR 4021 __le16 flags; 4022 #define CQ_RES_RC_FLAGS_SRQ 0x1UL 4023 #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL 4024 #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL 4025 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ 4026 #define CQ_RES_RC_FLAGS_IMM 0x2UL 4027 #define CQ_RES_RC_FLAGS_INV 0x4UL 4028 #define CQ_RES_RC_FLAGS_RDMA 0x8UL 4029 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3) 4030 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3) 4031 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE 4032 __le32 srq_or_rq_wr_id; 4033 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4034 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 4035 }; 4036 4037 /* cq_res_ud (size:256b/32B) */ 4038 struct cq_res_ud { 4039 __le16 length; 4040 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL 4041 #define CQ_RES_UD_LENGTH_SFT 0 4042 __le16 cfa_metadata; 4043 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL 4044 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 4045 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL 4046 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL 4047 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 4048 __le32 imm_data; 4049 __le64 qp_handle; 4050 __le16 src_mac[3]; 4051 __le16 src_qp_low; 4052 u8 cqe_type_toggle; 4053 #define CQ_RES_UD_TOGGLE 0x1UL 4054 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL 4055 #define CQ_RES_UD_CQE_TYPE_SFT 1 4056 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1) 4057 #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD 4058 u8 status; 4059 #define CQ_RES_UD_STATUS_OK 0x0UL 4060 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4061 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4062 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4063 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4064 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4065 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4066 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL 4067 #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR 4068 __le16 flags; 4069 #define CQ_RES_UD_FLAGS_SRQ 0x1UL 4070 #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL 4071 #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL 4072 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ 4073 #define CQ_RES_UD_FLAGS_IMM 0x2UL 4074 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL 4075 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 4076 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL 4077 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 4078 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4079 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4080 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4081 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 4082 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL 4083 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 4084 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4085 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 4086 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4087 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4088 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4089 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET 4090 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 4091 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 4092 __le32 src_qp_high_srq_or_rq_wr_id; 4093 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4094 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 4095 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL 4096 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 4097 }; 4098 4099 /* cq_res_ud_v2 (size:256b/32B) */ 4100 struct cq_res_ud_v2 { 4101 __le16 length; 4102 #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL 4103 #define CQ_RES_UD_V2_LENGTH_SFT 0 4104 __le16 cfa_metadata0; 4105 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL 4106 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 4107 #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL 4108 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4109 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 4110 __le32 imm_data; 4111 __le64 qp_handle; 4112 __le16 src_mac[3]; 4113 __le16 src_qp_low; 4114 u8 cqe_type_toggle; 4115 #define CQ_RES_UD_V2_TOGGLE 0x1UL 4116 #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL 4117 #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 4118 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1) 4119 #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD 4120 u8 status; 4121 #define CQ_RES_UD_V2_STATUS_OK 0x0UL 4122 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4123 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4124 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4125 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4126 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4127 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4128 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL 4129 #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 4130 __le16 flags; 4131 #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL 4132 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL 4133 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL 4134 #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ 4135 #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL 4136 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL 4137 #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 4138 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 4139 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 4140 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4141 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4142 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4143 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 4144 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 4145 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 4146 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4147 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 4148 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4149 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4150 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4151 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET 4152 __le32 src_qp_high_srq_or_rq_wr_id; 4153 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4154 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 4155 #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL 4156 #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 4157 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4158 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 4159 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4160 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4161 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4162 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4163 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4164 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4165 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4166 #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL 4167 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL 4168 #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 4169 }; 4170 4171 /* cq_res_ud_cfa (size:256b/32B) */ 4172 struct cq_res_ud_cfa { 4173 __le16 length; 4174 #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL 4175 #define CQ_RES_UD_CFA_LENGTH_SFT 0 4176 __le16 cfa_code; 4177 __le32 imm_data; 4178 __le32 qid; 4179 #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL 4180 #define CQ_RES_UD_CFA_QID_SFT 0 4181 __le32 cfa_metadata; 4182 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL 4183 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 4184 #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL 4185 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL 4186 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 4187 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL 4188 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 4189 __le16 src_mac[3]; 4190 __le16 src_qp_low; 4191 u8 cqe_type_toggle; 4192 #define CQ_RES_UD_CFA_TOGGLE 0x1UL 4193 #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL 4194 #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 4195 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 4196 #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA 4197 u8 status; 4198 #define CQ_RES_UD_CFA_STATUS_OK 0x0UL 4199 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4200 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4201 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4202 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4203 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4204 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4205 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL 4206 #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 4207 __le16 flags; 4208 #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL 4209 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL 4210 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL 4211 #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 4212 #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL 4213 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL 4214 #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 4215 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL 4216 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 4217 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4218 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4219 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4220 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 4221 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL 4222 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 4223 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4224 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6) 4225 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4226 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4227 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4228 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET 4229 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL 4230 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 4231 __le32 src_qp_high_srq_or_rq_wr_id; 4232 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4233 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 4234 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL 4235 #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 4236 }; 4237 4238 /* cq_res_ud_cfa_v2 (size:256b/32B) */ 4239 struct cq_res_ud_cfa_v2 { 4240 __le16 length; 4241 #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL 4242 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 4243 __le16 cfa_metadata0; 4244 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL 4245 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 4246 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL 4247 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4248 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 4249 __le32 imm_data; 4250 __le32 qid; 4251 #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL 4252 #define CQ_RES_UD_CFA_V2_QID_SFT 0 4253 __le32 cfa_metadata2; 4254 __le16 src_mac[3]; 4255 __le16 src_qp_low; 4256 u8 cqe_type_toggle; 4257 #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL 4258 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL 4259 #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 4260 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1) 4261 #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA 4262 u8 status; 4263 #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL 4264 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4265 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4266 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4267 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4268 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4269 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4270 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL 4271 #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 4272 __le16 flags; 4273 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL 4274 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL 4275 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL 4276 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 4277 #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL 4278 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL 4279 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 4280 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL 4281 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 4282 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4) 4283 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4) 4284 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4) 4285 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 4286 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL 4287 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 4288 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6) 4289 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6) 4290 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6) 4291 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6) 4292 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6) 4293 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \ 4294 CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET 4295 __le32 src_qp_high_srq_or_rq_wr_id; 4296 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4297 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 4298 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL 4299 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 4300 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4301 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 4302 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4303 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4304 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4305 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4306 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4307 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4308 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \ 4309 CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4310 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL 4311 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL 4312 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 4313 }; 4314 4315 /* cq_res_raweth_qp1 (size:256b/32B) */ 4316 struct cq_res_raweth_qp1 { 4317 __le16 length; 4318 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL 4319 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 4320 __le16 raweth_qp1_flags; 4321 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4322 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 4323 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL 4324 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4325 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4326 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4327 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4328 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4329 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4330 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4331 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4332 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4333 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4334 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4335 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4336 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4337 __le16 raweth_qp1_errors; 4338 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4339 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4340 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4341 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4342 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4343 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4344 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4345 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4346 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4347 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4348 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4349 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4350 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4351 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4352 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4353 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4354 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4355 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4356 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4357 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4358 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4359 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4360 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4361 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4362 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4363 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12) 4364 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12) 4365 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4366 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4367 __le16 raweth_qp1_cfa_code; 4368 __le64 qp_handle; 4369 __le32 raweth_qp1_flags2; 4370 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL 4371 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL 4372 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL 4373 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL 4374 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4375 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4376 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4377 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4) 4378 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4379 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4380 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4381 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4382 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4383 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4384 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4385 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL 4386 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 4387 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4388 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4389 __le32 raweth_qp1_metadata; 4390 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL 4391 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 4392 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL 4393 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 4394 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL 4395 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL 4396 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 4397 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL 4398 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 4399 u8 cqe_type_toggle; 4400 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL 4401 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL 4402 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 4403 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4404 #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 4405 u8 status; 4406 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL 4407 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4408 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4409 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4410 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4411 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4412 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4413 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL 4414 #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 4415 __le16 flags; 4416 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL 4417 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL 4418 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL 4419 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 4420 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4421 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4422 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 4423 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4424 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4425 }; 4426 4427 /* cq_res_raweth_qp1_v2 (size:256b/32B) */ 4428 struct cq_res_raweth_qp1_v2 { 4429 __le16 length; 4430 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL 4431 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 4432 __le16 raweth_qp1_flags; 4433 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL 4434 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 4435 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL 4436 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL 4437 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 4438 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6) 4439 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6) 4440 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6) 4441 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6) 4442 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6) 4443 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6) 4444 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6) 4445 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6) 4446 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6) 4447 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \ 4448 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP 4449 __le16 raweth_qp1_errors; 4450 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL 4451 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL 4452 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL 4453 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL 4454 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL 4455 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL 4456 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 4457 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9) 4458 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9) 4459 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9) 4460 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9) 4461 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9) 4462 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9) 4463 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9) 4464 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \ 4465 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL 4466 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL 4467 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 4468 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12) 4469 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12) 4470 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12) 4471 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12) 4472 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12) 4473 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12) 4474 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12) 4475 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ 4476 (0x7UL << 12) 4477 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ 4478 (0x8UL << 12) 4479 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \ 4480 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN 4481 __le16 cfa_metadata0; 4482 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL 4483 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 4484 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL 4485 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL 4486 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 4487 __le64 qp_handle; 4488 __le32 raweth_qp1_flags2; 4489 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL 4490 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL 4491 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 4492 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4) 4493 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4) 4494 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4) 4495 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4) 4496 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4) 4497 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \ 4498 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET 4499 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL 4500 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL 4501 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL 4502 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 4503 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL 4504 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 4505 __le32 cfa_metadata2; 4506 u8 cqe_type_toggle; 4507 #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL 4508 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL 4509 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 4510 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1) 4511 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 4512 u8 status; 4513 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL 4514 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL 4515 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL 4516 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL 4517 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL 4518 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL 4519 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL 4520 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL 4521 #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 4522 __le16 flags; 4523 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL 4524 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL 4525 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL 4526 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 4527 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id; 4528 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL 4529 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 4530 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL 4531 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 4532 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL 4533 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 4534 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20) 4535 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20) 4536 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20) 4537 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20) 4538 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20) 4539 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20) 4540 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \ 4541 CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG 4542 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL 4543 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL 4544 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 4545 }; 4546 4547 /* cq_terminal (size:256b/32B) */ 4548 struct cq_terminal { 4549 __le64 qp_handle; 4550 __le16 sq_cons_idx; 4551 __le16 rq_cons_idx; 4552 __le32 reserved32_1; 4553 __le64 reserved64_3; 4554 u8 cqe_type_toggle; 4555 #define CQ_TERMINAL_TOGGLE 0x1UL 4556 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL 4557 #define CQ_TERMINAL_CQE_TYPE_SFT 1 4558 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1) 4559 #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL 4560 u8 status; 4561 #define CQ_TERMINAL_STATUS_OK 0x0UL 4562 #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK 4563 __le16 reserved16; 4564 __le32 reserved32_2; 4565 }; 4566 4567 /* cq_cutoff (size:256b/32B) */ 4568 struct cq_cutoff { 4569 __le64 reserved64_1; 4570 __le64 reserved64_2; 4571 __le64 reserved64_3; 4572 u8 cqe_type_toggle; 4573 #define CQ_CUTOFF_TOGGLE 0x1UL 4574 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL 4575 #define CQ_CUTOFF_CQE_TYPE_SFT 1 4576 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1) 4577 #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF 4578 #define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL 4579 #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 4580 u8 status; 4581 #define CQ_CUTOFF_STATUS_OK 0x0UL 4582 #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK 4583 __le16 reserved16; 4584 __le32 reserved32; 4585 }; 4586 4587 /* nq_base (size:128b/16B) */ 4588 struct nq_base { 4589 __le16 info10_type; 4590 #define NQ_BASE_TYPE_MASK 0x3fUL 4591 #define NQ_BASE_TYPE_SFT 0 4592 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL 4593 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL 4594 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL 4595 #define NQ_BASE_TYPE_QP_EVENT 0x38UL 4596 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL 4597 #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT 4598 #define NQ_BASE_INFO10_MASK 0xffc0UL 4599 #define NQ_BASE_INFO10_SFT 6 4600 __le16 info16; 4601 __le32 info32; 4602 __le32 info63_v[2]; 4603 #define NQ_BASE_V 0x1UL 4604 #define NQ_BASE_INFO63_MASK 0xfffffffeUL 4605 #define NQ_BASE_INFO63_SFT 1 4606 }; 4607 4608 /* nq_cn (size:128b/16B) */ 4609 struct nq_cn { 4610 __le16 type; 4611 #define NQ_CN_TYPE_MASK 0x3fUL 4612 #define NQ_CN_TYPE_SFT 0 4613 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 4614 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 4615 #define NQ_CN_TOGGLE_MASK 0xc0UL 4616 #define NQ_CN_TOGGLE_SFT 6 4617 __le16 reserved16; 4618 __le32 cq_handle_low; 4619 __le32 v; 4620 #define NQ_CN_V 0x1UL 4621 __le32 cq_handle_high; 4622 }; 4623 4624 /* nq_srq_event (size:128b/16B) */ 4625 struct nq_srq_event { 4626 u8 type; 4627 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL 4628 #define NQ_SRQ_EVENT_TYPE_SFT 0 4629 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL 4630 #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT 4631 #define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL 4632 #define NQ_SRQ_EVENT_TOGGLE_SFT 6 4633 u8 event; 4634 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL 4635 #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 4636 __le16 reserved16; 4637 __le32 srq_handle_low; 4638 __le32 v; 4639 #define NQ_SRQ_EVENT_V 0x1UL 4640 __le32 srq_handle_high; 4641 }; 4642 4643 /* nq_dbq_event (size:128b/16B) */ 4644 struct nq_dbq_event { 4645 u8 type; 4646 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL 4647 #define NQ_DBQ_EVENT_TYPE_SFT 0 4648 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL 4649 #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT 4650 u8 event; 4651 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL 4652 #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 4653 __le16 db_pfid; 4654 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL 4655 #define NQ_DBQ_EVENT_DB_PFID_SFT 0 4656 __le32 db_dpi; 4657 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL 4658 #define NQ_DBQ_EVENT_DB_DPI_SFT 0 4659 __le32 v; 4660 #define NQ_DBQ_EVENT_V 0x1UL 4661 __le32 db_type_db_xid; 4662 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL 4663 #define NQ_DBQ_EVENT_DB_XID_SFT 0 4664 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL 4665 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 4666 }; 4667 4668 /* xrrq_irrq (size:256b/32B) */ 4669 struct xrrq_irrq { 4670 __le16 credits_type; 4671 #define XRRQ_IRRQ_TYPE 0x1UL 4672 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL 4673 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL 4674 #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ 4675 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL 4676 #define XRRQ_IRRQ_CREDITS_SFT 11 4677 __le16 reserved16; 4678 __le32 reserved32; 4679 __le32 psn; 4680 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL 4681 #define XRRQ_IRRQ_PSN_SFT 0 4682 __le32 msn; 4683 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL 4684 #define XRRQ_IRRQ_MSN_SFT 0 4685 __le64 va_or_atomic_result; 4686 __le32 rdma_r_key; 4687 __le32 length; 4688 }; 4689 4690 /* xrrq_orrq (size:256b/32B) */ 4691 struct xrrq_orrq { 4692 __le16 num_sges_type; 4693 #define XRRQ_ORRQ_TYPE 0x1UL 4694 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL 4695 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL 4696 #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ 4697 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL 4698 #define XRRQ_ORRQ_NUM_SGES_SFT 11 4699 __le16 reserved16; 4700 __le32 length; 4701 __le32 psn; 4702 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL 4703 #define XRRQ_ORRQ_PSN_SFT 0 4704 __le32 end_psn; 4705 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL 4706 #define XRRQ_ORRQ_END_PSN_SFT 0 4707 __le64 first_sge_phy_or_sing_sge_va; 4708 __le32 single_sge_l_key; 4709 __le32 single_sge_size; 4710 }; 4711 4712 /* ptu_pte (size:64b/8B) */ 4713 struct ptu_pte { 4714 __le32 page_next_to_last_last_valid[2]; 4715 #define PTU_PTE_VALID 0x1UL 4716 #define PTU_PTE_LAST 0x2UL 4717 #define PTU_PTE_NEXT_TO_LAST 0x4UL 4718 #define PTU_PTE_UNUSED_MASK 0xff8UL 4719 #define PTU_PTE_UNUSED_SFT 3 4720 #define PTU_PTE_PAGE_MASK 0xfffff000UL 4721 #define PTU_PTE_PAGE_SFT 12 4722 }; 4723 4724 /* ptu_pde (size:64b/8B) */ 4725 struct ptu_pde { 4726 __le32 page_valid[2]; 4727 #define PTU_PDE_VALID 0x1UL 4728 #define PTU_PDE_UNUSED_MASK 0xffeUL 4729 #define PTU_PDE_UNUSED_SFT 1 4730 #define PTU_PDE_PAGE_MASK 0xfffff000UL 4731 #define PTU_PDE_PAGE_SFT 12 4732 }; 4733 4734 #endif /* ___BNXT_RE_HSI_H__ */ 4735